TW201448134A - 包含導電底部塡充材料之半導體裝置及封裝以及相關方法 - Google Patents

包含導電底部塡充材料之半導體裝置及封裝以及相關方法 Download PDF

Info

Publication number
TW201448134A
TW201448134A TW103111304A TW103111304A TW201448134A TW 201448134 A TW201448134 A TW 201448134A TW 103111304 A TW103111304 A TW 103111304A TW 103111304 A TW103111304 A TW 103111304A TW 201448134 A TW201448134 A TW 201448134A
Authority
TW
Taiwan
Prior art keywords
substrate
conductive structures
semiconductor
semiconductor device
electrically
Prior art date
Application number
TW103111304A
Other languages
English (en)
Other versions
TWI538120B (zh
Inventor
Jaspreet S Gandhi
Luke G England
Owen R Fay
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of TW201448134A publication Critical patent/TW201448134A/zh
Application granted granted Critical
Publication of TWI538120B publication Critical patent/TWI538120B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165—Material
    • H01L2224/16505—Material outside the bonding interface, e.g. in the bulk of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/175—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29301—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29309—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29301—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29311—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29301—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29316—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29317—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29324—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29344—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29347—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29499—Shape or distribution of the fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32052—Shape in top view
    • H01L2224/32054—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/3301—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/335—Material
    • H01L2224/33505—Layer connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024—Applying flux to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81122—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors by detecting inherent features of, or outside, the semiconductor or solid-state body
    • H01L2224/81125—Bonding areas on the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/81948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83874—Ultraviolet [UV] curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

半導體裝置及裝置封裝包含透過複數個導電結構而電耦合至一基板之至少一半導體晶粒。該至少一半導體晶粒可為複數個記憶體晶粒，且該基板可為一邏輯晶粒。安置於該至少一半導體晶粒與該基板之間之一底部填充材料可包含一熱傳導材料。一電絕緣材料經安置於該複數個導電結構與該底部填充材料之間。諸如用於形成半導體裝置封裝之將一半導體晶粒附接至一基板的方法包含覆蓋或塗佈導電結構的至少一外側表面、使用一電絕緣材料來將該半導體晶粒電耦合至該基板，及在該半導體晶粒與該基板之間安置一熱傳導材料。

Description

包含導電底部填充材料之半導體裝置及封裝以及相關方法 [優先權聲明]
本申請案主張2013年3月27日提交之名稱為「SEMICONDUCTOR DEVICES AND PACKAGES INCLUDING CONDUCTIVE UNDERFILL MATERIAL AND RELATED METHODS」之美國專利申請案號13/851,788之權利。
本發明之實施例係關於用於將一半導體裝置機械及電連接至一基板(諸如使用一導電底部填充材料來將具有基節導電結構(例如焊球、金屬支柱)之一半導體裝置連接至一基板或另一半導體裝置)之封裝技術。
在電子工業中存在一趨勢以減小電子裝置之組件之大小。此一尺寸上之減小可實現除了其他優點之外之成本減小、效率增加及更低能量需求。半導體裝置封裝(例如記憶體、處理器、發光二極體(LED)、微機電系統(MEMS)裝置封裝、其等之組合)已成為各種尺寸減小努力之對象。例如，減小由一半導體裝置封裝覆蓋之一區域之一方法包含將多個半導體裝置堆疊彼此上方且透過矽通孔(TSV)來使用以將多個半導體裝置電耦合至一下伏基板。
一些習知半導體裝置封裝包含導電結構(例如錫焊凸塊、銅柱)，其等將半導體裝置彼此電耦合及/或電耦合至一下伏基板。一底部填充材料安置於半導體裝置之間之一容積中以將物理穩定性添加至封裝且以保護(諸如藉由形成一防潮層)導電結構免於環境損害。儘管可包含添加劑及填充材料以更改底部填充材料之機械、化學及/或熱性質，然習知底部填充材料主要為介電材料(諸如聚合物)。
半導體裝置在操作期間產生非所要量之熱量。例如，已知邏輯裝置(例如處理器)、動態隨機存取記憶體(DRAM)裝置及互補金氧半導體(CMOS)裝置以在操作期間產生顯著熱量。若此等裝置使用其他半導體裝置來堆疊或由其等覆蓋，且使用一蓋子來囊封、覆蓋(或兩者)(諸如在包括多個半導體裝置之一半導體裝置封裝中)，則在半導體裝置之一或多者內，熱量可被陷留，且溫度可上升至不可接受之位準。將熱量自半導體裝置轉移，且一半導體裝置封裝中之基板可改良半導體裝置之效能，且可減小對半導體裝置之熱致損害之可能。
吾人已知使用包含一環氧成份及一助焊劑成份之環氧助焊劑以在半導體裝置之導電元件與一基板之焊墊之間之電連接之形成期間將氧化物自一半導體裝置之導電元件(例如導電結構、焊球)移除。當在形成電連接時(或之後)，諸如藉由透過加熱之蒸發而移除助焊劑成份。環氧助焊劑之環氧成份可同時或隨後經固化以形成可在結構上加固將半導體裝置結合至基板之一固體環氧樹脂。然而，環氧樹脂之熱阻相對較高(即環氧樹脂一般不是一良好熱導體)，且熱量可由熱絕緣環氧樹脂保留於封裝之一半導體裝置中。此熱量可損害及/或減少半導體裝置封裝之效能。
已將填充劑添加至底部填充材料以透過底部填充材料而增加熱傳導。例如，已將一陶瓷材料之顆粒用作一填充劑以透過底部填充材料而改良熱轉移。然而，陶瓷填充劑(諸如氮化鋁及氮化硼)難以依一 球形形式產生，且當依薄片形式被採用時，可在達成一均勻的可接受薄度的結合線中存在難度，且可穿孔於(例如鈍化)保護層。導電顆粒(例如金屬顆粒)(其可展現比陶瓷顆粒或其他電絕緣顆粒更大之導熱性)一般避免作為填充劑或用於受限濃度中以抑制一半導體裝置封裝之鄰近導電結構之間之非所要電連通(例如短路)。
100‧‧‧半導體晶粒
102‧‧‧導電結構
104‧‧‧導電墊
106‧‧‧挑頭
108‧‧‧液體容器
110‧‧‧液體環氧助焊劑
110A‧‧‧經硬化環氧
112‧‧‧基板
114‧‧‧焊墊/終端墊
116‧‧‧焊錫遮罩
120‧‧‧箭頭
130‧‧‧底部填充材料
200‧‧‧半導體裝置封裝
201A‧‧‧半導體記憶體晶粒
201B‧‧‧半導體記憶體晶粒
201C‧‧‧半導體記憶體晶粒
201D‧‧‧半導體記憶體晶粒
201E‧‧‧半導體記憶體晶粒
201F‧‧‧半導體記憶體晶粒
201G‧‧‧半導體記憶體晶粒
201H‧‧‧半導體記憶體晶粒
202‧‧‧第一複數個導電結構/第二複數個導電結構
210‧‧‧電絕緣材料
212‧‧‧半導體邏輯晶粒
222‧‧‧印刷電路板(PCB)
224‧‧‧第三複數個導電結構
226‧‧‧第四複數個導電結構
228‧‧‧散熱元件
230‧‧‧底部填充材料
232‧‧‧熱介面材料(TIM)
D‧‧‧深度
L‧‧‧長度
圖1至圖7繪示一種根據本發明之一實施例之將一半導體晶粒附接至一基板以形成一半導體裝置封裝之方法。
圖1至圖3繪示一種根據本發明之一實施例之用於使用一環氧助焊劑來塗佈半導體晶粒之基節導電結構之程序。
圖4繪示其中經塗佈之半導體晶粒之基節導電結構與基板之焊墊對準之定位於基板上方之半導體晶粒。
圖5繪示放置於其中經塗佈之基節導電結構定位於基板之焊墊上方之基板上之半導體晶粒。
圖6繪示形成至基板之導電特徵之一電連接之基節導電結構。
圖7繪示包含安置於半導體晶粒與基板之間之一容積中之一底部填充材料之半導體裝置封裝之一部分。
圖8係根據本發明之一實施例之沿圖7之線I-I取得之圖7之半導體裝置封裝之部分之一橫截面俯視圖。
圖9係根據本發明之另一實施例之類似於圖8之一半導體裝置封裝之一部分之一橫截面俯視圖。
圖10係根據本發明之一實施例之一半導體裝置封裝之一橫截面側視圖。
如文中所使用，參考一給定參數之術語「實質上」意指且包含一般技術者將瞭解給定參數、性質或條件滿足變異之一較小程度(諸 如在可接受製造容限內)之一程度。經由實例且無限制，「實質上」滿足之一參數可至少約90%滿足、至少約95%滿足或甚至至少約99%滿足。
如文中所使用，任何相關術語(諸如「第一」、「第二」、「在上方」、「在上面」、「頂部」、「底部」、「垂直」、「橫向」等等)用於清晰及方便理解本發明及附圖，且不意味或取決於除了內文另外清晰指示之處之外之任何特性偏好、定向或順序。
以下描述提供特定細節，諸如材料類型及處理條件，以便提供本發明之實施例之一透徹描述。然而，一般技術者將瞭解，本發明之實施例可在不採用此等特性細節之情況下實施。當然，本發明之實施例可結合工業中所採用之習知半導體製造技術而實施。另外，下文所提供之描述可能無法形成用於製造半導體裝置及封裝之一完整程序流程。下文所描述之結構無需形成完整半導體裝置或封裝。在下文詳細描述理解本發明之實施例僅需之該等程序行為及結構。形成完整半導體裝置、封裝及系統之額外行為可由習知製造技術而執行。據此，在文中描述理解本發明之實施例僅需之方法及半導體裝置結構。
在以下詳細描述中，對附圖進行參考，該等附圖就此形成一部分，且其中經由繪示來展示其中可實施本發明之特定實施例。足夠詳細地描述此等實施例，以使得一般技術者能夠實施本發明。然而，可利用其他實施例，且可在不背離本發明之範疇的情況下做出結構、邏輯、方法及組合改變。文中所呈現之說明不意指任何特性系統、裝置、結構或封裝之真實圖式，而僅為經採用以描述本發明之實施例之經理想化的表示。文中所呈現之圖式無需按照比例繪製。另外，圖式之間之共同元件可保留相同數值名稱。然而，編號中之任何相似性不意指結構或組件需要在尺寸、成份、組態或其他性質上相同。
本發明之實施例包含(例如)將一半導體晶粒電及機械連接至一基 板(諸如另一半導體晶粒(例如一記憶體晶粒、一邏輯晶粒)、一印刷電路板、一插入器等等)之方法，用以形成一半導體裝置封裝。該等方法包含使用一底部填充材料，其可包含熱傳導及導電填充材料以促進透過底部填充材料之熱量轉移。使用此一底部填充材料可在半導體晶粒及基板之至少一者中維持一足夠低之溫度，以改良或維持其之效能及可靠性。另外，本發明之實施例包含使用此等底部填充材料來形成一半導體裝置封裝之方法。為避免或減少用於將半導體晶粒連接至基板之導電結構(例如錫焊凸塊、導電支柱、金屬支柱、銅柱)之間的電短路，在將底部填充材料引入半導體晶粒與基板之間之一容積中之前，導電結構可至少部分塗佈有一環氧助焊劑。環氧助焊劑之一環氧成份可在導電結構與任何鄰近導電底部填充材料之間形成一電絕緣障壁。本發明之方法可尤其對將一半導體晶粒附接至一基板(其中複數個基節導電結構用於形成半導體晶粒與基板之間之電連接)有用。因此，本發明之實施例可實現底部填充材料中之導電填充材料(例如金屬填充材料)的使用，以實質上增強導熱性。
圖1至圖7繪示一種將一半導體晶粒100附接至一基板之方法。參考圖1，半導體晶粒100可為一習知半導體晶粒，其包含(例如)一動態隨機存取記憶體(DRAM)晶粒、一快閃晶粒、一邏輯晶粒(例如一處理器晶粒)、一互補金氧半導體(CMOS)晶粒等等。因此，本發明之方法不限於任何特性類型之半導體晶粒100。半導體晶粒100可包含自一主要表面突出以用於將半導體晶粒100附接及電耦合至一基板之複數個導電結構102。經由實例且無限制，導電結構102之各者可為形成於半導體晶粒100之一對應導電墊104上之一導電凸塊或支柱，諸如一錫焊凸塊(例如包含一銀錫合金之一凸塊)、一金屬支柱、一銅柱、一焊料尖頭金屬支柱等等。導電結構102可(例如)跨半導體晶粒100之一主要表面而配置於一所謂的「球形陣列」(BGA)中。
在一些實施例中，複數個導電結構102可形成於一基節處。節距係用於描述鄰近(例如重複)特徵之一大小之一概念，且一般被定義為一特徵之一寬度加上該特徵與一緊鄰特徵之間之一距離。如文中所使用，片語「基節」係指具有一相對較小節距之特徵。因此，形成於一基節處之導電結構102可為相對較小導電結構102及/或相對接近彼此而定位。經由實例且無限制，本發明之導電結構102可具有約1000微米或更少之一節距，諸如在約40微米與約500微米之間。在一些實施例中，導電結構102可具有在約40微米與約100微米之間之一節距。在其他實施例中，複數個導電結構102可形成於一增大之節距處(即未在一基節處)。當然，所列出之節距值僅作為實例而提供，且本發明之實施例可包含在所列出之值以上或以下之節距。
如圖1中所示，半導體晶粒100可(諸如)藉由一真空力由一所謂的「取置」裝置之一挑頭106固持於與導電結構102相反之半導體晶粒100之一側上。挑頭106可用於將半導體晶粒100定位於包含一液體環氧助焊劑110之一水槽之一液體容器108(例如一所謂的「助焊劑托盤」)上方。液體環氧助焊劑110可包含一環氧成份及一助焊劑成份。環氧成份可包含(例如)一環氧樹脂及一環氧固化劑。環氧樹脂可為一電絕緣材料。助焊劑成份可為用於在一結合程序期間移除或抑制在導電結構102之一表面上之一金屬氧化物之形成之一化學成份，如一般技術者所知。例如，助焊劑成份可包含一羧酸。其他習知成份可包含於液體環氧材料110中，諸如一膠粘劑成份、一增稠劑、一催化劑材料、一助流劑、一助黏劑、一染料等等。
環氧助焊劑110可為商業上可購得或可針對一特定應用而被特別配製。在一些實施例中，可作為環氧助焊劑110使用之商業上可購得之材料之實例包含以下：可自德國杜塞爾多夫之Henkel Corporation購得之部件號FF6000；可自喬治亞州薩沃尼之Alpha Advanced Materials 購得之商標STAYCHIPTM PRL 50-5D之材料；可自日本東京之Senju Metal Industry Co.,Ltd.購得之商標JPK8之材料；可自北卡羅萊納州喀里之LORD Corporation購得之商標EXP10067之材料；及可自伊利諾斯州伊塔斯加之Kester,Inc.購得之商標JL-8-22-4及JL8-106-1兩者之材料。
參考圖2，挑頭106可經降低以定位導電結構102以在液體容器108中至少部分與液體環氧助焊劑110接觸。液體容器108之一深度D(圖1)可與導電結構102自半導體晶粒100之主要表面延伸之一距離L(圖1)相關，且與待以塗佈導電結構102之液體環氧助焊劑110之所要容積相關。可基於在半導體晶粒100與一基板(半導體晶粒100待被結合至其)之間之一所要結合線厚度而選擇導電結構102自半導體晶粒100之主要表面延伸之長度L，如下文更詳細討論。在一些實施例中，深度D可小於長度L以使得半導體晶粒100能夠被降低(或升高液體容器108)直到導電結構102接觸液體容器108之一底部。在其他實施例中，深度D可大於長度L，且半導體晶粒100可被降低(或可升高液體容器108)直到所要量之導電結構102及/或半導體晶粒100之主要表面由液體環氧助焊劑110接觸。若深度D大於長度L，則半導體晶粒100可被降低(或可升高液體容器108)直到在導電結構102之橫向外部之半導體晶粒100之主要表面接觸液體容器108之一頂面。
液體容器108中之液體環氧助焊劑110之粘度及黏性可經調整以使得所要量之液體環氧助焊劑110能夠形成於導電結構102且使得導電結構102能夠浸漬於液體環氧助焊劑110中且能夠在不陷入液體環氧助焊劑110中之情況下被移除。例如，液體環氧助焊劑110可經加熱以減小其之粘度或經冷卻以增大其之粘度。替代地或另外，液體環氧助焊劑110之化學成份可經選擇使得液體環氧助焊劑110展現一所要粘度及黏性。另外，可更改導電結構102定位於液體容器108中之大量時間以更 改形成於導電結構102上之液體環氧助焊劑110之一容積。
參考圖3，挑頭106可被抬起以自液體容器108移除導電結構102。導電結構102之外表面之至少一部分可由液體環氧助焊劑110之一容積覆蓋。如圖3中所示，各導電結構102可至少部分由液體環氧助焊劑110之一單獨容積覆蓋。在其他實施例中，液體環氧助焊劑110亦可在導電結構102之間(諸如在導電結構102之間之半導體晶粒100之主要表面上)形成，使得液體環氧助焊劑110之一單一連續容積可覆蓋導電結構102之一者以上或甚至全部。
儘管已參考藉由將導電結構102浸入液體容器108中之液體環氧助焊劑110中而使用液體環氧助焊劑110來覆蓋導電結構102而描述圖1至圖3，然本發明並非如此受限。例如，在其他實施例中，液體環氧助焊劑110可(例如)藉由將液體環氧助焊劑110噴射於導電結構102上方、將液體環氧助焊劑110列印於導電結構上方或在導電結構102上形成一液體環氧材料的任何其他方法而形成於導電結構102上方。
參考圖4，在液體環氧助焊劑110之一容積形成於導電結構102之至少一部分上之後，半導體晶粒100可被定位於一基板112上方，且導電結構102可與基板112之各自焊墊114對準。基板112可為半導體晶粒100與其實體及電耦合的任何基板。經由實例且無限制，基板112可為一印刷電路板(PCB)、一插入器、一邏輯晶粒、一處理器晶粒、一引線框或實質上類似於半導體晶粒100之另一半導體晶粒。基板112可包含焊墊114，其等在基板為一PCB或任何插入器之情況下可替代地被特性化為終端墊114，經配置於對應於複數個導電結構102之一圖案之一圖案中。另外，基板可包含一錫焊遮罩116(例如經組態以抑制錫焊材料圍繞焊墊114橫向流動之一介電材料)。基板112亦可包含其他組件、結構及材料，諸如(取決於基板112之結構及功能且無限制)電晶體、電容器、介電材料、導電線路、導電通孔、一重分配層、一累積 層、一鈍化層等等，如技術中已知。
參考圖5，半導體晶粒100可被放置於基板112上。導電結構102可被放置於焊墊114上，且透過液體環氧助焊劑110接觸焊墊114。若液體環氧助焊劑110可足以流動，則半導體晶粒100之重量、挑頭106之力或其等之一組合可使得液體環氧助焊劑110流動，且導電結構102之一或多者可直接接觸一各自一或多個焊墊114。如圖5中所示，在將半導體晶粒100放置於基板112上之後，挑頭106可釋放半導體晶粒100且被撤出。
參考圖6，半導體晶粒100可透過複數個導電結構102來電耦合至基板112，該等導電結構112可經定位於半導體晶粒100與基板112之間之一容積中。經由非限制實例，半導體晶粒100可被壓向基板112(如使用表示施力之箭頭120所示)，以使得導電結構102實體及電接觸焊墊114。在一些實施例中，熱量亦可被施加至結構以至少部分軟化或熔化導電結構102或其之部分，從而在導電結構102與焊墊114之間形成一結合。當導電結構102被壓於焊墊114上及/或被熔化時，液體環氧助焊劑110可自結合介面流走，且流向導電結構102之外側表面。因此，導電結構102與焊墊114之間之一結合介面可實質上無環氧助焊劑110，使得可在導電結構102與各自焊墊114之間形成一直接實體及電結合。另外，液體環氧助焊劑110可沿導電結構102之外側表面，自焊錫遮罩116實質上連續延伸至面向容積之半導體晶粒100之一主要表面，以圍繞導電結構102之各者形成一障壁。
導電結構102與焊墊114之間之實體結合之形成可形成複數個機械及電連接，該等連接透過導電結構102自導電墊104延伸且至焊墊114。因此，亦提供機械附接點之電連通路徑可透過導電結構102而在半導體晶粒100與基板112之間建立。
熱量可被施加至圖6中所繪示之結構以至少部分固化液體環氧助 焊劑110。熱量可包含一化學反應以交叉連接環氧樹脂成份。此交叉連接可硬化及機械強化環氧助焊劑110之環氧成份。另外，環氧助焊劑110之任何揮發性成份(諸如助焊劑成份)可當暴露於固化程序之熱量中時至少部分蒸發。歸因於助焊劑成份及(可能)其他成份之損耗，環氧助焊劑110可在容積、厚度及質量上縮小。例如，在施加熱量及固化環氧助焊劑110之後剩餘之環氧助焊劑110之環氧成份可當最初應用於導電結構102時在環氧助焊劑110之約10重量%與約25%重量之間。因此，環氧助焊劑110可藉由施加熱量而自液體環氧助焊劑110轉換成一經硬化環氧110A(見圖7至圖9)。
在一些實施例中，可將熱量之至少一部分施加至結構，同時半導體晶粒100被壓向基板112，諸如在一所謂的「熱壓縮」程序中。在其他實施例中，可將足夠熱量施加至結構以在一所謂的「回焊」程序中熔化或軟化導電結構102或其等之部分，該程序可涉及在比熱壓縮程序更長之時間量內施加熱量。回焊程序可結合或不結合朝向基板112之半導體晶粒100施力(由箭頭120指示)而執行。在一些實施例中，可在半導體晶粒100被壓向基板112之後施加額外熱量(熱壓縮程序及/或回焊程序)以更完全固化環氧助焊劑110且以蒸發其之助焊劑成份之至少一部分。取決於(例如)所選環氧助焊劑110之特定化學成份，一般技術者將能夠選擇特定溫度及時間量而足以固化環氧助焊劑110。
參考圖7，在導電結構102結合至焊墊114且環氧助焊劑110經固化變為環氧110A之後，一底部填充材料130可安置於半導體晶粒100與基板112之間之一容積中且鄰近導電結構102。可使用一習知技術(諸如)藉由接近半導體晶粒100之一或多個邊緣分配液體底部填充材料130且允許毛細力汲取底部填充材料130進入容積中來將底部填充材料130引入容積中。在一些實施例中，可藉由施加大於大氣壓力之一壓 力以迫使底部填充材料130進入容積中或藉由施加一經減小之壓力(例如真空)以汲取容積外之任何氣體(例如空氣)及汲取底部填充材料130進入容積中而輔助此毛細管作用及形成減小之孔隙。底部填充材料130可至少實質上填充半導體晶粒100與基板112之間之容積，且鄰近且橫向圍繞導電結構102。沿導電結構102之外側表面之環氧110A可在導電結構102與底部填充材料130之間形成一實體及絕緣(例如介電)障壁。環氧110A可橫向囊封導電結構102，透過介入底部填充材料130而實質上減少或甚至防止導電結構102之間之短路之可能。環氧110A亦可將機械支撐提供至導電結構102，且將機械強度提供至半導體晶粒100與基板112之間之連接。
底部填充材料130可包含一聚合物基質及一導熱材料(即一填充材料)，其可依顆粒之形式。如文中所使用，術語「導熱材料」意指且包含展現至少比一基質材料(導熱材料在其中分散)之一導熱性更大之導熱性之一材料。導熱材料可用於透過底部填充材料130(比較不具有此一導熱材料之底部填充材料)來改良熱轉移。展現相對較高導熱性之諸多材料(諸如金屬)亦係導電的。因此，在一些實施例中，底部填充材料130之導熱材料可為或包含金屬或另一材料之導電顆粒。
底部填充材料130之聚合物基質可為或包含(例如)一環氧材料、一聚矽氧材料、一改進聚矽氧材料或一丙烯酸脂材料。經由實例且無限制，導熱材料可為一金屬或金屬合金材料。經由另一實例，導熱材料可包含銀、金、銅、錫、銦、鉛、鋁之至少一者、其之合金、錫焊合金及其之組合。底部填充材料130之導熱材料可依任何形狀之顆粒之形式。例如，導熱材料之顆粒可依球體、薄片、纖維或不規則形狀之形式。顆粒之各者之表面可為平滑或粗糙。導熱材料之量在固化之前可至少為底部填充材料130之約50重量%。在一些實施例中，導熱材料之量可在底部填充材料130之約60重量%與約95重量%之間。在一 些實施例中，導熱材料之量可在底部填充材料130之約75重量%與約90重量%之間。在一特性實施例中，導熱材料之量可為底部填充材料130之約86重量%。此高負載量之導熱材料可大體上使得底部填充材料130(整體上)為導電以及導熱。然而，由環氧110A形成之導電結構102與底部填充材料130之間之電絕緣障壁可實現用於包含基節導電結構102之半導體裝置封裝之此一導電底部填充材料130之使用。因此，環氧110A可實現較高導熱底部填充材料130之使用，而不約束如其之導電性。
為促進底部填充材料130(包含導熱材料)之流入半導體晶粒100與基板112之間之容積，導熱材料之顆粒之平均直徑可約為一結合線厚度之三分之一或更少。結合線厚度可由跨半導體晶粒100與基板之間之容積之一最短垂直距離界定，不包含導電結構102。換言之，結合線厚度等於半導體晶粒100與基板112之間之底部填充材料130之一薄膜厚度。經由實例且無限制，半導體晶粒100與基板之間之結合線厚度可在約10微米與約100微米之間，例如在約20微米與約30微米之間。導熱材料之顆粒之大小可實質上小於結合線厚度以防止橋接及妥協結合線及以防止橫向囊封導電結構102之環氧110A之機械應力誘發穿孔。因此，在一些實施例中，導熱材料之最大顆粒大小(例如直徑)可約為30微米或更小，諸如小於約20微米、小於約3微米或甚至小於約1微米。其中一結合線在深度上為約20微米與約30微米之間，一最大顆粒大小可小於約3微米。在一些實施例中，導熱材料之最大顆粒大小可在約500納米與約25微米之間。
包含導熱材料之底部填充材料130可商業上可購得或可針對一特定應用而特別配製。在一些實施例中，可用作底部填充材料130之商業上可購得之材料之實例包含以下：商標EN-4920T_U-5677-011(具有一丙烯酸脂基質及銀粉填充劑，銀粉填充劑構成約材料之86重量%) 及EN-4620K(具有一環氧基質及銀粉填充劑，銀粉填充劑構成材料之約75重量%與約95重量%之間)之材料，兩者可自日本東京之Hitachi Chemical Co.,Ltd.購得；商標MT-315及MT-141(各具有一環氧基質及一銀填充劑，銀填充劑構成材料之約75重量%與約80重量%之間)之材料，兩者可自北卡羅萊納州喀里之LORD Corporation購得；商標EPO-TEK® H20S(具有一環氧基質及一銀片填充劑)及EPO-TEK® H20S-D(具有一環氧基質及一銀片填充劑，銀片填充劑構成材料之約60重量%與約75重量%之間)之材料，兩者可自馬薩諸塞州比勒利卡之Epoxy Technology,Inc.購得；商標84-1LMISR4(具有一環氧基質及一銀片填充劑)之材料，其可透過德國杜塞爾多夫之Henkel Corporation之ABLESTIK®品牌購得；商標260C(具有一環氧基質及一銅及錫合金填充劑，銅及錫合金填充劑構成材料之約86重量%)之材料，其可自加州聖地亞哥之Ormet Circuits,Inc.購得；商標DA-6534(具有一改進聚矽氧基質及一銀片填充劑，銀片填充劑構成材料之約60重量%)之材料，其可自密歇根州米德蘭之Dow Corning Corporation購得；商標X-23-7835-5(具有一聚矽氧基質及一銦填充劑)之材料，其可自日本東京之Shin-Etsu Chemical Co.,Ltd.購得及商標APS1E(具有一環氧基質及一銅及錫焊填充劑，銅及錫焊填充劑構成材料之約80重量%與約90重量%之間)之材料，其可自新澤西莫裡斯鎮之Honeywell International Inc.購得。
經由實例且無限制，儘管底部填充材料之聚合物基質可展現一相對較低導熱性(例如約1.3W/mK)之量級，然所選底部填充材料130(整體上)可展現高達(例如)約300.0W/mK之一導熱性。在一些實施例中，底部填充材料130可展現至少約1.0W/mK之一導熱性，諸如在約10.0W/mK與約30.0W/mK之間。在一些實施例中，底部填充材料130可展現在約10W/mK與約200.0W/mK之間之一導熱性。在一些實 施例中，底部填充材料130可為習知地用於填充一組件(例如一半導體裝置)與一散熱元件之間之一介面中之間隙之一熱介面材料(「TIM」)。
導電材料(例如TIM)並未習知地用作底部填充材料，特別是在具有如文中所描述之該等結構之基節導電結構102之半導體裝置封裝中，此係因為其之導電性將具有一較高可能性使得導電結構102透過底部填充材料而彼此非所要地電連通(即形成電連接)，如上文所描述。然而，如上文所提及，沿本發明之導電結構102之外側表面由環氧110A形成之電絕緣障壁實現導電底部填充材料130之使用，比較非導電及/或不包含導電填充材料之底部填充材料，其亦係高度導熱的。
在底部填充材料130安置於半導體晶粒100與基板112之間之容積中之後，底部填充材料130可被固化(例如凝固)。取決於所使用之底部填充材料130之類型，底部填充材料130可藉由(例如)施加熱量或暴露於輻射(諸如紫外線輻射)中而固化。在一些實施例中，底部填充材料130之固化可使得底部填充材料130之聚合物基質化學結合至環氧110A。若存在，則此等化學結合可抑制底部填充材料130與環氧110A之間之一介面處之孔隙及/或應力濃度之形成。
據此，本發明包含將一半導體晶粒附接至一基板之方法。根據此等方法，半導體晶粒可使用複數個基節導電結構來電耦合至一基板。複數個基節導電結構之各基節導電結構之至少一外側表面可由一電絕緣材料覆蓋。一導熱材料可安置於半導體晶粒與基板之間。導熱材料可包含複數個導熱顆粒及一聚合物基質。
另外，本發明包含形成一半導體裝置封裝之方法。根據此等方法，一半導體裝置之複數個基節導電結構可至少部分塗佈有一電絕緣材料。複數個基節導電結構可電耦合至一基板之對應複數個焊墊。一 底部填充材料可安置於半導體裝置與基板之間之一容積中。底部填充材料可具有分散於其中之複數個導熱顆粒。
參考圖8，展示沿圖7之線I-I通過半導體晶粒100與基板112之間之容積取得之圖7之結構之一橫截面俯視圖。如圖8中所示，在一些實施例中，複數個導電結構102之各導電結構102可具有沿其之一外側表面之環氧110A之一不同容積。底部填充材料130可安置於基板112上方(包含在複數個導電結構102之緊鄰導電結構102之間)。
參考圖9，展示類似於圖8之圖式之一橫截面俯視圖，除了複數個導電結構102之一個以上導電結構102可具有圍繞其之外側表面之環氧110A之一共同容積。因此，底部填充材料130可能不安置於複數個導電結構102之至少一些緊鄰導電結構102之間。
在額外實施例中，環氧110A之一單一連續容積可覆蓋導電結構102之一者以上，但可能無法完全填充半導體晶粒100(圖7)與基板112之間及緊鄰導電結構102之間之容積。在此一情況下，導電結構102之一者以上可由環氧110A之一單一連續容積覆蓋，但一些底部填充材料130仍可安置於緊鄰導電結構102之間之未填充容積中。
參考圖10，繪示一半導體裝置封裝200，其包含透過第一複數個導電結構202(其可具有一基節)而堆疊及電耦合之複數個半導體記憶體(例如DRAM)晶粒201A至201H。複數個半導體記憶體晶粒201A至201H可堆疊於一半導體邏輯晶粒212上方。半導體邏輯晶粒212可為一處理器，諸如一專用積體電路(ASIC)處理器或一中央處理單元(CPU)處理器。半導體記憶體晶粒201A至201H可透過第二複數個導電結構202(其可具有一基節)而電耦合至半導體邏輯晶粒212。儘管第三複數個導電結構224之節距可大於第一複數個導電結構202及第二複數個導電結構202之一節距，然半導體邏輯晶粒212可透過(例如)第三複數個導電結構224(其可具有一基節)而電耦合至一印刷電路板 (PCB)222。PCB 222可包含第四複數個導電結構226用以將PCB 222電耦合至一更高位準基板，諸如(例如)一母板。儘管第四複數個導電結構226之節距可大於第一複數個導電結構202及第二複數個導電結構202及/或第三複數個導電結構224之各自節距，然第四複數個導電結構226亦可具有一基節。在一些實施例中，第四複數個導電結構226可能不具有一基節。
一散熱元件228(例如一銅板)可定位於半導體記憶體晶粒201A至201H之堆疊上方以自半導體記憶體晶粒201A至201H及半導體邏輯晶粒212抽走熱量。一熱介面材料(TIM)232可安置於頂部半導體記憶體晶粒201H與散熱元件228之間用於其間之改良熱轉移。
經配製為上文所描述或其他導電配方之底部填充材料130之一者以提供一所要導熱性之一底部填充材料230可安置於半導體晶粒之間(例如在半導體記憶體晶粒201A至201H之任何者與半導體邏輯晶粒212之間)、一半導體晶粒與一基板之間(例如在半導體邏輯晶粒212與PCB 222之間)及在一基板與一更高位準基板之間(例如在PCB 222與一母板之間)之容積之任何者或全部中。如上文所解釋，底部填充材料230可包含亦可為一導電材料之一導熱材料，使得底部填充材料230整體上可為導電的。在底部填充材料230安置於其中之任何容積中，對應導電結構202、224及/或226之至少一外側表面可由一電絕緣材料210(例如一環氧)覆蓋，如上文參考環氧助焊劑110及環氧110A所描述。儘管第二複數個導電結構202、第三複數個導電結構224及/或第四複數個導電結構226之外側表面可替代地或額外由電絕緣材料210覆蓋，然為簡單起見，電絕緣材料210在圖10中被展示為僅覆蓋第一複數個導電結構202。
在一些實施例中，半導體記憶體晶粒201A至201H之各者之間之容積可填充有底部填充材料230(包含導電及導熱材料)。另外，更低 半導體記憶體晶粒201A與半導體邏輯晶粒212之間之容積可填充有底部填充材料230。將半導體記憶體晶粒201A至201H彼此電耦合且電耦合至半導體邏輯晶粒212之導電結構202之各者之外側表面可由電絕緣材料210覆蓋。因此，可減小半導體晶粒(包含半導體邏輯晶粒212及半導體記憶體晶粒201A至201H)之堆疊之一整體熱阻，且半導體裝置封裝200之組件(例如半導體記憶體晶粒201A至201H及半導體邏輯晶粒212)之一操作溫度可比不包含底部填充材料230(其包含一導電及導熱材料)之半導體裝置封裝更低。據此，比較習知半導體裝置封裝，底部填充材料230可藉由使得半導體裝置封裝200能夠在一更低晶粒溫度中操作而改良效能、再新率及半導體裝置封裝200之可靠性。
據此，本發明包含半導體裝置，該等裝置包含一基板及透過複數個基節導電結構而電耦合至基板之至少一半導體晶粒。一底部填充材料可安置於基板與至少一半導體晶粒及鄰近複數個基節導電結構之間之一容積中。底部填充材料可包括一導熱材料。半導體裝置亦可包含安置於複數個基節導電結構之間之一電絕緣材料及底部填充材料。
另外，本發明包含半導體裝置封裝，該等裝置封裝包含一半導體邏輯晶粒及堆疊於半導體邏輯晶粒上方之複數個半導體記憶體晶粒。複數個導電結構可將複數個半導體記憶體晶粒之鄰近晶粒與半導體邏輯晶粒彼此電耦合。一電絕緣材料可覆蓋複數個導電結構之各導電結構之外側表面。一導熱及導電材料可安置於半導體邏輯晶粒之鄰近晶粒與複數個半導體記憶體晶粒之間之一聚合物基質中。
上文所描述及附圖中所繪示之本發明之實施例不限制本發明之範疇，此係由於此等實施例僅係本發明之實施例之實例。本發明由所附申請專利範圍及其等之合法等效物定義。任何等效實施例位於本發明之範疇內。當然，除了文中所示及所描述之該等修改之外，一般技術者將自描述明白本發明之多種修改，諸如所描述之元件之替代的有 用組合。此等修改及實施例亦處於所附申請專利範圍及其等之合法等效物之範疇內。
200‧‧‧半導體裝置封裝
201A‧‧‧半導體記憶體晶粒
201B‧‧‧半導體記憶體晶粒
201C‧‧‧半導體記憶體晶粒
201D‧‧‧半導體記憶體晶粒
201E‧‧‧半導體記憶體晶粒
201F‧‧‧半導體記憶體晶粒
201G‧‧‧半導體記憶體晶粒
201H‧‧‧半導體記憶體晶粒
202‧‧‧第一複數個導電結構/第二複數個導電結構
210‧‧‧電絕緣材料
212‧‧‧半導體邏輯晶粒
222‧‧‧印刷電路板(PCB)
224‧‧‧第三複數個導電結構
226‧‧‧第四複數個導電結構
228‧‧‧散熱元件
230‧‧‧底部填充材料
232‧‧‧熱介面材料(TIM)

Claims (20)

  1. 一種半導體裝置，該裝置包括：一基板；至少一半導體晶粒，其透過複數個基節導電結構而電耦合至該基板；一底部填充材料，其經安置於該基板與該至少一半導體晶粒之間且鄰近該複數個基節導電結構之一容積中，該底部填充材料包括一導熱材料；及一電絕緣材料，其經安置於該複數個基節導電結構與該底部填充材料之間。
  2. 如請求項1之半導體裝置，其中該基板包括一邏輯晶粒及實質上類似於該至少一半導體晶粒之另一半導體晶粒中之一者。
  3. 如請求項1之半導體裝置，其中該電絕緣材料包括一環氧材料。
  4. 如請求項1之半導體裝置，其中該底部填充材料展現在介於約1.0W/mK與約300.0W/mK之間之一導熱性。
  5. 如請求項1之半導體裝置，其中該電絕緣材料經化學結合至該底部填充材料。
  6. 如請求項1之半導體裝置，其中該底部填充材料經進一步安置於該複數個基節導電結構之緊鄰基節導電結構之間之一容積中。
  7. 如請求項1之半導體裝置，其中該導熱材料包括小於該半導體晶粒與該基板之間之該容積之一厚度之約三分之一的顆粒。
  8. 如請求項1之半導體裝置，其中該複數個基節導電結構係定位於約1000微米或更小之一節距處。
  9. 如請求項1之半導體裝置，其中該電絕緣材料橫向囊封該複數個基節導電結構之各基節導電結構。
  10. 如請求項1之半導體裝置，其中該至少一半導體晶粒包括堆疊於該基板上方之複數個半導體晶粒。
  11. 如請求項1至10中任一項之半導體裝置，其中該底部填充材料之該導熱材料包括一導電材料。
  12. 如請求項11之半導體裝置封裝，其中該導電材料包括複數個導電顆粒。
  13. 一種將一半導體晶粒附接至一基板之方法，該方法包括：使用複數個基節導電結構來將一半導體晶粒電耦合至一基板；使用一電絕緣材料來覆蓋該複數個基節導電結構之各基節導電結構之至少一外側表面；及將包含複數個導熱顆粒之一導熱材料及一聚合物基質材料安置於該半導體晶粒與該基板之間。
  14. 如請求項13之方法，其中使用一電絕緣材料來覆蓋該複數個基節導電結構之各基節導電結構之至少一外側表面包括：使用一環氧助焊劑來覆蓋各基節導電結構之至少該外側表面；及固化該環氧助焊劑。
  15. 如請求項14之方法，其中固化該環氧助焊劑包括將熱量施加至該環氧助焊劑以固化其之一環氧成份，及以蒸發其之一助焊劑成份之至少一部分。
  16. 如請求項13之方法，其中使用複數個基節導電結構來將一半導體晶粒電耦合至一基板包括將該複數個基節導電結構電耦合至該基板之對應複數個焊墊。
  17. 如請求項16之方法，其中該複數個基節導電結構電耦合至該基板之對應複數個焊墊包括將該半導體晶粒結合至該基板之熱壓 縮及使該複數個基節導電結構持續一時段經受一溫度以至少部分熔化及回焊該等基節導電結構之材料中的至少一者。
  18. 如請求項13之方法，進一步包括選擇該導電材料以包含該複數個導熱顆粒之至少約50重量%。
  19. 如請求項13至18之任一項之方法，進一步包括選擇該導熱材料以包含複數個導熱及導電顆粒。
  20. 如請求項19之方法，進一步包括選擇該導電材料以包括具有約30微米或更小之一最大顆粒大小之該複數個導熱及導電顆粒。
TW103111304A 2013-03-27 2014-03-26 包含導電底部塡充材料之半導體裝置及封裝以及相關方法 TWI538120B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/851,788 US20140291834A1 (en) 2013-03-27 2013-03-27 Semiconductor devices and packages including conductive underfill material and related methods

Publications (2)

Publication Number Publication Date
TW201448134A true TW201448134A (zh) 2014-12-16
TWI538120B TWI538120B (zh) 2016-06-11

Family

ID=51620003

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103111304A TWI538120B (zh) 2013-03-27 2014-03-26 包含導電底部塡充材料之半導體裝置及封裝以及相關方法

Country Status (5)

Country Link
US (2) US20140291834A1 (zh)
KR (1) KR101825278B1 (zh)
CN (1) CN105051891B (zh)
TW (1) TWI538120B (zh)
WO (1) WO2014160675A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI680543B (zh) * 2015-03-02 2019-12-21 美商美光科技公司 具有底部填充控制腔之半導體裝置總成
TWI695469B (zh) * 2015-08-28 2020-06-01 美商英特爾Ip公司 具有高整合微電子晶粒堆疊之微電子封裝體
TWI712123B (zh) * 2015-10-22 2020-12-01 美商艾馬克科技公司 半導體裝置及其製造方法

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110309481A1 (en) * 2010-06-18 2011-12-22 Rui Huang Integrated circuit packaging system with flip chip mounting and method of manufacture thereof
US9209149B2 (en) * 2013-11-14 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace structures with high assembly yield
CN106164142B (zh) * 2014-03-11 2019-03-22 香港科技大学 导电导热糊剂组合物、以及利用该组合物降低逾渗阈值并提高逾渗传导性能的方法
US9691746B2 (en) * 2014-07-14 2017-06-27 Micron Technology, Inc. Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
US9548289B2 (en) * 2014-09-15 2017-01-17 Mediatek Inc. Semiconductor package assemblies with system-on-chip (SOC) packages
US20160079205A1 (en) * 2014-09-15 2016-03-17 Mediatek Inc. Semiconductor package assembly
US9601374B2 (en) 2015-03-26 2017-03-21 Micron Technology, Inc. Semiconductor die assembly
CN113257766A (zh) * 2015-08-21 2021-08-13 意法半导体有限公司 半导体装置及其制造方法
US10957667B2 (en) * 2016-10-01 2021-03-23 Intel Corporation Indium solder metallurgy to control electro-migration
US10424559B2 (en) * 2016-12-22 2019-09-24 Intel Corporation Thermal management of molded packages
US10593565B2 (en) * 2017-01-31 2020-03-17 Skyworks Solutions, Inc. Control of under-fill with a packaging substrate having an integrated trench for a dual-sided ball grid array package
US9978707B1 (en) * 2017-03-23 2018-05-22 Delphi Technologies, Inc. Electrical-device adhesive barrier
US20180286704A1 (en) * 2017-04-01 2018-10-04 Intel Corporation Processes and methods for applying underfill to singulated die
CN110660809B (zh) * 2018-06-28 2023-06-16 西部数据技术公司 包含分支存储器裸芯模块的垂直互连的半导体装置
CN110557937B (zh) * 2018-05-31 2021-08-06 铟泰公司 有效抑制在bga组合件的不润湿开口的助焊剂
US10861714B2 (en) * 2019-01-15 2020-12-08 Asm Technology Singapore Pte Ltd Heating of a substrate for epoxy deposition
US10764989B1 (en) * 2019-03-25 2020-09-01 Dialog Semiconductor (Uk) Limited Thermal enhancement of exposed die-down package
US10872835B1 (en) * 2019-07-03 2020-12-22 Micron Technology, Inc. Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same
CN112838079B (zh) * 2020-12-31 2022-06-10 湖北长江新型显示产业创新中心有限公司 显示模组及其制作方法
US11862591B2 (en) 2021-08-25 2024-01-02 Micron Technology, Inc. Conductive buffer layers for semiconductor die assemblies and associated systems and methods

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232563B1 (en) * 1995-11-25 2001-05-15 Lg Electronics Inc. Bump electrode and method for fabricating the same
US5956605A (en) * 1996-09-20 1999-09-21 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
KR100309957B1 (ko) * 1997-09-08 2002-08-21 신꼬오덴기 고교 가부시키가이샤 반도체장치
US6002168A (en) * 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
US20070241303A1 (en) * 1999-08-31 2007-10-18 General Electric Company Thermally conductive composition and method for preparing the same
JP2001093938A (ja) * 1999-09-20 2001-04-06 Nec Kansai Ltd 半導体装置及びその製造方法
JP3813797B2 (ja) * 2000-07-07 2006-08-23 株式会社ルネサステクノロジ 半導体装置の製造方法
TW498506B (en) * 2001-04-20 2002-08-11 Advanced Semiconductor Eng Flip-chip joint structure and the processing thereof
US6686664B2 (en) * 2001-04-30 2004-02-03 International Business Machines Corporation Structure to accommodate increase in volume expansion during solder reflow
US6610559B2 (en) * 2001-11-16 2003-08-26 Indium Corporation Of America Integrated void-free process for assembling a solder bumped chip
US6677179B2 (en) * 2001-11-16 2004-01-13 Indium Corporation Of America Method of applying no-flow underfill
TW571375B (en) * 2002-11-13 2004-01-11 Advanced Semiconductor Eng Semiconductor package structure with ground and method for manufacturing thereof
US7332821B2 (en) * 2004-08-20 2008-02-19 International Business Machines Corporation Compressible films surrounding solder connectors
US7252514B2 (en) * 2004-09-02 2007-08-07 International Business Machines Corporation High density space transformer and method of fabricating same
WO2006123478A1 (ja) * 2005-05-17 2006-11-23 Matsushita Electric Industrial Co., Ltd. フリップチップ実装方法とフリップチップ実装装置及びフリップチップ実装体
US8344523B2 (en) * 2006-05-08 2013-01-01 Diemat, Inc. Conductive composition
US20090108472A1 (en) * 2007-10-29 2009-04-30 International Business Machines Corporation Wafer-level underfill process using over-bump-applied resin
US8390117B2 (en) * 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
US8106520B2 (en) 2008-09-11 2012-01-31 Micron Technology, Inc. Signal delivery in stacked device
US8314499B2 (en) * 2008-11-14 2012-11-20 Fairchild Semiconductor Corporation Flexible and stackable semiconductor die packages having thin patterned conductive layers
US8507325B2 (en) * 2010-01-28 2013-08-13 International Business Machines Corporation Co-axial restraint for connectors within flip-chip packages
US9236277B2 (en) * 2012-08-10 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit with a thermally conductive underfill and methods of forming same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI680543B (zh) * 2015-03-02 2019-12-21 美商美光科技公司 具有底部填充控制腔之半導體裝置總成
TWI695469B (zh) * 2015-08-28 2020-06-01 美商英特爾Ip公司 具有高整合微電子晶粒堆疊之微電子封裝體
TWI712123B (zh) * 2015-10-22 2020-12-01 美商艾馬克科技公司 半導體裝置及其製造方法

Also Published As

Publication number Publication date
US20160351530A1 (en) 2016-12-01
KR20150129768A (ko) 2015-11-20
US20140291834A1 (en) 2014-10-02
TWI538120B (zh) 2016-06-11
CN105051891A (zh) 2015-11-11
WO2014160675A1 (en) 2014-10-02
KR101825278B1 (ko) 2018-02-02
CN105051891B (zh) 2019-07-05

Similar Documents

Publication Publication Date Title
TWI538120B (zh) 包含導電底部塡充材料之半導體裝置及封裝以及相關方法
TWI582920B (zh) 半導體封裝以及其之製造方法
US9502323B2 (en) Method of forming encapsulated semiconductor device package
US11862469B2 (en) Package structure and method of manufacturing the same
US11289346B2 (en) Method for fabricating electronic package
US8642393B1 (en) Package on package devices and methods of forming same
US8901732B2 (en) Semiconductor device package and method
TWI625838B (zh) 複合焊球、半導體封裝、半導體裝置及制造方法
TWI311352B (en) Fabricating process of leadframe-based bga packages and leadless leadframe utilized in the process
US20140210080A1 (en) PoP Device
US9852918B2 (en) Embedding additive particles in encapsulant of electronic device
US20160343616A1 (en) Semiconductor device including at least one element
JP2009260132A (ja) 半導体装置の製造方法
US20140226290A1 (en) Wiring substrate, component embedded substrate, and package structure
JP6242231B2 (ja) 半導体装置及びその製造方法
US20120146242A1 (en) Semiconductor device and method of fabricating the same
CN106469712A (zh) 电子封装结构及其制法
CN112310063A (zh) 半导体装置封装及其制造方法
CN112054007A (zh) 半导体封装载板及其制法与电子封装件
CN108807288B (zh) 电子封装件及其制法
CN109427725B (zh) 中介基板及其制法
TWM521807U (zh) 封裝結構及其中介板
CN111883505A (zh) 电子封装件及其承载基板与制法
TWI814524B (zh) 電子封裝件及其製法與電子結構及其製法
CN209880589U (zh) 半导体封装结构