CN1107340C - 形成半导体器件中的自对准接触的方法 - Google Patents

形成半导体器件中的自对准接触的方法 Download PDF

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CN1107340C
CN1107340C CN99109049A CN99109049A CN1107340C CN 1107340 C CN1107340 C CN 1107340C CN 99109049 A CN99109049 A CN 99109049A CN 99109049 A CN99109049 A CN 99109049A CN 1107340 C CN1107340 C CN 1107340C
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赵昶贤
李圭现
李宰求
郑相燮
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Abstract

本发明公开了一种半导体器件中的自对准接触焊盘及其形成方法，其中SAC开口与栅间隔层同时形成。形成其上具有栅电极和帽盖层的叠置栅图形之后，淀积用于栅间隔层的绝缘层。在该绝缘层上淀积层间绝缘层。该层间绝缘层具有相对于帽盖层和绝缘层的腐蚀选择性。在层间绝缘层中进行SAC开口，并同时形成栅间隔层。

Description

形成半导体器件中的自对准接触的方法
本发明涉及半导体器件中的接触焊盘及其制造方法，特别涉及自对准接触焊盘及其制造方法。
半导体制造技术的发展已经引入了千兆位DRAM时代。近来，随着半导体技术的发展，对于诸如千兆位DRAM等半导体器件向着较小设计规则发展的趋势已经进行到当将接触栓塞与接触栓塞下面的半导体层或互连层对准时已几乎不能保证对准余量的程度。因而，对于具有小于0.18微米或更小的临界尺寸的千兆位DRAM来说，使用容许通过与接触栓塞下面的半导体层或互连层自对准形成接触栓塞的制造工艺。
自对准接触(以下称为“SAC”)技术的优点是，可以增加照相工艺的不对准余量并且可以减小接触电阻。为此把重点放在SAC技术上。
图1表示根据常规SAC技术具有多个栅电极和接触焊盘的半导体衬底的剖面图。图1中示意地表示的结构是用下面的工艺步骤形成的。在半导体衬底1上形成器件隔离区3以确定有源区和无源区。器件隔离区3可以用本领域公知的任何合适方法形成，例如，浅槽隔离和硅的局部氧化。用常规方法即热氧化方法形成栅氧化物层(未示出)。栅电极导电层4a和栅帽盖绝缘层4b按顺序层叠在栅氧化物层上。栅帽盖层4b具有相对于后来的层间绝缘膜6的腐蚀选择性。使用本领域公知的光刻技术形成栅图形4。
用栅图形4作掩模，向半导体衬底1的有源区注入低浓度杂质离子。用淀积氮化硅层和对其深腐蚀的工艺在栅图形4的侧壁上形成栅间隔层5。栅间隔层5也具有相对于后来的层间绝缘膜6的腐蚀选择性。然后，使用栅图形4和间隔层5，向半导体衬底1的有源区中注入高浓度杂质离子。
在所得到的半导体衬底1上淀积层间绝缘膜6。在层间绝缘膜6上淀积光刻胶图形(未示出)。使用光刻胶图形，腐蚀暴露的层间绝缘膜6以形成多个接触孔7a和7b。光刻胶图形具有圆形或椭圆形结构的开口。
去掉光刻胶图形之后，用导电材料如多晶硅填充接触孔7a和7b。然后用如CMP(化学机械抛光)或深腐蚀平面化该多晶硅层，由此形成多个接触焊盘8a和8b，即位线接触焊盘8b和存储节点接触焊盘8a。
在腐蚀层间绝缘膜而用于形成SAC的过程中，由于SAC开口的高的高宽比而可能发生腐蚀停止现象(这意味着腐蚀副产物不容易从SAC开口扩散出来，从而SAC腐蚀率显著降低)。为解决腐蚀停止现象，腐蚀必需在可以抑制形成腐蚀副产物如聚合物的条件下进行，并且腐蚀时间必需增加。但是，在这种腐蚀条件的情况下，在腐蚀步骤过程中栅帽盖层和栅间隔层被腐蚀，由此引起SAC焊盘和栅电极之间的短路。
鉴于上述问题做出本发明，因此本发明的目的是提供在半导体器件中形成可靠的SAC的方法而不破坏栅间隔层，由此防止栅电极和后来形成的SAC焊盘之间的桥。
根据本发明，SAC开口与栅间隔层同时形成。具体地说，在形成具有栅电极和其上的帽盖层的叠置栅图形之后，淀积用于栅间隔层的绝缘层。在该绝缘层上淀积层间绝缘层。该层间绝缘层具有相对于帽盖层和绝缘层的腐蚀选择性。例如层间绝缘层是由氧化物层构成的，帽盖层和绝缘层是由氮化物层构成的。在层间绝缘层中形成SAC开口，同时形成栅间隔层。
通过参照附图使本发明更容易被理解，其目的对于本领域技术人员也更明显，其中：
图1是表示根据常规方法的SAC的剖面图；和
图2-6是表示根据本发明用于形成SAC焊盘的新方法的流程图。
下面参照附图介绍本发明的优选实施例。本发明涉及形成自对准接触的方法，该方法可以防止栅帽盖层和栅侧壁间隔层被破坏并防止腐蚀停止现象。栅侧壁间隔层是在腐蚀层间绝缘层用于形成SAC开口的过程中同时形成的。图2表示具有多个叠置栅结构和绝缘层的半导体衬底的单元阵列区的剖面图。用器件隔离区102在半导体衬底100中和半导体衬底100上确定有源区101和无源区。器件隔离层是用硅局部氧化(LOCOS)技术或沟槽隔离技术形成的。有源区101具有长椭圆形结构。在半导体衬底100上常规地形成叠置栅结构104。叠置栅结构104包括栅氧化物层(未示出)、栅电极104a、和栅帽盖层104b。常规地形成厚度约为50-100的栅氧化物层。淀积用于栅电极104a的栅导电层，并在其上淀积栅帽盖层。例如，栅导电层是由多晶硅和硅化钨层构成，并且其每个厚度约为1000。也可以使用其它的金属硅化物代替硅化钨。栅帽盖层104b是选自具有相对于后来的由氧化物层构成的层间绝缘层108的腐蚀选择性的材料。形成的栅帽盖层104b的厚度约为1000到2000范围内。在本例中，栅帽盖层104b是由约1500的氮化硅层和约500的氧化物层的双层构成的。
构图栅导电层和栅帽盖层以形成栅电极结构104。具体地说，在栅帽盖层上旋涂光刻胶层并通过曝光和显影构图成所希望的结构。使用该构图的光刻胶层，腐蚀栅帽盖层以形成栅帽盖图形104b。去掉构图的光刻胶层之后，使用栅帽盖图形104b，腐蚀栅导电层以形成栅电极104a，由此形成叠置栅结构104。
用叠置栅结构104作掩模，向半导体衬底100的有源区101中注入低浓度杂质离子。在包括叠置栅结构104的半导体衬底100上淀积用于栅间隔层的绝缘层106。绝缘层106是由具有相对于后来的层间绝缘层108的腐蚀选择性的材料构成。例如，形成的绝缘层106的厚度约为300到1000。最好选择氮化硅层并且厚度约为500。
虽然图中未示出，但中心区域和外围区域被光刻胶图形暴露。使用该光刻胶图形，深腐蚀绝缘层106，在中心区域和外围区域中形成栅间隔层。单元阵列区中被光刻胶图形帽盖的绝缘层106没有被深腐蚀，并用作后来SAC腐蚀的腐蚀停止层。然后，用光刻胶图形和间隔层作掩模，向半导体衬底100中注入高浓度杂质离子。
现在参照图3，淀积厚度约为3000到9000范围内的层间绝缘层108以填充叠置栅结构之间的间隔。最好层间绝缘层108由具有好的间隙填充特性的氧化物层构成，并且厚度约为5000。在层间绝缘层108上进行平面化工艺，并且其部分厚度被腐蚀以在栅帽盖层104b的上表面上留下约为1000(见图3的参考标号“t”)。
在平面化的层间绝缘层108上形成光刻胶图形110，暴露对准在SAC区域上的所希望的层间绝缘层108的部分111。如图3所示，被光刻胶图形110暴露的开口区域111对准在三个接触区域、两个存储节点区域和一个位线接触区域上。从顶视平面图可以看到，开口部分111具有包括有源区101和部分无源区的“T”形结构。或者，被光刻胶图形110暴露的开口区域可以只对准在一个接触区域上。
由于“T”结构同时暴露位线接触和存储节点接触区域，所以为SAC腐蚀提供宽的处理窗口。因此，可以避免在常规方法中遇到的腐蚀停止现象并腐蚀。
Y.Kohyama等人在1997 VLSI技术报告会，技术文章摘要的pp17-18的主题为“A Fully Printable，Self-aligned and Planarized StackedCapactor DRAM Cell Technology for 1Gbit DRAM and Beyond”的文章中已经提出了利用合并存储节点接触和位线接触的接触图形形成SAC焊盘的方法。但是在本发明中，栅SAC图形(表示抗蚀面积)与有源面积是一样的，并且向栅方向偏移半个间距。因此，光刻胶图形面积是如此的小以致于在SAC腐蚀过程中产生少量的聚合物。结果层间绝缘膜和栅间隔层的氮化物层和栅帽盖层具有彼此不好的腐蚀选择性。这是因为聚合物的形成与光刻胶图形面积成比例。
但是，根据本发明，被光刻胶图形占据的面积比被Y.Kohyama等人建议的大，从而提高了氮化物层和氧化物层之间的腐蚀选择性。
用光刻胶图形110作掩模，腐蚀层间绝缘层108和绝缘层106，由此同时形成栅间隔层106a和SAC开口111a。具体地说，相对于绝缘层106(用作腐蚀停止层)选择腐蚀层间绝缘层108。之后，深腐蚀绝缘层106，从而同时形成SAC开口111a和栅间隔层106a。根据本发明不会固有地发生在常规方法中遇到的栅间隔层106a的破坏。
形成SAC开口111a之后，在具有间隔层的叠置栅外边的暴露的半导体衬底上进行杂质离子注入，以便减小接触电阻。
去掉光刻胶图形110之后，在层间绝缘层108上淀积诸如多晶硅112的导电层，从而填充SAC开口111a。例如，多晶硅被淀积为约3000到7000的厚度。随后，进行平面化工艺以去掉层间绝缘层上的多晶硅层，同时留下SAC开口中的多晶硅层，如图5所示。平面化工艺可以是CMP或深腐蚀。CMP使用对于多晶硅是很普通的浆料。
层间绝缘层108和多晶硅层112是用平面化工艺同时去掉的，直到露出栅帽盖层104b的上表面为止，以便电隔离每个接触焊盘。平面化工艺可以是使用对于氧化物是常规的浆料的CMP。
如果开口区域111只暴露一个接触区域，存储节点或位线，就不需要前述用于电隔离的平面化工艺了。
本领域技术人员应该明白，本发明中公开的创新的概念可以适用于很宽的各种范围。而且，最佳实施方式也可以以各种方式修改。因而，应该理解，下面和上面建议的修改和改变只是表示性的。这些例子可以帮助表示创造性的概念的某些范围，但是这些例子并不表示所公开的新概念变化的整个范围。

Claims (7)

1.形成半导体器件中的自对准接触的方法，包括以下步骤：
在其中和其上具有有源区和无源区的半导体衬底上形成多个间隔的叠置栅图形，每个所述叠置栅图形包括栅电极和其上的栅帽盖层；
在所述叠置栅图形上和所述半导体衬底的顶部形成第二绝缘层；
形成层间绝缘层以填充所述叠置栅图形之间的间隔；
在所述层间绝缘层上形成掩模图形；
利用掩模蚀刻层间绝缘层，使在叠置栅图形之间的半导体衬底的表面暴露出来，以形成多个自对准开口，同时在叠置栅图形的侧壁上形成间隔层；
去掉所述掩模图形；和
用导电层填充所述自对准开口。
2.根据权利要求1的方法，其特征在于所述栅帽盖层和绝缘层具有相对于所述层间绝缘层的腐蚀选择性。
3.根据权利要求1或2的方法，其特征在于所述栅帽盖层和绝缘层是由氮化物化合物构成。
4.根据权利要求1或2的方法，其特征在于所述栅帽盖层的厚度在约1000到2000的范围内，而所述绝缘层的厚度在约300到1000的范围内。
5.根据权利要求1的方法，其特征在于所述层间绝缘层的厚度在约3000到9000的范围内，而所述导电层的厚度在约3000到7000的范围内。
6.根据权利要求1的方法，还包括平面化所述层间绝缘层。
7.根据权利要求1的方法，其特征在于至少一个所述自对准开口暴露至少两个不同接触区域。
CN99109049A 1998-06-17 1999-06-15 形成半导体器件中的自对准接触的方法 Expired - Lifetime CN1107340C (zh)

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CN1239815A (zh) 1999-12-29
FR2784229B1 (fr) 2004-03-12
TW439202B (en) 2001-06-07
KR100284535B1 (ko) 2001-04-02
GB2338596B (en) 2001-08-15
FR2784229A1 (fr) 2000-04-07
DE19925657B4 (de) 2006-07-06
GB2338596A (en) 1999-12-22
US6337275B1 (en) 2002-01-08
JP2000031085A (ja) 2000-01-28
GB9909492D0 (en) 1999-06-23
DE19925657A1 (de) 1999-12-23

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