GB2338596B - Process for use in forming a self aligned contact in a semiconductor device - Google Patents

Process for use in forming a self aligned contact in a semiconductor device

Info

Publication number
GB2338596B
GB2338596B GB9909492A GB9909492A GB2338596B GB 2338596 B GB2338596 B GB 2338596B GB 9909492 A GB9909492 A GB 9909492A GB 9909492 A GB9909492 A GB 9909492A GB 2338596 B GB2338596 B GB 2338596B
Authority
GB
United Kingdom
Prior art keywords
forming
semiconductor device
aligned contact
self aligned
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB9909492A
Other versions
GB9909492D0 (en
GB2338596A (en
Inventor
Chang-Hyun Cho
Kyu-Hyun Lee
Jae-Goo Lee
Sang-Sub Jeong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB9909492D0 publication Critical patent/GB9909492D0/en
Publication of GB2338596A publication Critical patent/GB2338596A/en
Application granted granted Critical
Publication of GB2338596B publication Critical patent/GB2338596B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
GB9909492A 1998-06-17 1999-04-23 Process for use in forming a self aligned contact in a semiconductor device Expired - Lifetime GB2338596B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980022733A KR100284535B1 (en) 1998-06-17 1998-06-17 Self-aligned contact formation method of semiconductor device

Publications (3)

Publication Number Publication Date
GB9909492D0 GB9909492D0 (en) 1999-06-23
GB2338596A GB2338596A (en) 1999-12-22
GB2338596B true GB2338596B (en) 2001-08-15

Family

ID=19539795

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9909492A Expired - Lifetime GB2338596B (en) 1998-06-17 1999-04-23 Process for use in forming a self aligned contact in a semiconductor device

Country Status (8)

Country Link
US (1) US6337275B1 (en)
JP (2) JP2000031085A (en)
KR (1) KR100284535B1 (en)
CN (1) CN1107340C (en)
DE (1) DE19925657B4 (en)
FR (1) FR2784229B1 (en)
GB (1) GB2338596B (en)
TW (1) TW439202B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064801B1 (en) 2014-01-23 2015-06-23 International Business Machines Corporation Bi-layer gate cap for self-aligned contact formation

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6376344B1 (en) * 1999-10-20 2002-04-23 Texas Instruments Incorporated Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device
KR100334572B1 (en) * 1999-08-26 2002-05-03 윤종용 Method of forming a self aligned contact in a semiconductor device
KR100527577B1 (en) * 1999-12-24 2005-11-09 주식회사 하이닉스반도체 Fabricating method for semiconductor device
US6261924B1 (en) * 2000-01-21 2001-07-17 Infineon Technologies Ag Maskless process for self-aligned contacts
KR100388477B1 (en) * 2000-12-11 2003-06-25 주식회사 하이닉스반도체 Method for forming contact hole of semiconductor device
KR100410980B1 (en) * 2001-04-24 2003-12-18 삼성전자주식회사 Method for Forming SAC Contact pad in Semiconductor Device
KR100414563B1 (en) * 2001-06-29 2004-01-07 주식회사 하이닉스반도체 Method of manufacturing semiconductor device
KR100442962B1 (en) * 2001-12-26 2004-08-04 주식회사 하이닉스반도체 Method for manufacturing of metal line contact plug of semiconductor device
KR100444302B1 (en) * 2001-12-29 2004-08-11 주식회사 하이닉스반도체 Manufacturing method of semiconductor device
KR100869357B1 (en) * 2002-05-17 2008-11-19 주식회사 하이닉스반도체 Method for fabricating semiconductor device with improved protection of void
US7105442B2 (en) * 2002-05-22 2006-09-12 Applied Materials, Inc. Ashable layers for reducing critical dimensions of integrated circuit features
US20040059726A1 (en) * 2002-09-09 2004-03-25 Jeff Hunter Context-sensitive wordless search
KR100587635B1 (en) * 2003-06-10 2006-06-07 주식회사 하이닉스반도체 Method for fabrication of semiconductor device
KR100670706B1 (en) * 2004-06-08 2007-01-17 주식회사 하이닉스반도체 Forming method of contact plug in semiconductor device
KR20060099870A (en) * 2005-03-15 2006-09-20 삼성전자주식회사 Thin film transistor comprising capping layer and method of manufacturing the same
US8124537B2 (en) * 2008-02-12 2012-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method for etching integrated circuit structure
KR102183038B1 (en) 2014-07-16 2020-11-26 삼성전자주식회사 Method for manufacturing a semiconductor device
US10622458B2 (en) 2017-05-19 2020-04-14 International Business Machines Corporation Self-aligned contact for vertical field effect transistor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670404A (en) * 1996-06-21 1997-09-23 Industrial Technology Research Institute Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer
EP0849785A2 (en) * 1996-12-20 1998-06-24 Texas Instruments Incorporated Method of making a self-aligned contact
GB2333179A (en) * 1998-01-08 1999-07-14 Samsung Electronics Co Ltd A method for forming a self aligned contact in a memory device

Family Cites Families (14)

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JPH02121336A (en) * 1988-10-31 1990-05-09 Hitachi Ltd Semiconductor device and its manufacture
KR950011643B1 (en) * 1992-04-17 1995-10-07 현대전자산업주식회사 Semiconductor device and fabricating method thereof
ATE168500T1 (en) * 1992-04-29 1998-08-15 Siemens Ag METHOD FOR PRODUCING A CONTACT HOLE TO A DOPPED AREA
US5416349A (en) * 1993-12-16 1995-05-16 National Semiconductor Corporation Increased-density flash EPROM that requires less area to form the metal bit line-to-drain contacts
US5482894A (en) * 1994-08-23 1996-01-09 Texas Instruments Incorporated Method of fabricating a self-aligned contact using organic dielectric materials
US5723381A (en) * 1995-09-27 1998-03-03 Siemens Aktiengesellschaft Formation of self-aligned overlapping bitline contacts with sacrificial polysilicon fill-in stud
JP2953404B2 (en) * 1995-12-08 1999-09-27 ソニー株式会社 Semiconductor device and manufacturing method thereof
JP3599466B2 (en) * 1996-03-18 2004-12-08 株式会社日立製作所 Method for manufacturing semiconductor integrated circuit device
JP3215320B2 (en) * 1996-03-22 2001-10-02 株式会社東芝 Method for manufacturing semiconductor device
JP3795634B2 (en) * 1996-06-19 2006-07-12 株式会社東芝 Manufacturing method of semiconductor device
US5817562A (en) * 1997-01-24 1998-10-06 Taiwan Semiconductor Manufacturing Company, Ltd Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC)
US6069077A (en) * 1997-07-07 2000-05-30 Vanguard International Semiconductor Corporation UV resist curing as an indirect means to increase SiN corner selectivity on self-aligned contact etching process
US6074915A (en) * 1998-08-17 2000-06-13 Taiwan Semiconductor Manufacturing Company Method of making embedded flash memory with salicide and sac structure
US6037223A (en) * 1998-10-23 2000-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Stack gate flash memory cell featuring symmetric self aligned contact structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670404A (en) * 1996-06-21 1997-09-23 Industrial Technology Research Institute Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer
EP0849785A2 (en) * 1996-12-20 1998-06-24 Texas Instruments Incorporated Method of making a self-aligned contact
GB2333179A (en) * 1998-01-08 1999-07-14 Samsung Electronics Co Ltd A method for forming a self aligned contact in a memory device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
1997 Symposium on VLSI Technology, Digest of Technical Papers, pp17-18 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064801B1 (en) 2014-01-23 2015-06-23 International Business Machines Corporation Bi-layer gate cap for self-aligned contact formation

Also Published As

Publication number Publication date
JP2000031085A (en) 2000-01-28
DE19925657A1 (en) 1999-12-23
DE19925657B4 (en) 2006-07-06
KR100284535B1 (en) 2001-04-02
KR20000002141A (en) 2000-01-15
CN1239815A (en) 1999-12-29
JP2007329501A (en) 2007-12-20
US6337275B1 (en) 2002-01-08
GB9909492D0 (en) 1999-06-23
FR2784229A1 (en) 2000-04-07
GB2338596A (en) 1999-12-22
CN1107340C (en) 2003-04-30
TW439202B (en) 2001-06-07
FR2784229B1 (en) 2004-03-12

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Expiry date: 20190422