CN110690209B - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN110690209B
CN110690209B CN201910467484.3A CN201910467484A CN110690209B CN 110690209 B CN110690209 B CN 110690209B CN 201910467484 A CN201910467484 A CN 201910467484A CN 110690209 B CN110690209 B CN 110690209B
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chip
substrate
semiconductor package
support structure
stack
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CN110690209A (zh
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白昇铉
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种半导体封装包括基板、在基板上的第一芯片、在基板上并与第一芯片并排布置的第二芯片、以及在第二芯片上的支撑结构。支撑结构的宽度等于或大于第二芯片的宽度。

Description

半导体封装
技术领域
本发明构思涉及一种半导体封装，更具体地，涉及一种包括以倒装芯片接合方式安装的半导体芯片的半导体封装。
背景技术
半导体封装被提供来实现用于电子产品的集成电路芯片。通常，半导体封装配置为使得半导体芯片安装在印刷电路板(PCB)上，接合引线或凸块用于将半导体芯片电连接到印刷电路板，并且半导体芯片被包封在模塑层中。随着电子工业的不断发展，越来越需要半导体封装具有增加的容量、功能、性能和紧凑性。因此，例如，已经发展了具有安装在PCB上的多个芯片的半导体封装。
发明内容
根据本发明构思，提供一种半导体封装，该半导体封装包括：基板；至少一个第一芯片，在基板的上表面上；第二芯片，在基板的上表面上并且当在平面图中观看时位于所述至少一个第一芯片旁边；以及在第二芯片上的支撑结构，其中支撑结构在平行于基板的上表面的方向上的宽度等于或大于第二芯片在所述方向上的宽度。
根据本发明构思，还提供一种半导体封装，该半导体封装包括：基板；至少一个第一芯片，设置在基板上并引线接合到基板；第二芯片，设置在基板上并在平面图中观看时在第一芯片旁边，并倒装芯片接合到基板；以及至少一个第三芯片，设置为横跨在所述至少一个第一芯片和第二芯片之上。
根据本发明构思，还提供一种半导体封装，该半导体封装包括：电子封装基板；第一功能块，包括设置在电子封装基板的上表面上且电连接到电子封装基板的第一芯片或第一芯片的堆叠；第二芯片，设置在电子封装基板的上表面上并电连接到电子封装基板；含硅材料块，设置在第二芯片上并且当在平面图中观看时设置在第一芯片或第一芯片的堆叠旁边；以及模塑层，在电子封装基板上并且其中包封第一功能块、第二芯片和含硅材料块。第一功能块在电子封装基板的上表面的第一区域上具有占用面积(footprint)。当在平面图中观看时，第二芯片设置在第一芯片或第一芯片的堆叠旁边，使得第二芯片具有在第一区域旁边的电子封装基板的第二区域上的占用面积。含硅材料块在与电子封装基板的上表面平行的方向上的宽度等于或大于第二芯片在所述方向上的宽度，使得含硅材料块具有在电子封装基板的第二区域上的占用面积。此外，含硅材料块具有比模塑层的硅含量比大的硅含量比。
根据本发明构思，还提供一种半导体封装，该半导体封装包括：电子封装基板；第一功能块，包括设置在电子封装基板的上表面上并电连接到电子封装基板的第一芯片或第一芯片的堆叠；第二芯片，设置在电子封装基板的上表面并电连接到电子封装基板；硅基第三芯片，设置在第二芯片上并且当在平面图中观看时设置在第一芯片或第一芯片的堆叠旁边；以及模塑层，在电子封装基板上并且第一功能块、第二芯片和硅基第三芯片被包封在其中。第一功能块在电子封装基板的上表面的第一区域上具有占用面积。当在平面图中观看时，第二芯片设置在第一芯片或第一芯片的堆叠旁边，使得第二芯片在基板的位于第一区域旁边的第二区域上具有占用面积。硅基第三芯片在平行于基板的上表面的方向上的宽度等于或大于第二芯片在所述方向上的宽度，使得硅基第三芯片在基板的第二区域上具有占用面积。此外，硅基第三芯片具有比模塑层的硅含量比大的硅含量比。
附图说明
图1是根据本发明构思的半导体封装的示例的简化截面图。
图2是根据本发明构思的半导体封装的另一示例的简化截面图。
图3A、图3B、图3C和图3D是图1的半导体封装在其制造过程中的简化截面图，并一起示出根据本发明构思的制造半导体封装的方法的示例。
图4是根据本发明构思的半导体封装的另一示例的简化截面图。
图5是根据本发明构思的半导体封装的另一示例的简化截面图。
图6是根据本发明构思的半导体封装的另一示例的简化截面图。
图7是根据本发明构思的半导体封装的另一示例的简化截面图。
图8是根据本发明构思的半导体封装的另一示例的简化截面图。
具体实施方式
现在将参照图1详细描述根据本发明构思的半导体封装1的示例。注意，在下面的描述中，为了简单起见，可以参考单个元件或特征诸如芯片、端子或电连接器，然而在实践中并且如附图所示，根据本发明构思的半导体封装可以具有多个这样的特征或元件。
半导体封装1可以包括基板100、包含至少一个第一芯片的第一功能块200、第二芯片300、支撑结构400和模塑层900。基板100是具有与绝缘材料的层成一体的导电迹线、焊盘、布线层等的电子封装基板，因此可以是印刷电路板(PCB)。因此，如附图所示，连接焊盘112提供在基板100的绝缘主体的顶表面102上。连接焊盘112可以包括例如信号连接焊盘和/或电源/接地连接焊盘。外部焊盘114可以提供在基板100的绝缘主体的底表面104上。外部端子120可以提供在外部焊盘114上。外部端子120可以包括焊料凸块或焊球。外部端子120可以联接到外部装置，该外部装置通过外部端子120电连接到基板100。外部端子120可以包括例如信号连接端子和/或电源/接地连接端子。
第一功能块200设置在基板100的上表面102上。第一功能块200可以设置在基板100的一侧上。第一功能块200可以包括单个(仅一个)存储器芯片。此外，每个第一芯片可以包括在其顶表面上的第一焊盘212。第一连接器220可以经由焊盘112、212提供在第一芯片和基板100之间且联接到第一芯片和基板100。第一连接器220可以是接合引线。接合引线可以包括金属，诸如金或铝。
如图1的示例所示，代替仅一个存储器芯片，第一功能块200可以包括在基板100的一侧堆叠在基板100的第一区域上的多个存储器芯片210。每个存储器芯片210可以是例如NAND芯片。第一粘合层230可以插置在存储器芯片210之间以及在基板100和最下面的存储器芯片210之间。每个第一粘合层230可以是例如管芯附着膜(DAF)或线上膜(FOW)。此外，每个存储器芯片210可以包括在其顶表面上的第一焊盘212。存储器芯片210在堆叠中彼此横向地偏移，使得每个存储器芯片210的第一焊盘212不被直接堆叠在其上的存储器芯片210覆盖。第一连接器220可以提供在第一芯片210和基板100之间且联接到第一芯片210和基板100。
第二芯片300可以设置在基板100的在第一区域旁边的第二区域上，第一功能块200的第一芯片或第一芯片210的堆叠设置在该第一区域上。第二芯片300可以设置在基板100的另一侧。因此，第一芯片和第二芯片可以并排提供在基板100上。第二芯片300可以是逻辑芯片。第二芯片300可以通过第二连接构件310电连接到基板100。第二连接构件310可以是焊料凸块或焊球。例如，第二芯片300可以倒装芯片接合到基板100。保护第二连接构件310的底填充层320可以提供在基板100和第二芯片300之间。
通常，至少在其占用面积方面，逻辑芯片将小于存储器芯片。因此，当第一功能块200实现为单个存储器芯片或存储器芯片210的堆叠并且第二芯片300被实现为逻辑芯片时，第一功能块200将在基板100的第一区域上具有比基板100的第二区域上的第二芯片300的占用面积大的占用面积。由于第二芯片300以倒装芯片接合方式安装，所以半导体封装1可以具有相对高的操作速度和短的周转时间(TAT)。
支撑结构400可以设置在第二芯片300上。支撑结构400可以包括硅(Si)。支撑结构400的硅与其它材料的比率(硅含量)可以大于模塑层900的该比率。支撑结构400可以是由包含硅的绝缘体组成的块。硅的比率(硅含量)是指每单位体积的Si的体积。在这种情况下，术语“块”可以指的是具有厚度或高度的材料的主体，该厚度或高度在附图中显著大于该主体在平行于基板的上表面的方向上的宽度。或者，支撑结构400可以包括虚设芯片。顾名思义，如本领域普通技术人员将理解的，虚设芯片与封装中的所有其它电路(即基板和芯片)电隔离，并可以是硅基芯片。
第二粘合层430可以插置在第二芯片300和支撑结构400之间。第二粘合层430可以是例如管芯附着膜(DAF)或线上膜(FOW)。第二粘合层430可以具有与第一粘合层230基本上相同的厚度。
支撑结构400可以具有等于或大于第二芯片300的宽度W2的宽度W1。在本说明书中，术语“宽度”是指在平行于基板100的上表面的方向上的尺寸。从基板100的顶表面102到支撑结构400的顶表面的距离D2可以与从基板100的顶表面102到第一芯片200的顶表面的距离D1基本上相同。在具有第一芯片的堆叠的所示示例中，距离D1可以对应于从基板100的顶表面102到芯片堆叠中的最上面的芯片的顶表面的距离。在本说明书中，短语“基本上”相同的尺寸或形状用于解释固有的或由于制造工艺中的微不足道的误差引起的可能的差异。
模塑层900可以提供在基板100上从而覆盖或“包封”第一芯片200、第二芯片300、支撑结构400和第一连接器220。模塑层900可以包括电介质聚合物，诸如环氧模塑料。
根据本发明构思的一方面，支撑结构400可以减小剪切应力的差异对第一功能块200的第一芯片和第二芯片300的影响。术语“剪切应力”是指抵抗由物体的工程特性或施加到物体的外力引起的物体变形的反作用力。如果没有提供支撑结构400，由于第一芯片和第二芯片之间的硅含量不平衡，施加在第二芯片300上的剪切应力将非常高，结果在第二芯片300和模塑层900之间会发生分层。也就是，半导体封装1的某个芯片与另一个(些)芯片之间的硅含量的不平衡越大，在该某个芯片上的剪切应力会变得越大。由于支撑结构400的硅含量大于模塑层900的硅含量，所以根据本发明构思的半导体封装1可以在各芯片之间具有硅含量的相对高的平衡。
接下来将参照图2描述根据本发明构思的半导体封装2。在图2的半导体封装2的描述中，与参照图1讨论的半导体封装1的部件类似的部件被分配相同的附图标记，并且为了简洁起见，可以省略这样的部件的详细描述。
图2的半导体封装2具有被提供为半导体芯片的支撑结构400a。
支撑结构400a可以被提供为存储器芯片。因此，支撑结构400a可以是NAND芯片或DRAM芯片。被提供为存储器芯片的支撑结构400a的硅含量大于模塑层900的硅含量。支撑结构400a可以包括第二焊盘410。第二连接器420可以提供在支撑结构400a和基板100之间且联接到支撑结构400a和基板100。第二连接器420可以是接合引线。接合引线可以包括金属，诸如金或铝。
在本发明构思的其中支撑结构400a被提供为存储器芯片的此示例中，可以防止第二芯片300的分层并提高半导体封装2的处理能力。
图3A至图3D示出制造图1的半导体封装1的方法。
参照图1和图3A，第二芯片300被放置在基板100上，第二芯片300的第二连接构件310设置为与基板100的连接焊盘(未示出)接触。之后，可以执行回流工艺。回流工艺可以在高于第二连接构件310的熔点的温度执行。
参照图1和图3B，底填充供应器350可以在第二芯片300的第二连接构件310周围提供底填充材料，并可以执行固化工艺。结果，第二芯片300被倒装芯片接合到基板100。
参照图1和图3C，支撑结构400安装在第二芯片300上。例如，第二粘合层430提供在第二芯片300上，支撑结构400提供在第二粘合层430上。或者，第二粘合层430可以提供在支撑结构的底表面上，然后具有第二粘合层430的支撑结构400被按压到第二芯片300的顶表面上。注意，与如果相同的芯片被引线接合到基板相比，当第二芯片300以倒装芯片接合方式安装到基板100时，第二芯片300更容易受到由支撑结构400施加的应力影响。因此，当支撑结构400被接合到第二芯片300时会需要小的压力和长的工艺时间以防止芯片300被损坏。
参照图1和图3D，第一功能块200可以在基板100上形成在第二芯片300旁边。在此工艺中，第一功能块的第一芯片可以引线接合到基板100。可以形成模塑层900以覆盖第一芯片200、第二芯片300和支撑结构400，并且外部端子120可以附接到基板100的底表面104，该步骤可以完成图1的半导体封装1的制造。
接下来，将参照图4详细描述根据本发明构思的半导体封装3的示例。在图4的半导体封装3的描述中，与参照图1讨论的半导体封装1的部件类似的部件被分配相同的附图标记，并且为了简洁起见，可以省略其详细描述。
图4的半导体封装3包括第二功能块500，第二功能块500包括至少一个第三芯片。在此示例中，第一功能块是单个存储器芯片200a。第二功能块500也可以是单个存储器芯片。第二功能块500可以包括例如NAND芯片或DRAM芯片。第二功能块500提供在第一芯片200a和支撑结构400上。
在图4所示的半导体封装3的示例中，代替单个第三芯片，第二功能块500包括提供在第一芯片200a和支撑结构400上的多个堆叠的存储器芯片510。第三粘合层530可以插置在堆叠的存储器芯片510之间。第三粘合层530可以是例如管芯附着膜(DAF)或线上膜(FOW)。第三粘合层530也可以插置在最下面的存储器芯片510、第一芯片200a和支撑结构400之间。
每个存储器芯片510可以包括在其顶表面上的第三焊盘512。第三连接器520可以提供在第三芯片510和基板100之间且联接到第三芯片510和基板100。第三连接器520可以是接合引线。接合引线可以包括金属，诸如金或铝。
现在将参照图5详细描述根据本发明构思的半导体封装4的示例。在图5的半导体封装4的描述中，与参照图4讨论的半导体封装3的部件类似的部件被分配相同的附图标记，并且为了简洁起见，可以省略其详细描述。
图5的半导体封装4包括第一功能块200b、第二功能块500、第三功能块600和第一间隔物700。
第三功能块600可以与第一功能块200b和第二芯片300并排地布置在基板100的上表面102上。例如，第二芯片300可以设置在第一功能块200b和第三功能块600之间。
第一功能块200b可以是包括多个堆叠的芯片的芯片堆叠。例如，第一功能块200b可以包括第一下存储器芯片210a和堆叠在第一下存储器芯片210a上的第一上存储器芯片210b。第一下存储器芯片210a和第一上存储器芯片210b中的每个可以包括单个DRAM芯片，但是本发明构思不限于此。第一粘合层230a和230b可以分别插置在第一下存储器芯片210a和基板100之间以及在第一下存储器芯片210a和第一上存储器芯片210b之间。第一粘合层230a和230b中的每个可以是例如管芯附着膜(DAF)或线上膜(FOW)。第一下存储器芯片210a和第一上存储器芯片210b可以在其顶表面上包括它们的第一焊盘212a和212b。第一连接器220a和220b可以提供在第一芯片200b和基板100之间且联接到第一芯片200b和基板100。第一连接器220a和220b可以是接合引线。
第三功能块600可以具有单个(仅一个)存储器芯片。或者，第三功能块600可以是包括多个堆叠的芯片的芯片堆叠。例如，第三功能块600可以包括第四下存储器芯片610a和堆叠在第四下存储器芯片610a上的第四上存储器芯片610b。第四下存储器芯片610a和第四上存储器芯片610b中的每个(即芯片堆叠的第四芯片中的每个)可以是DRAM芯片，但是本发明构思不限于此。第四粘合层630a和630b可以分别插置在第四下存储器芯片610a和基板100之间以及在第四下存储器芯片610a和第四上存储器芯片610b之间。第四粘合层630a和630b中的每个可以是例如管芯附着膜(DAF)或线上膜(FOW)。第四下存储器芯片610a和第四上存储器芯片610b可以分别在其顶表面上包括第四焊盘612a和612b。第四连接器620a和620b可以提供在第四芯片600和基板100之间且联接到第四芯片600和基板100。第四连接器620a和620b可以是接合引线。
第一间隔物700可以提供在第一功能块200b、第二芯片300、第三功能块600一起与第二功能块500之间。更具体地，第一间隔物700可以提供在第一功能块200b、支撑结构400、第三功能块600一起与第二功能块500之间。第一间隔物700可以提供在第一功能块200b、第三功能块600和支撑结构400上。第一间隔物700是绝缘体的板，即可以具有实质上小于它的其它两个尺寸(在平行于基板的上表面的方向上的尺寸)的厚度或高度，并可以包括硅(Si)，但是本发明构思不限于此。第一间隔物700可以具有与功能块500的芯片的尺寸(占用面积)对应的尺寸(占用面积)，但是本发明构思不限于此。
根据本发明构思的此示例的一方面，第一间隔物可以用作支撑结构。因此，第一间隔物700可以增强半导体封装4的结构稳定性。具体地，第一间隔物700可以防止半导体封装4在功能块500的芯片的区域中在其上部处翘曲和/或防止由于翘曲而形成空隙。结果，半导体封装4可以相对无缺陷。
管芯附着膜(DAF)或线上膜(FOW)可以提供在第一间隔物700与第一功能块200b、支撑结构400和第三功能块600之间，但是为了附图的简洁，其可以被省略。
现在将参照图6描述根据本发明构思的半导体封装5。在图6中，分别与参照图4和图5讨论的半导体封装3和4的部件类似的部件被分配相同的附图标记，并且为了简洁起见，可以省略其详细描述。
图6的半导体封装5可以包括第二间隔物800。第三功能块600a可以具有单个(仅一个)存储器芯片。
图6的半导体封装5可以包括第一芯片堆叠500a和堆叠在第一芯片堆叠500a上的第二芯片堆叠500b。如上所述，第一芯片堆叠500a和第二芯片堆叠500b中的每个可以包括多个堆叠的存储器芯片。因此，将省略其详细描述。
第二间隔物800可以提供在第一芯片堆叠500a和第二芯片堆叠500b之间。第二间隔物800可以由包括硅(Si)的板形式的绝缘体组成，但是本发明构思不限于此。第二间隔物800可以具有与功能块500的芯片之一的尺寸(占用面积)对应的尺寸(占用面积)，但是本发明构思不限于此。
根据本发明构思的此示例的一个方面，第二间隔物800可以赋予半导体封装5结构稳定性。可以提供第二间隔物800以防止半导体封装5在包含功能块500的芯片的区域的上部翘曲和/或可以防止由于翘曲而形成空隙。
管芯附着膜(DAF)或线上膜(FOW)可以提供在第一间隔物700与第一功能块200a、第二芯片300和第三功能块600a之间，但是为了附图的简洁，它可以被省略。
现在将参照图7详细描述根据本发明构思的半导体封装6。在图7的半导体封装6中，与参照图4讨论的半导体封装3的部件类似的部件被分配相同的附图标记，并且为了简洁起见，可以省略其描述。
图7的半导体封装6没有支撑结构。
由于第二芯片300以倒装芯片接合方式安装，所以半导体封装6可以以短的周转时间(TAT)高速操作，同时仍具有高集成度。
现在将参照图8描述根据本发明构思的半导体封装7。在图8的半导体封装7中，与参照图7讨论的半导体封装6的部件类似的部件被分配相同的附图标记，并且为了简洁起见，可以省略其描述。
图8的半导体封装7包括第一间隔物700。
第一间隔物700可以提供在第一芯片220和第二芯片300一起与功能块500之间。第一间隔物700可以是绝缘体的板并可以包括硅(Si)。第一间隔物700可以具有与功能块500的芯片的尺寸(占用面积)对应的尺寸(占用面积)，但是本发明构思不限于此。
根据本发明构思的此示例的一方面，第一间隔物700可以赋予半导体封装7结构稳定性。特别地，可以提供第一间隔物700以防止半导体封装7在包含功能块500的芯片的区域的上部翘曲和/或可以防止由于翘曲而形成空隙。结果，半导体封装7可以相对无缺陷。
根据本发明构思的一些示例，提供具有高集成度并结构稳定的半导体封装。
管芯附着膜(DAF)或线上膜(FOW)可以提供在第一间隔物700与第一功能块200a和第二芯片300之间，但是为了附图的简洁，它可以被省略。
此外，根据本发明构思的一些示例，提供了半导体封装，其中模塑层和安装在基板上的芯片被防止彼此分层。
然而，本发明构思的效果、益处和优点不限于上述那些。从前面的描述和附图，以上没有提到的其它效果、益处和优点将对于本领域技术人员来说是明显的。
最后，这里描述的本发明构思的示例被给出以促进理解本发明构思，而不应被解释为限制本发明构思的范围。而是，这里描述的示例的各种组合、修改和变化被视为落入由权利要求书限定的本发明构思的实际精神和范围内。
本申请要求于2018年7月5日在韩国知识产权局提交的韩国专利申请第10-2018-0078275号的优先权，其全部内容通过引用结合于此。

Claims (22)

1.一种半导体封装，包括：
基板；
至少一个第一芯片，在所述基板的上表面上；
第二芯片，在所述基板的所述上表面上并且当在平面图中观看时位于所述至少一个第一芯片旁边；
支撑结构，在所述第二芯片上；以及
模塑层，在所述基板上并且包封所述至少一个第一芯片、所述第二芯片和所述支撑结构，
其中所述支撑结构在平行于所述基板的所述上表面的方向上的宽度等于或大于所述第二芯片在所述方向上的宽度，
其中所述支撑结构的硅含量比大于所述模塑层的硅含量比，以及
其中从所述基板的所述上表面到所述支撑结构的顶表面的距离与从所述基板的所述上表面到所述至少一个第一芯片的顶表面的距离基本上相同。
2.根据权利要求1所述的半导体封装，其中所述支撑结构包括绝缘材料块、虚设芯片或存储器芯片。
3.根据权利要求1所述的半导体封装，其中所述至少一个第一芯片是存储器芯片，并且
所述第二芯片是逻辑芯片。
4.根据权利要求3所述的半导体封装，其中所述至少一个第一芯片包括多个堆叠的第一芯片以构成第一芯片堆叠。
5.根据权利要求1所述的半导体封装，其中所述至少一个第一芯片被引线接合到所述基板，并且
所述第二芯片被倒装芯片接合到所述基板。
6.根据权利要求1所述的半导体封装，还包括在所述至少一个第一芯片和所述第二芯片上的至少一个第三芯片。
7.根据权利要求1所述的半导体封装，还包括在所述至少一个第一芯片和所述支撑结构上的至少一个第三芯片。
8.根据权利要求6或者7所述的半导体封装，还包括插置在所述至少一个第一芯片和所述至少一个第三芯片之间的第一间隔物。
9.根据权利要求8所述的半导体封装，还包括在所述基板的所述上表面上并且当在平面图中观看时设置在所述至少一个第一芯片和所述第二芯片旁边的至少一个第四芯片，所述至少一个第四芯片插置在所述基板和所述第一间隔物之间。
10.根据权利要求9所述的半导体封装，其中所述至少一个第一芯片包括多个堆叠的第一芯片以构成第一芯片堆叠和/或所述至少一个第四芯片包括多个堆叠的第四芯片以构成第四芯片堆叠。
11.根据权利要求9所述的半导体封装，其中所述至少一个第三芯片包括多个堆叠的第三芯片以构成第一芯片堆叠和设置在所述第一芯片堆叠上的第二芯片堆叠，并且
所述半导体封装还包括第二间隔物，该第二间隔物设置在所述第一芯片堆叠和所述第二芯片堆叠之间。
12.根据权利要求9所述的半导体封装，其中所述至少一个第四芯片是存储器芯片。
13.一种半导体封装，包括：
基板；
至少一个第一芯片，设置在所述基板上并引线接合到所述基板；
第二芯片，设置在所述基板上并且当在平面图中观看时在所述第一芯片旁边，并倒装芯片接合到所述基板；以及
至少一个第三芯片，设置在所述至少一个第一芯片和所述第二芯片之上；
支撑结构，插置在所述第二芯片和所述至少一个第三芯片之间；以及
模塑层，在所述基板上并且包封所述至少一个第一芯片、所述第二芯片、所述至少一个第三芯片和所述支撑结构，
其中所述支撑结构的硅含量比大于所述模塑层的硅含量比，
其中从所述基板的上表面到所述支撑结构的顶表面的距离与从所述基板的所述上表面到所述至少一个第一芯片的顶表面的距离基本上相同。
14.根据权利要求13所述的半导体封装，其中所述至少一个第一芯片是存储器芯片，并且所述第二芯片是逻辑芯片。
15.根据权利要求13所述的半导体封装，其中所述至少一个第三芯片包括多个存储器芯片。
16.根据权利要求13所述的半导体封装，其中所述支撑结构包括绝缘材料块、虚设芯片或存储器芯片。
17.根据权利要求13所述的半导体封装，其中所述支撑结构在平行于所述基板的上表面的方向上的宽度等于或大于所述第二芯片在所述方向上的宽度。
18.根据权利要求13所述的半导体封装，还包括：第一间隔物，插置在所述至少一个第一芯片与所述至少一个第三芯片之间和所述第二芯片与所述至少一个第三芯片之间。
19.根据权利要求18所述的半导体封装，还包括插置在所述第二芯片和所述第一间隔物之间的支撑结构。
20.根据权利要求18所述的半导体封装，还包括至少一个第四芯片，所述至少一个第四芯片设置在所述基板上并在平面图中观看时在所述至少一个第一芯片和所述第二芯片旁边，所述至少一个第四芯片插置在所述基板和所述第一间隔物之间。
21.根据权利要求20所述的半导体封装，其中所述至少一个第一芯片包括多个堆叠的第一芯片以构成第一芯片堆叠和/或所述至少一个第四芯片包括多个堆叠的第四芯片以构成第四芯片堆叠。
22.根据权利要求20所述的半导体封装，其中所述至少一个第三芯片包括多个堆叠的第三芯片以构成第一芯片堆叠和设置在所述第一芯片堆叠上的第二芯片堆叠，并且
所述半导体封装还包括插置在所述第一芯片堆叠和所述第二芯片堆叠之间的第二间隔物。
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