CN1106043C - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1106043C CN1106043C CN98100991A CN98100991A CN1106043C CN 1106043 C CN1106043 C CN 1106043C CN 98100991 A CN98100991 A CN 98100991A CN 98100991 A CN98100991 A CN 98100991A CN 1106043 C CN1106043 C CN 1106043C
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- layer
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- semiconductor device
- insulating barrier
- siof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31629—Deposition of halogen doped silicon oxide, e.g. fluorine doped silicon oxide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims (14)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9080672A JP3019021B2 (ja) | 1997-03-31 | 1997-03-31 | 半導体装置及びその製造方法 |
JP80672/1997 | 1997-03-31 | ||
JP80672/97 | 1997-03-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1198014A CN1198014A (zh) | 1998-11-04 |
CN1106043C true CN1106043C (zh) | 2003-04-16 |
Family
ID=13724859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN98100991A Expired - Fee Related CN1106043C (zh) | 1997-03-31 | 1998-03-31 | 半导体器件及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US6130154A (zh) |
JP (1) | JP3019021B2 (zh) |
KR (1) | KR100265256B1 (zh) |
CN (1) | CN1106043C (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101399219B (zh) * | 2007-09-28 | 2011-11-02 | 上海华虹Nec电子有限公司 | 金属层间通孔的制备和填充方法 |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW469619B (en) * | 1998-05-26 | 2001-12-21 | Winbond Electronics Corp | Structure and manufacturing method for metal line |
US6444564B1 (en) * | 1998-11-23 | 2002-09-03 | Advanced Micro Devices, Inc. | Method and product for improved use of low k dielectric material among integrated circuit interconnect structures |
US6252303B1 (en) * | 1998-12-02 | 2001-06-26 | Advanced Micro Devices, Inc. | Intergration of low-K SiOF as inter-layer dielectric |
US6281584B1 (en) * | 1998-12-02 | 2001-08-28 | Advanced Micro Devices, Inc. | Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces |
JP3266195B2 (ja) | 1999-03-23 | 2002-03-18 | 日本電気株式会社 | 半導体装置の製造方法 |
JP2001035808A (ja) * | 1999-07-22 | 2001-02-09 | Semiconductor Energy Lab Co Ltd | 配線およびその作製方法、この配線を備えた半導体装置、ドライエッチング方法 |
US6265305B1 (en) * | 1999-10-01 | 2001-07-24 | United Microelectronics Corp. | Method of preventing corrosion of a titanium layer in a semiconductor wafer |
KR100602314B1 (ko) * | 1999-12-29 | 2006-07-14 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 형성 방법 |
JP4646346B2 (ja) * | 2000-01-28 | 2011-03-09 | パナソニック株式会社 | 電子デバイスの製造方法 |
WO2002075801A2 (en) * | 2000-11-07 | 2002-09-26 | Tokyo Electron Limited | Method of fabricating oxides with low defect densities |
JP2002217292A (ja) * | 2001-01-23 | 2002-08-02 | Hitachi Ltd | 半導体集積回路装置および半導体集積回路装置の製造方法 |
JP2003045874A (ja) | 2001-07-27 | 2003-02-14 | Semiconductor Energy Lab Co Ltd | 金属配線およびその作製方法、並びに金属配線基板およびその作製方法 |
JP2003060031A (ja) | 2001-08-14 | 2003-02-28 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法。 |
JP2003152165A (ja) * | 2001-11-15 | 2003-05-23 | Fujitsu Ltd | 半導体装置およびその製造方法 |
KR20030053967A (ko) * | 2001-12-24 | 2003-07-02 | 동부전자 주식회사 | 반도체 소자의 금속배선 형성방법 |
JP2004140198A (ja) * | 2002-10-18 | 2004-05-13 | Oki Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2005101597A (ja) * | 2003-09-04 | 2005-04-14 | Seiko Epson Corp | 半導体装置およびその製造方法 |
US7100216B2 (en) * | 2003-10-15 | 2006-09-05 | Impact Innovative Products, Llc | Garment with energy dissipating conformable padding |
US7045455B2 (en) * | 2003-10-23 | 2006-05-16 | Chartered Semiconductor Manufacturing Ltd. | Via electromigration improvement by changing the via bottom geometric profile |
US7329953B2 (en) * | 2003-10-29 | 2008-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same |
KR100536808B1 (ko) * | 2004-06-09 | 2005-12-14 | 동부아남반도체 주식회사 | 반도체 소자 및 그 제조 방법 |
US20060038293A1 (en) * | 2004-08-23 | 2006-02-23 | Rueger Neal R | Inter-metal dielectric fill |
DE602005001759D1 (de) * | 2004-12-16 | 2007-09-06 | St Microelectronics Crolles 2 | SRAM-Speicherzelle |
US7446047B2 (en) * | 2005-02-18 | 2008-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal structure with sidewall passivation and method |
DE102007037858B4 (de) | 2007-08-10 | 2012-04-19 | Infineon Technologies Ag | Halbleiterbauelement mit verbessertem dynamischen Verhalten |
JP5170101B2 (ja) | 2007-11-02 | 2013-03-27 | 富士通セミコンダクター株式会社 | 半導体装置とその製造方法 |
US8710661B2 (en) * | 2008-11-26 | 2014-04-29 | International Business Machines Corporation | Methods for selective reverse mask planarization and interconnect structures formed thereby |
CN102569168A (zh) * | 2010-12-23 | 2012-07-11 | 无锡华润上华半导体有限公司 | 金属互连线的制作方法 |
JP5364765B2 (ja) * | 2011-09-07 | 2013-12-11 | 東京エレクトロン株式会社 | 半導体装置及び半導体装置の製造方法 |
CN105789218A (zh) * | 2016-03-10 | 2016-07-20 | 京东方科技集团股份有限公司 | 一种基板、其制作方法及显示装置 |
US10347509B1 (en) | 2018-02-09 | 2019-07-09 | Didrew Technology (Bvi) Limited | Molded cavity fanout package without using a carrier and method of manufacturing the same |
CN112005369A (zh) * | 2018-02-15 | 2020-11-27 | 迪德鲁科技(Bvi)有限公司 | 制造无热界面材料气密平顶his/emi屏蔽封装的系统和方法 |
US10424524B2 (en) | 2018-02-15 | 2019-09-24 | Chengdu Eswin Sip Technology Co., Ltd. | Multiple wafers fabrication technique on large carrier with warpage control stiffener |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06163538A (ja) * | 1992-11-26 | 1994-06-10 | Sumitomo Metal Ind Ltd | プラズマエッチング方法 |
US5489553A (en) * | 1995-05-25 | 1996-02-06 | Industrial Technology Research Institute | HF vapor surface treatment for the 03 teos gap filling deposition |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
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US5179435A (en) * | 1990-03-05 | 1993-01-12 | Nec Corporation | Resin sealed semiconductor integrated circuit device |
JPH04174541A (ja) * | 1990-03-28 | 1992-06-22 | Nec Corp | 半導体集積回路及びその製造方法 |
JPH04147651A (ja) * | 1990-04-02 | 1992-05-21 | Toshiba Corp | 半導体装置およびその製造方法 |
US5189502A (en) * | 1990-05-08 | 1993-02-23 | Nec Corporation | Semiconductor device having ventilative insulating films |
US5345108A (en) * | 1991-02-26 | 1994-09-06 | Nec Corporation | Semiconductor device having multi-layer electrode wiring |
US5532516A (en) * | 1991-08-26 | 1996-07-02 | Lsi Logic Corportion | Techniques for via formation and filling |
JPH05226480A (ja) * | 1991-12-04 | 1993-09-03 | Nec Corp | 半導体装置の製造方法 |
JP2755035B2 (ja) * | 1992-03-28 | 1998-05-20 | ヤマハ株式会社 | 多層配線形成法 |
JP3688726B2 (ja) * | 1992-07-17 | 2005-08-31 | 株式会社東芝 | 半導体装置の製造方法 |
JP2778612B2 (ja) * | 1992-09-02 | 1998-07-23 | 日本電気株式会社 | 半導体装置 |
KR0128491B1 (ko) * | 1993-04-14 | 1998-04-07 | 모리시다 요이치 | 반도체 장치 및 그 제조방법 |
JPH06302593A (ja) * | 1993-04-16 | 1994-10-28 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
US5378659A (en) * | 1993-07-06 | 1995-01-03 | Motorola Inc. | Method and structure for forming an integrated circuit pattern on a semiconductor substrate |
US5753975A (en) * | 1994-09-01 | 1998-05-19 | Kabushiki Kaisha Toshiba | Semiconductor device with improved adhesion between titanium-based metal wiring layer and insulation film |
US5565707A (en) * | 1994-10-31 | 1996-10-15 | International Business Machines Corporation | Interconnect structure using a Al2 Cu for an integrated circuit chip |
JP2737764B2 (ja) * | 1995-03-03 | 1998-04-08 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JPH09139428A (ja) * | 1995-11-16 | 1997-05-27 | Mitsubishi Electric Corp | 半導体装置 |
JP2739853B2 (ja) * | 1995-11-28 | 1998-04-15 | 日本電気株式会社 | 半導体装置の製造方法及びエッチング方法 |
KR100230392B1 (ko) * | 1996-12-05 | 1999-11-15 | 윤종용 | 반도체 소자의 콘택 플러그 형성방법 |
US6310300B1 (en) * | 1996-11-08 | 2001-10-30 | International Business Machines Corporation | Fluorine-free barrier layer between conductor and insulator for degradation prevention |
KR100243272B1 (ko) * | 1996-12-20 | 2000-03-02 | 윤종용 | 반도체 소자의 콘택 플러그 형성방법 |
-
1997
- 1997-03-31 JP JP9080672A patent/JP3019021B2/ja not_active Expired - Lifetime
-
1998
- 1998-03-30 US US09/049,931 patent/US6130154A/en not_active Expired - Fee Related
- 1998-03-31 KR KR1019980011285A patent/KR100265256B1/ko not_active IP Right Cessation
- 1998-03-31 CN CN98100991A patent/CN1106043C/zh not_active Expired - Fee Related
-
2000
- 2000-10-06 US US09/680,437 patent/US6627996B1/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06163538A (ja) * | 1992-11-26 | 1994-06-10 | Sumitomo Metal Ind Ltd | プラズマエッチング方法 |
US5489553A (en) * | 1995-05-25 | 1996-02-06 | Industrial Technology Research Institute | HF vapor surface treatment for the 03 teos gap filling deposition |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101399219B (zh) * | 2007-09-28 | 2011-11-02 | 上海华虹Nec电子有限公司 | 金属层间通孔的制备和填充方法 |
Also Published As
Publication number | Publication date |
---|---|
KR19980080955A (ko) | 1998-11-25 |
KR100265256B1 (ko) | 2000-09-15 |
US6627996B1 (en) | 2003-09-30 |
JPH10275859A (ja) | 1998-10-13 |
CN1198014A (zh) | 1998-11-04 |
JP3019021B2 (ja) | 2000-03-13 |
US6130154A (en) | 2000-10-10 |
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