CN110249431B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN110249431B
CN110249431B CN201880009680.XA CN201880009680A CN110249431B CN 110249431 B CN110249431 B CN 110249431B CN 201880009680 A CN201880009680 A CN 201880009680A CN 110249431 B CN110249431 B CN 110249431B
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semiconductor substrate
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CN110249431A (zh
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宫田征典
高桥茂树
住友正清
志贺智英
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Denso Corp
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Abstract

半导体装置，具有元件部(1)和将元件部(1)包围的外周部(2)，在外周部(2)形成有深度比基极层(12)深的深层(23)，设深层(23)中的最靠元件部(1)侧的位置为边界位置(K)，设边界位置(K)与能够注入第1载流子的发射极区域(16)中的最靠外周部(2)侧的位置之间的距离为第1距离(L1)，设边界位置(K)与集电极层(21)中的半导体基板(10)的面方向上的端部的位置之间的距离为第2距离(L2)，将第1距离(L1)及第2距离(L2)进行调整，以使得基于因深层(23)而降低了的外周部(2)的耐压而该外周部(2)的载流子密度降低。

Description

半导体装置
关连申请的相互参照
本申请基于2017年2月3日申请的日本专利申请第2017－18672号，这里通过参照而引入其记载内容。
技术领域
本发明涉及具有形成了绝缘栅双极型晶体管(以下简称IGBT)元件的元件部和将元件部包围的外周部的半导体装置。
背景技术
以往，提出了具有形成了IGBT元件的元件部和将该元件部包围的外周部的半导体装置(例如参照专利文献1)。具体而言，该半导体装置具备具有一面以及与一面相反侧的另一面并且构成漂移层的半导体基板。并且，在元件部，在漂移层上形成有P型的基极层，在基极层的表层部形成有N+型的发射极区域。此外，以隔着栅极绝缘膜而与基极层相接的方式，形成有栅极电极。并且，在漂移层中的与基极层相反的一侧，形成有集电极层。另外，该集电极层从元件部形成到外周部。此外，在半导体基板的一面侧，以与基极层及发射极区域电连接的方式形成有上部电极，在半导体基板的另一面侧，以与集电极层电连接的方式形成有下部电极。
在外周部，在半导体基板的一面侧，多个P+型的深层以构成多重环构造的方式形成。另外，多个深层形成得比基极层深，以抑制元件部的电场集中。
在这样的半导体装置中，当向栅极电极施加规定的栅极电压，则在基极层中的与栅极电极相邻的部分形成反型层(即沟道区域)。由此，电子被从发射极区域经由反型层向漂移层供给，并且空穴被从集电极层向漂移层供给，由于电导率调制，漂移层的电阻值降低而电流流动。
现有技术文献
专利文献
专利文献1:日本特开2001―217420号公报
发明概要
但是，在上述半导体装置中，由于在外周部形成有比基极层深的深层，因此，在外周部，漂移层的实质厚度比元件部薄而耐压降低。此外，上述半导体装置中，在外周部也形成有集电极层，空穴也从形成在外周部的集电极层向漂移层供给。因此，上述半导体装置中，在从流动电流的状态将该电流切断时，在外周部容易发生击穿。并且，上述半导体装置，由于与元件部相比在外周部不易使电流流出，所以如果在外周部发生击穿则损坏的可能性变高。
发明内容
本发明的目的在于，关于在外周部具有形成得比基极层深的深层的半导体装置，提供能够抑制在外周部发生击穿的半导体装置。
根据本发明的1个观点，具有元件部和将元件部包围的外周部的半导体装置，具备：半导体基板，具有一面以及一面的相反侧的另一面，构成第1导电型的漂移层；第2导电型的基极层，形成在元件部中的漂移层上并且半导体基板的一面侧；栅极绝缘膜，分别形成在将基极层贯通并到达漂移层、沿着半导体基板的面方向延伸设置的多个沟槽的壁面；栅极电极，分别形成在栅极绝缘膜上；第1导电型的发射极区域，形成在基极层的表层部，与沟槽相接；第2导电型的深层，形成在外周部中的漂移层的表层部并且半导体基板的一面侧，深度比基极层深；第2导电型的集电极层，至少形成在元件部中的半导体基板的另一面侧；第1电极，与发射极区域及基极层电连接；以及第2电极，与集电极层电连接。并且，半导体装置，通过向栅极电极施加规定的栅极电压，从第1电极经由发射极区域向漂移层注入第1载流子并且从第2电极经由集电极层向漂移层注入第2载流子，从而在第1电极与第2电极之间流过电流，在半导体基板的一面，设深层中的最靠元件部侧的位置为边界位置，设边界位置与能够从第1电极注入第1载流子的发射极区域中的最靠外周部侧的位置之间的距离为第1距离，设边界位置与集电极层中的半导体基板的面方向上的端部的位置之间的距离为第2距离，第1距离以及第2距离被进行了调整，以使得基于因深层而降低了的外周部的耐压而该外周部的载流子密度降低。
由此，当从流动电流的状态将该电流切断时，能够抑制在外周部发生击穿，能够抑制半导体装置损坏。
附图说明
图1是第1实施方式的半导体装置的剖面图。
图2A是表示相邻的沟槽的间隔为4μm的情况下的空穴密度的仿真结果。
图2B是表示相邻的沟槽的间隔为2μm的情况下的空穴密度的仿真结果。
图2C是表示相邻的沟槽的间隔为1.2μm的情况下的空穴密度的仿真结果。
图3是表示相邻的沟槽的间隔与半导体基板的一面侧的载流子扩展的关系的图。
图4是表示第1距离及第2距离与半导体装置的损坏的有无的关系的图。
图5是第1实施方式的其他半导体装置的剖面图。
图6是第2实施方式的半导体装置的剖面图。
图7是第3实施方式的半导体装置的剖面图。
具体实施方式
以下，基于附图说明本发明的实施方式。另外，以下的各实施方式中，对于相同或等同的部分附加同一附图标记进行说明。
(第1实施方式)
参照图1说明第1实施方式的半导体装置。如图1所示，本实施方式的半导体装置具备具有一面10a以及一面10a的相反侧的另一面10b的半导体基板10，形成有形成了IGBT元件的元件部1、和将该元件部1包围的外周部2。首先，对元件部1的基本结构进行说明。
元件部1具有N－型的漂移层11，在漂移层11上(即半导体基板10的一面10a侧)形成有P型的基极层12。此外，形成有将基极层12贯通并到达漂移层11的多个沟槽13，基极层12被多个沟槽13分断。本实施方式中，多个沟槽13沿着半导体基板10的一面10a的面方向中的一个方向(即图1中纸面进深方向)呈条状地等间隔形成。
另外，本实施方式中，漂移层11的杂质浓度为1.0×1014cm－3。此外，多个沟槽13形成为，彼此对置的侧面的间隔是固定的。即，相邻的沟槽13的间隔从沟槽13的开口部侧沿着底部侧是固定的。
多个沟槽13分别被将沟槽13的壁面覆盖而形成的栅极绝缘膜14和形成在该栅极绝缘膜14之上的栅极电极15埋入。由此，构成沟槽栅极构造。另外，本实施方式中，各栅极电极15适当地经由栅极布线3而与栅极焊盘4电连接，能够被从外部的栅极电路施加规定的栅极电压。
在基极层12的表层部，形成有N+型的发射极区域16以及P+型的体(body)区域17。具体而言，发射极区域16以比漂移层11高的杂质浓度构成，终止于基极层12内，并且与沟槽13的侧面相接而形成。另一方面，体区域17以比基极层12高的杂质浓度构成，与发射极区域16同样地，终止于基极层12内。
更详细而言，在沟槽13间的区域，发射极区域16沿着沟槽13的长度方向以与沟槽13的侧面相接的方式呈棒状延伸设置，在比沟槽13的前端靠内侧终止。此外，体区域17被2个发射极区域16夹着，沿着沟槽13的长度方向(即发射极区域16)呈棒状延伸设置。另外，本实施方式的体区域17以半导体基板10的一面10a为基准而形成得比发射极区域16深。
在半导体基板10的一面10a上，形成有由BPSG(Boro-phospho silicate glass的简称)等构成的层间绝缘膜18。在层间绝缘膜18，形成有使发射极区域16的一部分以及体区域17露出的第1接触孔18a。并且，在层间绝缘膜18上，形成有经由第1接触孔18a而与发射极区域16及体区域17电连接的上部电极19。
在漂移层11中的基极层12侧的相反侧(即半导体基板10的另一面10b侧)，形成有N型的场截止(field stop)层(以下简称FS层)20。该FS层20虽不必须，但为了通过防止耗尽层的扩展来实现耐压和稳态损耗的性能提高、并且控制从半导体基板10的另一面10b侧注入的空穴的注入量而具备。
并且，夹着FS层20而在漂移层11的相反侧，形成有P型的集电极层21，在集电极层21上(即半导体基板10的另一面10b上)，形成有与集电极层21电连接的下部电极22。
以上是本实施方式的元件部1的基本结构。接着，对外周部2的基本结构进行说明。
外周部2具有与元件部1相同的漂移层11。并且，在漂移层11的表层部，为了抑制元件部1的电场集中，形成有比基极层12深的P+型的深层23。具体而言，在外周部2，由于在元件部1中容易在沟槽13的底部发生电场集中，所以为了抑制沟槽13的底部的电场集中而形成有P+型的深层23。本实施方式中，深层23形成有多个，分别呈将元件部1围住的环状构造。即，多个深层23构成多重环构造。
另外，深层23形成得比基极层12深，但由于越深则漂移层11的实质厚度越薄而耐压降低，所以优选形成为比基极层12深1～3μm左右。此外，本实施方式中，多个深层23中的最靠元件部1侧的深层23以与形成于元件部1的基极层12接触的方式形成。即，该深层23也可以说与基极层12相连而形成。
此外，在外周部2，与元件部1同样地，在半导体基板10的一面10a上形成有层间绝缘膜18，在层间绝缘膜18，形成有使深层23露出的第2接触孔18b。并且，在层间绝缘膜18上，形成有经由第2接触孔18b而与深层23电连接的外周电极24。
外周部2中的半导体基板10的另一面10b侧形成有FS层20。并且，在外周部2，在FS层20上(即半导体基板10的另一面10b上)形成有下部电极22。
以上是本实施方式的半导体装置的基本结构。另外，本实施方式中，N+型、N－型相当于第1导电型，P型、P+型相当于第2导电型。此外，上部电极19相当于第1电极，下部电极22相当于第2电极。
接着，说明上述半导体装置的基本动作。上述半导体装置，如果在上部电极19接地并且下部电极22被施加了正电压的状态下被从外部的栅极电路向栅极电极15施加规定的栅极电压，则在基极层12中的与沟槽13相接的部分形成反型层(即沟道区域)。并且，半导体装置中，从发射极区域16经由反型层将电子向漂移层11供给，并且从集电极层21将空穴向漂移层11供给。由此，半导体装置通过电导率调制而漂移层11的电阻值降低，在上部电极19与下部电极22之间流过电流。
并且，上述半导体装置，通过向上部电极19施加正电压并且将下部电极22接地、例如向栅极电极15施加0V的电压，从而在上部电极19与下部电极22之间流动的电流被切断。另外，以下，将在上部电极19与下部电极22之间流过电流的状态设为半导体装置为导通状态、将该电流被切断了的状态设为半导体装置为截止状态来进行说明。此外，本实施方式中，电子相当于第1载流子，空穴相当于第2载流子。
这里，本实施方式中，为了抑制在从导通状态成为截止状态时在外周部2发生击穿，调整了发射极区域16以及集电极层21的位置关系。即，如上所述，如果在外周部2形成比基极层12深的深层23，则外周部2中的漂移层11的实质厚度变薄，外周部2的耐压容易变低。因此，本实施方式中，为了使得即使耐压降低也难以在外周部2发生击穿，调整了发射极区域16与集电极层21的位置关系。换言之，由于通过形成深层23而外周部2的耐压降低，所以调整了发射极区域16与集电极层21的位置关系，以使得基于降低了的耐压而外周部2的载流子密度变低。
以下，对于发射极区域16以及集电极层21的位置关系具体地进行说明。另外，以下，如图1所示，将深层23中的最靠元件部1侧的位置设为元件部1与外周部2的边界位置K。此外，在多个发射极区域16中的能够被从上部电极19注入电子(即载流子)的发射极区域16中，将最靠外周部2侧的位置(以下称为最外发射极位置)与边界位置K之间的距离设为第1距离L1。并且，将集电极层21中的沿着半导体基板10的面方向的端部的位置与边界位置K之间的距离设为第2距离L2。另外，关于第2距离L2，将集电极层21中的沿着半导体基板10的面方向的端部的位置位于元件部1内的情况设为正的距离，将该端部的位置位于外周部2的情况设为负的距离。进而，将半导体基板10的板厚设为第3距离L3。并且，将相邻的沟槽13的间隔中的最窄部分的距离设为沟槽间隔L4。
首先，如上所述，本实施方式的半导体装置，如果向栅极电极15施加规定的栅极电压，则从发射极区域16将电子向漂移层11供给，并且从集电极层21将空穴向漂移层11供给从而成为导通状态。此时，如图2A～图2C所示，确认到：空穴密度的分布根据沟槽间隔L4而不同。并且，确认到：沟槽间隔L4越窄则空穴密度高的部分的扩展越大。即，图2A～图2C中，图2C的空穴密度高的部分最扩展。另外，图2A～图2C是将第1距离L1设为150μm、将第2距离L2设为150μm、将第3距离L3设为78μm的仿真结果。
因此，本发明者们，关于相对于板厚的一面侧的载流子扩展，基于沟槽间隔L4进行了研究，得到了图3所示的结果。即，如图3所示，相对于板厚的一面侧的载流子扩展A(以下简称载流子扩展A)通过利用了沟槽间隔L4的下式表示。
(式1)A＝－0.30×L4+1.53
另外，本实施方式中的载流子扩展A如以下那样定义。即，载流子扩展A表示：在漂移层11中的最靠半导体基板10的一面10a侧的部分、以最外发射极位置的正下方部分为基准、空穴密度成为漂移层11的杂质浓度的10倍的部分从该基准离开了多少。本实施方式中，由于漂移层11的杂质浓度设为1.0×1014cm－3，所以表示成为1.0×1015cm－3的部分离开了多少。换言之，表示空穴密度成为1.0×1015cm－3以上的部分与空穴密度不到1.0×1015cm－3的部分之间的边界从基准离开了多少。例如，如果载流子扩展A是1则意味着：在漂移层11中的最靠半导体基板10的一面10a侧的部分，空穴密度不到1.0×1015cm－3的部分是在外周部2侧从最外发射极位置的正下方部分离开了78μm(即板厚的量)以上的部分。此外，例如，如果载流子扩展A是0.5则意味着：在漂移层11中的最靠半导体基板10的一面10a侧的部分，空穴密度不到1.0×1015cm－3的部分是在外周部2侧从最外发射极位置的正下方部分离开了39μm(即板厚的一半量)以上的部分。
这里，以空穴密度成为漂移层11的杂质浓度的10倍的部分作为边界是因为，如果空穴密度超过漂移层11的杂质浓度的10倍，则电场强度由于空穴的正电荷而变得过强，耐压降低变得显著。即，本实施方式中，如果成为1.0×1015cm－3以上的部分达到外周部2，则半导体装置容易从该部分损坏。此外，载流子扩展A由于是相对于板厚的比，所以板厚×A为相对于基准而言空穴密度成为1.0×1015cm－3的位置。
另外，所谓漂移层11中的最靠半导体基板10的一面10a侧的部分，如果是元件部1则成为与基极层12的边界位置。并且，如果是外周部2，则成为与深层23的边界位置。但是，外周部2的情况下，在没有形成深层23的部分，将与形成有深层23的部分的边界位置相同深度的位置设为漂移层11中的最靠半导体基板10的一面10a侧的部分。
此外，沟槽间隔L4优选的是，至少离开100nm左右而形成，以使沿着相邻的沟槽13形成的反型层彼此不相连。进而，沟槽间隔L4如果过宽则在漂移层11中积累空穴的效果显著降低，所以优选为8μm以下。
接着，本发明者们，关于从导通状态成为截止状态时是否在外周部2发生击穿而半导体装置损坏，研究了第1距离L1与第2距离L2的关系，得到图4所示的结果。另外，图4是沟槽间隔L4为1.8μm且第3距离L3为78μm时的仿真结果。即，图4是载流子扩展A为1的情况下的仿真结果。换言之，是基准与空穴密度成为1.0×1015cm－3的部分之间的长度为78×1的情况下的仿真结果。
如图4所示，确认到：在沟槽间隔L4为1.8μm的情况下，第1距离L1及第2距离L2如果满足下式则半导体装置不损坏。
(式2)L1≥78×1－L2
并且，图4中，由于第3距离L3是78，载流子扩展A是1，所以如果将式2变形则成为下式。
(式3)L1≥L3×A－L2
因此，如果将上述式3基于式1变形则可得下式。
(式4)L1≥L3×(－0.30×L4+1.53)－L2
因而，本实施方式中，以满足上式的方式设定了第1距离L1、第2距离L2、第3距离L3以及沟槽间隔L4。
如以上说明的那样，本实施方式中，以满足L1≥L3×(－0.30×L4+1.53)－L2的方式，设定了第1距离L1、第2距离L2、第3距离L3以及沟槽间隔L4。因此，在从导通状态成为截止状态时，能够抑制在外周部2发生击穿，能够抑制半导体装置损坏。
此外，在设为L1＝L3×(－0.30×L4+1.53)－L2的情况下，能够得到半导体装置不损坏的极限的载流子密度。因此，在设为L1＝L3×(－0.30×L4+1.53)－L2的情况下，能够实现导通电压的降低并且抑制半导体装置损坏。
另外，图1中，示出了集电极层21中的沿着半导体基板10的面方向的端部的位置位于元件部1内的情况。但是，只要满足上述式4，集电极层21中的沿着半导体基板10的面方向的端部的位置也可以如图5所示那样位于外周部2，该情况下第2距离L2成为负的值。
(第2实施方式)
对第2实施方式进行说明。相对于第1实施方式，本实施方式中将多个栅极电极15的一部分与栅极焊盘4连接，将多个栅极电极15的剩余部分与上部电极19连接，其他与第1实施方式是同样的所以这里省略说明。
本实施方式中，如图6所示，多个栅极电极15中的一部分栅极电极15a与栅极焊盘4连接。并且，多个栅极电极15中的剩余部分的栅极电极15b不与栅极焊盘4连接，经由形成于层间绝缘膜18的第3接触孔18c而与上部电极19连接。即，与上部电极19连接的栅极电极15b作为不发挥在半导体装置为导通状态时在基极层12形成反型层的功能的所谓伪栅极电极。
本实施方式中，设一部分栅极电极15为第1栅极电极15a，设剩余部分的栅极电极15为第2栅极电极15b，第1栅极电极15a以及第2栅极电极15b沿着半导体基板10的面方向交替地配置。并且，第1栅极电极15a以及第2栅极电极15b配置为，在第1栅极电极15a与第2栅极电极15b的排列方向上的最靠外周部2侧存在第2栅极电极15b。
另外，本实施方式中，与上述第1实施方式同样地，发射极区域16沿着各沟槽13形成。即，本实施方式中，在配置第2栅极电极15b的沟槽13的侧面也形成发射极区域16。
此外，如上所述，第1距离L1是最外发射极位置与边界位置K之间的距离。因此，本实施方式的半导体装置中，与配置第1栅极电极15a的沟槽13相接的发射极区域16的最靠外周部2侧的位置与边界位置K之间的距离成为第1距离L1。
如以上说明的那样，具有第2栅极电极(即伪栅极电极)15b的半导体装置，通过满足上述式4，也能够得到与上述第1实施方式同样的效果。
(第3实施方式)
对第3实施方式进行说明。相对于第1实施方式，本实施方式改变了沟槽13的形状，其他与第1实施方式是相同的所以这里省略说明。
本实施方式中，如图7所示，各沟槽13在对置的侧面的间隔中底部侧的宽度比开口部侧的宽度长。换言之，关于相邻的沟槽13的间隔，底部侧的间隔比开口部侧的间隔短。即，本实施方式中，沟槽13呈所谓的壶形状。另外，如上所述，沟槽间隔L4是相邻的沟槽13的间隔中的最窄的部分。因此，本实施方式中，沟槽间隔L4成为相邻的沟槽13之间的部分中的底部侧的部分。
根据这样的半导体装置，在相邻的沟槽13的间隔中，由于能够使沟槽13的开口部侧的长度较长，所以能够实现发射极区域16以及体区域17的制造工序的简化并且得到与上述第1实施方式同样的效果。
(其他实施方式)
本发明依据实施方式进行了记载，但应理解的是本发明不限于该实施方式及构造。本发明还包含各种各样的变形例及等同范围内的变形。此外，各种各样的组合及形态、进而在它们中仅包含一要素、其以上或其以下的其他组合及形成也落入本发明的范畴及思想范围。
例如，上述各实施方式中，说明了设第1导电型为N型并且设第2导电型为P型的例子，但还能够设第1导电型为P型且设第2导电型为N型。
此外，上述第2实施方式中，也可以不以与配置第2栅极电极15b的沟槽13的侧面相接的方式形成发射极区域16。即，发射极区域16也可以仅形成在配置第1栅极电极15a的沟槽13的侧面。此外，第2栅极电极15b也可以不与上部电极19连接、而是与不同于栅极焊盘4的栅极焊盘连接而被维持在规定电位(例如地电位)，也可以不与电极连接而被设为浮置状态。进而，第1栅极电极15a以及第2栅极电极15b也可以是，在第1栅极电极15a与第2栅极电极15b的排列方向上的最外周部2侧存在第1栅极电极15a。
并且，也可以将上述第2实施方式与上述第3实施方式组合，在上述第3实施方式的半导体装置中，做成具有第1栅极电极15a以及第2栅极电极15b的结构。

Claims (2)

1.一种半导体装置，具有元件部(1)和将上述元件部包围的外周部(2)，其特征在于，
具备：
半导体基板(10)，具有一面(10a)以及上述一面的相反侧的另一面(10b)，构成第1导电型的漂移层(11)；
第2导电型的基极层(12)，形成在上述元件部中的上述漂移层上并且上述半导体基板的一面侧；
栅极绝缘膜(14)，分别形成在多个沟槽(13)的壁面，该多个沟槽将上述基极层贯通并到达上述漂移层且沿着上述半导体基板的面方向延伸设置；
栅极电极(15)，分别形成在上述栅极绝缘膜上；
第1导电型的发射极区域(16)，形成在上述基极层的表层部，与上述沟槽相接；
第2导电型的深层(23)，形成在上述外周部中的上述漂移层的表层部并且上述半导体基板的一面侧，深度比上述基极层深；
第2导电型的集电极层(21)，至少形成在上述元件部中的上述半导体基板的另一面侧；
第1电极(19)，与上述发射极区域及上述基极层电连接；以及
第2电极(22)，与上述集电极层电连接；
通过向上述栅极电极施加规定的栅极电压，从上述第1电极经由上述发射极区域向上述漂移层注入第1载流子并且从上述第2电极经由上述集电极层向上述漂移层注入第2载流子，从而在上述第1电极与上述第2电极之间流过电流；
在上述半导体基板的一面，将上述深层中的最靠上述元件部侧的位置设为边界位置(K)，将上述边界位置与能够从上述第1电极注入上述第1载流子的上述发射极区域中的最靠上述外周部侧的位置之间的距离设为第1距离(L1)，将上述边界位置与上述集电极层中的上述半导体基板的面方向上的端部的位置之间的距离设为第2距离(L2)；
上述第1距离及上述第2距离被进行了调整，以使得基于因上述深层而降低了的上述外周部的耐压而该外周部的载流子密度降低，并且上述第1距离及上述第2距离被基于相邻的上述沟槽的间隔(L4)进行了调整；
设上述半导体基板的厚度为第3距离，关于上述第2距离，将上述集电极层的端部位于上述元件部内的情况设为正的距离、并且将上述集电极层的端部位于上述外周部内的情况设为负的距离，设上述第1距离为L1，设上述第2距离为L2，设上述第3距离为L3，设相邻的上述沟槽的间隔为L4，
上述第1距离、上述第2距离、上述第3距离以及相邻的上述沟槽的间隔满足L1≥L3×(－0.30×L4+1.53)－L2。
2.如权利要求1所述的半导体装置，其特征在于，
上述第1距离、上述第2距离、上述第3距离以及相邻的上述沟槽的间隔是L1＝L3×(－0.30×L4+1.53)－L2。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004041892A1 (de) * 2004-08-30 2006-03-02 Infineon Technologies Ag Trenchtransistor
CN101165897A (zh) * 2006-10-20 2008-04-23 三菱电机株式会社 半导体装置及其制造方法
CN101494239A (zh) * 2009-02-27 2009-07-29 电子科技大学 一种高速igbt
JP2010177243A (ja) * 2009-01-27 2010-08-12 Denso Corp 半導体装置

Family Cites Families (11)

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JP5286706B2 (ja) 2007-07-10 2013-09-11 三菱電機株式会社 電力用半導体装置とその製造方法
JP5150195B2 (ja) 2007-10-16 2013-02-20 株式会社東芝 縦型半導体装置
JP4947111B2 (ja) * 2008-12-10 2012-06-06 株式会社デンソー 半導体装置の製造方法
JP5582102B2 (ja) 2010-07-01 2014-09-03 株式会社デンソー 半導体装置
WO2013005304A1 (ja) 2011-07-05 2013-01-10 三菱電機株式会社 半導体装置
JP2014138048A (ja) 2013-01-16 2014-07-28 Sumitomo Electric Ind Ltd 炭化珪素半導体装置
JP5967065B2 (ja) * 2013-12-17 2016-08-10 トヨタ自動車株式会社 半導体装置
JP2015153784A (ja) * 2014-02-10 2015-08-24 トヨタ自動車株式会社 半導体装置の製造方法及び半導体装置
US9224816B2 (en) * 2014-05-21 2015-12-29 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device
JP6830767B2 (ja) * 2016-06-14 2021-02-17 株式会社デンソー 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004041892A1 (de) * 2004-08-30 2006-03-02 Infineon Technologies Ag Trenchtransistor
CN101165897A (zh) * 2006-10-20 2008-04-23 三菱电机株式会社 半导体装置及其制造方法
JP2010177243A (ja) * 2009-01-27 2010-08-12 Denso Corp 半導体装置
CN101494239A (zh) * 2009-02-27 2009-07-29 电子科技大学 一种高速igbt

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