CN109887937A - 形成再分布线的方法及用该方法制造半导体器件的方法 - Google Patents

形成再分布线的方法及用该方法制造半导体器件的方法 Download PDF

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Publication number
CN109887937A
CN109887937A CN201811351387.XA CN201811351387A CN109887937A CN 109887937 A CN109887937 A CN 109887937A CN 201811351387 A CN201811351387 A CN 201811351387A CN 109887937 A CN109887937 A CN 109887937A
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layer
semiconductor substrate
redistribution lines
redistribution
metal
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CN109887937B (zh
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赵庸会
沈钟辅
延承勋
李元一
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本申请提供了形成再分布线的方法及用该方法制造半导体器件的方法。所述制造半导体器件的方法包括：提供了具有顶表面和与所述顶表面相对的底表面的半导体衬底，所述顶表面上形成有滤色器和微透镜；在所述半导体衬底的底表面上形成再分布线；在所述半导体衬底的底表面上形成覆盖所述再分布线的钝化层。在形成所述再分布线和所述钝化层之后，在避免对所述滤色器和所述微透镜造成热损坏的温度下，在所述再分布线与所述钝化层之间形成氧化物层。

Description

形成再分布线的方法及用该方法制造半导体器件的方法
优先权声明
本申请要求于2017年12月6日在韩国知识产权局提交的韩国专利申请No.10-2017-0166859的优先权，其内容通过引用整体并入本文。
技术领域
本发明构思涉及采用半导体的器件(诸如包括光电二极管的图像传感器)。特别地，本发明构思涉及一种在制造半导体器件时形成再分布线的方法。
背景技术
半导体器件的再分布线是在整个器件中分配各种信号的导线。再分布线易出现诸如构成线的组成元素的氧化和电化学迁移的问题，而这又降低了包含这些再分布线的器件的可靠性。
发明内容
根据本发明构思，提供了一种制造半导体器件的方法，所述方法包括：提供基底结构，所述基底结构包括具有顶表面和与所述顶表面相对的底表面的半导体衬底，以及在所述半导体衬底的顶表面上的滤色器和微透镜；在所述半导体衬底的底表面上形成再分布线；所述半导体衬底的底表面上形成覆盖所述再分布线的钝化层；以及在所述再分布线上自发地形成氧化物层，并在明确为避免对所述滤色器和所述微透镜造成热损坏的温度范围内，在所述再分布线与所述钝化层之间生长氧化物层。
根据本发明构思，还提供了一种制造半导体器件的方法，所述方法包括：提供基底结构，所述基底结构包括具有有源表面和与所述有源表面相对的无源表面的半导体衬底，以及在所述有源表面上的滤色器和微透镜；在所述半导体衬底的所述无源表面上形成再分布金属层；在所述半导体衬底的所述无源表面上形成覆盖所述再分布金属层的有机绝缘层；以及在所述再分布金属层与所述有机绝缘层之间生长金属氧化物层至预定厚度。在形成所述有机绝缘层之后进行的工艺期间，在明确为避免对所述滤色器和所述微透镜造成热损坏的温度范围内，使所述金属氧化物层生长至所述预定厚度。
根据本发明构思，还提供了一种形成再分布线的方法，所述方法包括：提供基底结构，所述基底结构包括具有有源表面和无源表面的半导体衬底，以及未达到所述无源表面的贯通电极；使所述半导体衬底的所述无源表面凹陷，以暴露所述贯通电极；随后在所述半导体衬底的所述无源表面上形成所述再分布线，所述再分布线电连接到所述贯通电极；形成覆盖所述再分布线的有机钝化层；以及在等于或小于250℃的温度下，使所述再分布线与所述有机钝化层之间的天然金属氧化物层生长到50nm至200nm的厚度。
根据本发明构思，还提供了一种制造半导体器件的方法，所述方法包括：提供基底结构，所述基底结构包括具有面向相反方向的顶表面和底表面的半导体衬底、在所述底表面处暴露的通路、以及在所述半导体衬底的所述顶表面上的滤色器和微透镜；形成金属再分布线，所述金属再分布线沿所述半导体衬底的底表面延伸并到达所述通路上；形成覆盖所述金属再分布线的钝化层；以及随后通过在最高温度低于所述滤色器和所述微透镜中的每一个的温度额定值的温度范围执行工艺，来完成所述半导体器件的制造，其中在所述温度范围，在所述金属再分布线与所述钝化层之间生长氧化物层，并且当所述工艺已经完成时，所述氧化物层的厚度为50nm至200nm。
附图说明
图1A是根据本发明构思的半导体器件的示例的截面图。
图1B是包括图1A的半导体器件的半导体封装件的截面图。
图2A、图2B、图2C、图2D、图2E、图2F、图2G、图2H、图2I、图2J、图2K、图2L和图2M是根据本发明构思的半导体器件在其制造过程中的截面图，并且一起示出了一种制造半导体器件的方法的示例。
图3A、图3B、图3C和图3D是根据本发明构思的半导体器件在其制造过程中的截面图，并且一起例示了制造半导体器件的方法的另一示例。
具体实施方式
下面将结合附图描述根据本发明构思的形成再分布线的方法以及制造包括该再分布线的半导体器件的方法。
图1A示出了根据本发明构思制造的半导体器件的示例。
参照图1A，半导体器件10可以包括：半导体衬底100，该半导体衬底100具有彼此面对的顶表面100a和底表面100c；多个光电二极管720，该多个光电二极管720通过器件隔离层710彼此分离地设置在半导体衬底100中；金属线结构740，该金属线结构740被设置在半导体衬底100的顶表面100a上；多个滤色器760，该多个滤色器760被设置在金属线结构740上；多个微透镜770，该多个微透镜770对应于多个滤色器760。顶表面100a可以是半导体衬底100的有源表面，底表面100c可以是半导体衬底100的无源表面。
金属线结构740可以包括堆叠的多个电介质层746、电连接到设置在半导体衬底100中的多个存储节点730的多个通路742以及多条金属线744。金属线结构740可以被具有单层或多层结构的上部绝缘层750覆盖。
半导体器件10还可以包括：贯通电极200，该贯通电极200延伸穿过半导体衬底100以实现与金属线结构740的电连接；再分布线430，该再分布线430被设置在半导体衬底100的底表面100c上并且电连接到贯通电极200；以及钝化层500，该钝化层500覆盖再分布线430。
贯通电极200可以耦接到金属线结构740的金属线744。贯通电极200可以通过通路绝缘层220与半导体衬底100电绝缘。阻挡层210还可以被包括在贯通电极200与通路绝缘层220之间，以防止组成元素的成分(例如铜，在下文中简称为贯通电极200的“成分”)扩散到半导体衬底100中。
第一下部绝缘层310和第二下部绝缘层320可以顺序地堆叠在半导体衬底100的底表面100c上。第一下部绝缘层310和第二下部绝缘层320可以具有彼此不同的绝缘材料。例如，第一下部绝缘层310可以是氧化硅层，第二下部绝缘层320可以是氮化硅层。
再分布线430可以被设置在第二下部绝缘层320上并且电连接到贯通电极200。再分布线430可以包括诸如铜的金属。可以将耦接到贯通电极200的阻挡层410和阻挡层410上的晶种层420设置在再分布线430与第二下部绝缘层320之间。或者，可以在半导体衬底100的底表面100c与再分布线430之间仅插入一个下部绝缘层，即仅插入单层绝缘材料。
在任何一种情况下，再分布线430的厚度都可以等于或小于约15μm，并且优选地为约10μm至约15μm。这里，并且在下面的描述中，术语“约”用于表示由于与制造工艺相关的正常公差和变化而产生的与设计规范(枚举值)的微小差异。因此，给出的范围可以包括枚举值。
钝化层500可以被设置在半导体衬底100的底表面100c上同时覆盖再分布线430。钝化层500可以包括(是或包含)无机绝缘层或有机绝缘层。例如，钝化层500可以包括(是或包含)有机绝缘层，例如聚苯并恶唑(polybenzoxazole，PBO)。钝化层500的厚度可以是约3μm至约5μm。
再分布线430可以被氧化物层440覆盖。氧化物层440可以是或包括自发氧化物层(或天然金属氧化物层)，该自发氧化物层是在钝化层500形成之后的后续工艺中钝化层500中的氧和再分布线430的成分(例如，铜)彼此发生反应时自动生长的。自发氧化物层是指无需专用于该目的的任何工艺(例如，热氧化或退火工艺)而(首先)形成的任何氧化物层。自发氧化物可以由于固体暴露在空气中(在室温下)或者由于固体与另一种含氧固体接触而形成在固体上。
在本发明构思的示例中，氧化物层440可以在低温状况下(例如，等于或小于约250℃的温度)生长几个小时至几十个小时(例如，小于约10小时)，这避免了对滤色器760和/或微透镜770的热损坏。特别地，滤色器760和微透镜770具有温度额定值额定值，该温度额定值是这些元件可以长时间承受而不会劣化的最高温度。因此，温度额定值可以是基于材料(例如，制成滤色器760和微透镜770的聚合物)的具体类型的已知量或规格。氧化物层440可以在低温下和/或在短工艺时间内自动生长，并且相应地氧化物层440的厚度T为约50nm至约200nm，优选地为约100nm。
外部端子630可以电连接到再分布线430。阻挡层610和晶种层620可以被设置在外部端子630与再分布线430之间，并且覆盖层640可以被设置在外部端子630上。外部端子630可以是凸起形状。或者，外部端子630可以是焊球。
根据本发明构思的一些示例，氧化物层440用作防止再分布线430的成分(例如，铜)迁移的屏障。如果氧化物层440的厚度T小于约50nm，那么再分布线430的成分(例如，铜)很容易迁移。如果氧化物层440的厚度T大于约200nm，则氧化物层440将易于破裂，并且这种破裂的氧化物层440不能有效地用作防止再分布线430的成分(例如，铜)迁移的屏障。这些问题中的任何一个都可能导致再分布线430或半导体器件10的电气故障。
然而，如上所述，根据本发明构思，氧化物层440在相对低的温度和/或相对短的时间内生长，从而允许其实现约50nm至约200nm，优选地约100nm的厚度T。结果，氧化物层440可以基本上没有铜或裂缝，否则会导致半导体器件10的电气故障。
图1B示出了包括图1A的半导体器件的半导体封装件的示例。
参照图1B，半导体器件10和电子器件20可以进行电连接以构成半导体封装件1。例如，焊球30可以形成在半导体器件10的外部端子630与电子器件20的外部端子23之间，并且可以设置环氧模制化合物(EMC)并使其固化以形成模制层40。电子器件20可以是或包括存储芯片、逻辑芯片或其组合。或者，电子器件20可以是或包括印刷电路板(PCB)。用于形成焊球30的回流工艺和用于形成模制层40的固化工艺可以在约室温(例如，约25℃)至等于或小于约250℃的温度范围内进行。
可以提供半导体器件10作为包括切割(sawing)工艺的晶片级工艺的一部分。更具体地，多个芯片级电子器件20可以被设置在已形成有多个半导体器件10的晶片上，可以形成模制层40，然后可以执行将这样的结构分离为单独的半导体封装件1的切割工艺。作为另一示例，其上已形成有多个电子器件20的晶片可以被设置在其上已形成有多个半导体器件10的另一晶片上，然后形成模制层40，然后可以执行切割工艺，以将层叠晶片结构分离成多个单独的半导体封装件1。
半导体器件10的氧化物层440可能受到在制造半导体封装件1所需的一个或更多个热工艺(例如，回流工艺和固化工艺)中产生的热量，从而继续生长。这些热工艺可以在约室温至等于或小于约250℃的温度范围内进行，此外，从形成氧化物层440的初始阶段到制造半导体封装件1的最后阶段可能需要约几个小时至几十个小时(例如，小于约10小时)。以这种方式，氧化物层440的厚度T可以呈现为约50nm至约200nm，或者更具体地约100nm，正如上面参照图1A所讨论的。
图2A至图2M示出了根据本发明构思的制造半导体器件的方法。
参照图2A，作为基底结构的一部分的半导体衬底100可以被设置为具有面向相反方向的第一表面100a和第二表面100b。半导体衬底100可以是或可以包括具有构成图像传感器的各种组件的半导体晶片(例如，硅晶片)。例如，半导体衬底100可以包括器件隔离层710、光电二极管720和多个存储节点730。基底结构还可以包括衬底100上的金属线结构740、多个滤色器760和多个微透镜770。滤色器760和微透镜770可以由聚合物形成。
金属线结构740可以形成在半导体衬底100的第一表面100a上。金属线结构740的形成可以包括：沉积诸如氧化硅的绝缘材料，以及沉积并图案化诸如铜、铝或钨的金属材料。可以对聚合物进行沉积和图案化，从而在金属线结构740上形成滤色器760和微透镜770。其他组件可以类似于上面参照图1A所述的那些组件。
贯通电极或通路200可以形成在半导体衬底100中的盲孔中。因此，贯通电极200可以延伸到半导体衬底100中，但是不到达半导体衬底100的第二表面100b。阻挡层210和通路绝缘层220可以在形成贯通电极200之前形成，以便覆盖贯通电极200的侧表面和底表面。贯通电极200可以通过电镀或沉积工艺来形成，在该电镀或沉积工艺中诸如铜、钨或多晶硅的导电材料被形成在阻挡层210上。可以通过在绝缘层220上沉积钛(Ti)、氮化钛(TiN)、钛钨(TiW)、钽(Ta)、氮化钽(TaN)、氮化钨(WN)等来形成阻挡层210。可以通过在半导体衬底100中的盲孔中沉积氧化硅、氮化硅等来形成通路绝缘层220。
参照图2B，半导体衬底100的第二表面100b可以凹陷到贯通电极200的端部下方。例如，载体90可以粘附到半导体衬底100的第一表面100a，并且半导体衬底100可以颠倒过来。载体90可以包括半导体晶片。可以使用粘合剂将载体90粘附到半导体衬底100。
第二表面100b的凹陷可能需要研磨、蚀刻或其组合。凹陷可以形成第三表面100c，并且使得贯通电极200突出超过第三表面100c。在本说明书中，第一表面100a可以被称为顶表面，第三表面100c可以被称为底表面。除非另有说明，否则顶表面100a可以表示半导体衬底100的有源表面，底表面100c可以表示半导体衬底100的无源表面。
参照图2C，半导体衬底100的底表面100c可以依次覆盖有：覆盖贯通电极200的第一下部绝缘层310、覆盖第一下部绝缘层310的第二下部绝缘层320。第一下部绝缘层310和第二下部绝缘层320可以具有彼此不同的绝缘材料。例如，第一下部绝缘层310可以由氧化硅形成，第二下部绝缘层320可以由氮化硅形成。在其他示例中，不形成第二下部绝缘层320。
参照图2D，可以执行诸如化学机械抛光(CMP)或回蚀工艺的平坦化工艺以露出贯通电极200，之后可以在半导体衬底100的底表面100c上形成掩模图案50或简称“掩模”。第一下部绝缘层310和第二下部绝缘层320可以被平坦化。掩模图案50可以具有暴露贯通电极200的凹槽55。掩模图案50可以由诸如光刻胶的有机材料或者诸如氧化硅或氮化硅的无机材料形成。
参照图2E，阻挡层410、晶种层420和牺牲层60可以形成在半导体衬底100的底表面100c上。阻挡层410可以形成在凹槽55中和掩模图案50上，晶种层420可以形成在阻挡层410上。牺牲层60可以填充凹槽55。阻挡层410可以由钛(Ti)、氮化钛(TiN)、钛钨(TiW)、钽(Ta)、氮化钽(TaN)、氮化钨(WN)等形成。晶种层420可以由铜(Cu)、钌(Ru)、镍(Ni)、钨(W)等形成。牺牲层60可以由诸如光刻胶的有机材料或者诸如氧化硅或氮化硅的无机材料形成。
参照图2F，晶种层420可以被部分地去除。可以采用湿法蚀刻工艺来部分地去除晶种层420。湿法蚀刻工艺可以允许晶种层420保留在凹槽55中。然后，晶种层420可以被限制在牺牲层60的底部与阻挡层410之间的凹槽55中。或者，晶种层420可以在凹槽55中沿着牺牲层60的侧表面在牺牲层60的底部与阻挡层410之间延伸。
参照图2G，可以从凹槽55中去除牺牲层60，并且可以在凹槽55中形成再分布线430。当去除牺牲层60时，晶种层420可以暴露在凹槽55中。暴露的晶种层420可以用于在凹槽55中电镀再分布线430。再分布线430可以由诸如铜(Cu)的金属形成。此时，晶种层420与再分布线430之间的界面在视觉上可能不可辨别，即，晶种层420可以结合到再分布线430中。然而，为了说明的目的，将继续在图中示出晶种层420。再分布线430的厚度等于或小于约15μm，并且优选地为约10μm至约15μm。
参照图2H，阻挡层410可以被部分地去除，使得其残余部分被留在凹槽55中。可以采用湿法蚀刻工艺来部分地去除阻挡层410。然后可以将阻挡层410限制在晶种层420与第二下部绝缘层320之间的凹槽55中。或者，阻挡层410可以被限制在凹槽55中，同时沿着再分布线430的侧表面在晶种层420与第二下部绝缘层320之间延伸。
参照图2I，可以去除掩模图案50，并且可以形成钝化层500。钝化层500可以是诸如氧化硅或氮化硅层的无机绝缘层，或者诸如聚酰亚胺(PI)或聚苯并恶唑(PBO)层的有机绝缘层。例如，可以提供聚苯并恶唑(PBO)并将其固化以形成钝化层500。钝化层500的厚度可以是约3μm至约5μm。
参照图2J，可以将钝化层500图案化以形成部分地暴露再分布线430的开口550，之后可以在钝化层500上顺序地形成阻挡层610和晶种层620。阻挡层610可以在开口550中与再分布线430接触。阻挡层610可以由钛(Ti)、氮化钛(TiN)、钛钨(TiW)、钽(Ta)、氮化钽(TaN)、氮化钨(WN)等形成。晶种层620可以由铜(Cu)、钌(Ru)、镍(Ni)、钨(W)等形成。
参照图2K，暴露开口550的掩模图案70可以形成在晶种层620上。掩模图案70可以由诸如光刻胶的有机材料或者诸如氧化硅或氮化硅的无机材料形成。
参照图2L，外部端子630和覆盖层640可以形成在开口550中。外部端子630可以通过使用晶种层620的电镀工艺来形成。覆盖层640可以通过在外部端子630上电镀金属来形成。外部端子630可以由镍、钨、铝、铜等形成。覆盖层640可以由金、镍、银等形成。
参照图2M，可以去除掩模图案70。可以对由于去除掩模图案70而暴露的阻挡层610和晶种层620执行去除工艺。可以采用湿法蚀刻工艺去除阻挡层610和晶种层620。当去除载体90时，可以视为已经完成了图1A的半导体器件10。如图1B所示，半导体器件10可以通过焊球30电连接到电子器件20，并由模制层40包覆，该工艺可以完成半导体封装件1的制造。
根据本发明构思的一些示例，在如上面参照图2I所讨论的形成钝化层500之后，后续工艺(例如，沉积工艺、电镀工艺、回流工艺和固化工艺)可以提供热量，通过该热量可以在再分布线430与钝化层500之间形成氧化物层440。例如，在后续工艺期间，后续工艺所需的热量(即，后续工艺的热状况)可以使钝化层500中的氧与再分布线430的成分(例如，铜)反应。该反应可以形成并生长出天然金属氧化物层或氧化物层440。注意，尽管仅在图2M中示出了氧化物层440(生长到其全部厚度)，但是氧化物层在该阶段之前形成，而在图中(例如，在图2G至图2L中的任何一幅图中)省略了氧化物层的任何开始。
后续工艺可以在室温(例如，约25℃)至约250℃的范围内的相对低的温度范围内进行，并且选择低于耐热性差的组件(诸如由聚合物形成的滤色器760和/或微透镜770)的温度额定值的温度，以避免对这些组件的热损坏。氧化物层440的厚度T不仅取决于热量，还取决于工艺时间。半导体器件10或半导体封装件1被设计成使得在形成钝化层500之后，仅需要几个至几十个小时，优选地少于约10个小时的工艺时间来完成其制造。这里，制造完成的时间可以与产生大量热量的最后的工艺(例如，温度是工艺配方的一部分的最后的工艺)的终止一致。
如上面参照图1A所讨论的，氧化物层400可以用作防止再分布线430的成分(例如，铜)迁移的屏障。当氧化物层440的厚度T小于约50nm或大于约200nm时，氧化物层440不会充当足够防止电化学迁移的屏障或者氧化物层440易于破裂。根据本发明构思，低温条件和/或短工艺时间使氧化物层440形成的厚度T在约50nm至约200nm的范围内，优选地为约100nm。具有这样的厚度T的氧化物层440将不会对半导体器件10和/或半导体封装件1的电特性有不利影响。
再参照图1A，再分布线430可以被阻挡层410和氧化物层440围绕。当在截面中观察时，阻挡层410可以具有覆盖再分布线430的顶表面的线形状，并且氧化物层440可以具有覆盖再分布线430的底表面和侧表面的支架(bracket)形状。再分布线430的顶表面可以面向半导体衬底100的底表面100c，再分布线430的底表面可以与再分布线430的顶表面相对。
图3A至图3D示出了根据本发明构思的制造半导体器件的方法的另一示例。
参照图3A，可以执行与上面参照图2A至图2E讨论的工艺相同或相似的工艺，以在半导体衬底100的底表面100c上形成阻挡层410和晶种层420。代替图2E的牺牲层60，形成金属层430a来填充凹槽55。金属层430a可以通过电镀诸如铜的金属来形成。
参照图3B，可以通过诸如化学机械抛光(CMP)或回蚀工艺的平坦化工艺来使金属层430a平坦化。平坦化工艺可以在凹槽55中形成再分布线430。可以继续进行平坦化工艺直到暴露掩模图案50。
参照图3C，可以执行与上面参照图2I至图2M讨论的工艺相同或相似的工艺，以在半导体衬底100的底表面100c上形成覆盖再分布线430的钝化层500，并形成耦接到再分布线430的外部端子630。
参照图3D，当载体90被去除时，可以制造半导体器件10a。类似于图1A的半导体器件10，半导体器件10a的氧化物层440的厚度T在约50nm至约200nm的范围内，优选地为约100nm。当在截面中观察时，氧化物层440可以具有覆盖再分布线430的底表面的线形状，阻挡层410可以具有覆盖再分布线430的顶表面和侧表面的支架形状。
根据本发明构思，再分布线上的氧化物层能够防止再分布线的成分的迁移，并且具有阻止裂纹萌生及蔓延的厚度。因此，本发明构思能够提供高可靠性的再分布线和/或包括该再分布线的半导体器件。
最后，不应将本发明构思的该详细描述理解为限于本文所阐述的示例。更确切地说，在不脱离由所附权利要求限定的发明构思的精神和范围的情况下，本发明构思可以应用于示例的各种组合、修改和变化。

Claims (25)

1.一种制造半导体器件的方法，所述方法包括：
提供基底结构，所述基底结构包括具有顶表面和与所述顶表面相对的底表面的半导体衬底，以及在所述半导体衬底的顶表面上的滤色器和微透镜；
在所述半导体衬底的底表面上形成再分布线；
在所述半导体衬底的底表面上形成覆盖所述再分布线的钝化层；以及
在所述再分布线上自发地形成氧化物层，并在明确为避免对所述滤色器和所述微透镜造成热损坏的温度范围内，在所述再分布线与所述钝化层之间生长所述氧化物层。
2.根据权利要求1所述的方法，其中，所述钝化层由含氧材料形成，并且所述钝化层中的所述氧与所述再分布线的材料的成分进行反应以形成所述氧化物层。
3.根据权利要求1所述的方法，其中，在形成所述钝化层之后进行的工艺期间自动发生所述氧化物层的生长，使得在已经完成所述半导体器件的制造时，所述氧化物层的厚度为50nm至200nm。
4.根据权利要求1所述的方法，其中，所述氧化物层在已经完成所述半导体器件的制造时自动生长至具有100nm的厚度。
5.根据权利要求1所述的方法，其中，所述温度范围的最高温度为250℃。
6.根据权利要求1所述的方法，其中，形成所述再分布线包括：
在所述半导体衬底的底表面上形成掩模图案；
在所述半导体衬底的被所述掩模图案暴露的表面上顺序地形成阻挡层和晶种层；以及
通过使用所述晶种层的电镀工艺来形成金属层。
7.根据权利要求6所述的方法，其中，所述基底结构包括贯通电极，所述贯通电极穿透所述半导体衬底并且在所述半导体衬底的底表面处暴露，
所述阻挡层被形成为耦接到所述贯通电极。
8.根据权利要求6所述的方法，其中，所述再分布线的顶表面面向所述半导体衬底的底表面，所述再分布线的底表面背离所述半导体衬底，所述再分布线的侧表面将所述再分布线的顶表面与所述再分布线的底表面相互连接，
所述阻挡层被形成为覆盖所述再分布线的顶表面，以及
所述氧化物层覆盖所述再分布线的底表面和所述再分布线的侧表面。
9.根据权利要求1所述的方法，其中，所述钝化层的形成包括：在所述再分布线上并沿着所述半导体衬底的未被所述再分布线覆盖的底表面形成聚苯并恶唑层。
10.一种制造半导体器件的方法，所述方法包括：
提供基底结构，所述基底结构包括具有有源表面和与所述有源表面相对的无源表面的半导体衬底，以及在所述有源表面上的滤色器和微透镜；
在所述半导体衬底的所述无源表面上形成再分布金属层；
在所述半导体衬底的所述无源表面上形成覆盖所述再分布金属层的有机绝缘层；以及
在所述再分布金属层与所述有机绝缘层之间生长金属氧化物层至预定厚度，
其中，在形成所述有机绝缘层之后进行的工艺期间，在明确为避免对所述滤色器和所述微透镜造成热损坏的温度范围内，使所述金属氧化物层生长到所述预定厚度。
11.根据权利要求10所述的方法，其中，所述金属氧化物层是通过所述再分布金属层与所述有机绝缘层之间的自发反应形成的。
12.根据权利要求10所述的方法，其中，所述温度范围的最高温度为250℃。
13.根据权利要求10所述的方法，其中，所述预定厚度为50nm至200nm。
14.根据权利要求10所述的方法，其中，所述基底结构的提供包括：
形成穿过所述半导体衬底的贯通电极；以及
使所述半导体衬底变薄以露出所述无源表面，
其中，所述贯通电极在所述半导体衬底的所述无源表面处被暴露。
15.根据权利要求14所述的方法，其中，所述再分布金属层的形成包括：
在所述半导体衬底的所述无源表面上形成掩模，所述掩模具有暴露所述贯通电极的凹槽；
在所述半导体衬底的所述无源表面上形成阻挡层，所述阻挡层耦接到所述贯通电极；
在所述阻挡层上形成晶种层；以及
使用所述晶种层执行电镀工艺，以在所述凹槽中形成包含铜的金属层。
16.根据权利要求15所述的方法，其中，所述有机绝缘层的形成包括：
在所述铜上提供聚苯并恶唑；以及
使所述聚苯并恶唑固化。
17.根据权利要求10所述的方法，其中，所述基底结构的提供包括：在所述半导体衬底的所述有源表面上形成金属线结构，其中所述滤色器和所述微透镜堆叠在所述金属线结构上；
所述方法还包括形成外部端子，所述外部端子延伸穿过所述有机绝缘层到达所述再分布金属层。
18.一种形成再分布线的方法，所述方法包括：
提供基底结构，所述基底结构包括具有有源表面和无源表面的半导体衬底，以及未达到所述无源表面的贯通电极；
使所述半导体衬底的所述无源表面凹陷，以暴露所述贯通电极；
随后在所述半导体衬底的所述无源表面上形成所述再分布线，所述再分布线电连接到所述贯通电极；
形成覆盖所述再分布线的有机钝化层；以及
在等于或小于250℃的温度下，使所述再分布线与所述有机钝化层之间的天然金属氧化物层生长到50nm至200nm的厚度。
19.根据权利要求18所述的方法，其中，所述再分布线包括铜，并且所述有机钝化层包括聚苯并恶唑。
20.根据权利要求18所述的方法，其中，所述半导体衬底的所述无源表面的凹陷包括：
将载体粘附到所述半导体衬底的所述有源表面；以及
对粘附有所述载体的所述半导体衬底进行研磨。
21.根据权利要求18所述的方法，还包括：在所述半导体衬底的所述无源表面已经凹陷之后，在所述无源表面上形成覆盖所述贯通电极的绝缘层，以及
使所述绝缘层平坦化，以形成所述贯通电极出现在所述绝缘层的表面处的平坦化结构，
其中，所述再分布线被形成为电连接到所述平坦化结构的所述贯通电极。
22.根据权利要求21所述的方法，其中，所述再分布线的形成包括：
在所述绝缘层的表面上形成包括凹槽的掩模图案，所述凹槽暴露在平坦化的所述绝缘层的表面处出现的所述贯通电极，
在包括所述掩模图案的所得结构上顺序地形成阻挡层和晶种层；以及
使用晶种层执行电镀工艺，以在所述凹槽中形成包含铜的金属层。
23.根据权利要求18所述的方法，其中，在形成所述有机钝化层之后，所述天然金属氧化物层经过10小时的过程形成100nm的厚度。
24.一种制造半导体器件的方法，所述方法包括：
提供基底结构，所述基底结构包括具有面向相反方向的顶表面和底表面的半导体衬底、在所述底表面处暴露的通路、以及在所述半导体衬底的所述顶表面上的滤色器和微透镜；
形成金属再分布线，所述金属再分布线沿所述半导体衬底的底表面延伸并到达所述通路上；
形成覆盖所述金属再分布线的钝化层；以及
随后通过在最高温度低于所述滤色器和所述微透镜中的每一个的温度额定值的温度范围执行工艺，来完成所述半导体器件的制造，
其中在所述温度范围，在所述金属再分布线与所述钝化层之间生长氧化物层，并且当所述工艺已经完成时，所述氧化物层的厚度为50nm至200nm。
25.根据权利要求24所述的方法，其中，所述再分布线的形成包括：
在所述半导体衬底的底表面上形成掩模，所述掩模包括暴露所述通路的凹槽；
在包括所述掩模的所得结构上顺序地形成阻挡层和晶种层；以及
使用所述晶种层执行电镀工艺，以在所述凹槽中形成金属层。
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