CN101911292B - 半导体的微焊盘形成 - Google Patents

半导体的微焊盘形成 Download PDF

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CN101911292B
CN101911292B CN2008801238236A CN200880123823A CN101911292B CN 101911292 B CN101911292 B CN 101911292B CN 2008801238236 A CN2008801238236 A CN 2008801238236A CN 200880123823 A CN200880123823 A CN 200880123823A CN 101911292 B CN101911292 B CN 101911292B
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semiconductor device
copper
tin
post
outside contact
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CN101911292A (zh
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V·马修
E·阿科斯塔
R·查特杰
S·S·加西亚
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

一种方法，形成到第一半导体器件(12，52，74)的外部接触件(14，54，78)的微焊盘(30，70，42)。在外部接触件上形成铜柱(＝20，24，66，88，82)。柱在第一半导体器件的表面上延伸。将铜柱浸入锡的溶液中。锡(28)置换柱的铜的至少95％，并优选大于99％。结果产生具有小于5％的重量的铜的锡微焊盘。由于微焊盘基本为纯锡，因此在不接合第一半导体器件的微焊盘的时间期间不会形成金属间接合。由于不形成金属间接合，因此导致较小的微焊盘尺寸。当将第一半导体器件接合到上覆的第二半导体器件时，接合尺寸不显著增加堆叠芯片的高度。

Description

半导体的微焊盘形成
技术领域
本发明总的涉及半导体，更具体地，涉及半导体的外部电连接。
背景技术
通过在三维(3D)叠层中堆叠两个或更多的集成电路，将集成电路递增地彼此连接。例如，已经使用这种技术通过堆叠两个存储器集成电路来倍增存储器的量。一种替代形式是将集成电路与半导体晶片堆叠。堆叠的集成电路通过芯片接合进行彼此电接触。芯片接合利用一个集成电路上的接合焊盘与另一集成电路上的另一接合焊盘接合。这些接合焊盘通常称为“微焊盘”(micropad)。来自两个不同的管芯或晶片的微焊盘的热压接合提供堆叠的管芯的机械和电内层连接。已知的接合工艺使用第一集成电路的接合焊盘处的铜微焊盘以及第二集成电路的接合焊盘处的铜和锡。两个接合焊盘被对准并接合在一起，其中第一集成电路的接合焊盘的铜接合到第二集成电路的接合焊盘的锡。但是，在包括室温的低温下发生第二集成电路的铜和锡的内扩散，从而形成诸如Cu3Sn和Cu6Sn5的金属间化合物。厚的金属间化合物是脆的，且对与接合焊盘相关联的可靠性问题有贡献。例如，由金属间化合物构成的刚性接合焊盘易于剪切和应力断裂。当形成足够量的金属间化合物时，必须添加附加的锡以保证材料保持可接合。附加的锡增加了厚度，这是不期望的。并且，一直到非常高的温度，例如600摄氏度，这种金属间化合物都稳定，从而变得不可接合。如此高的温度过大而对于接合材料不可用，因为完整的集成电路的其他部分在经受如此高温度时退化或失效。
附图说明
由附图以实例的方式示出本发明，而非由附图限制本发明，在附图中相似的附图标记表示相似的元件。图中的元件出于简洁和清楚的目的而示出，并不一定按比例绘制。
图1-9以截面图的形式示出被形成用于连接至第二半导体的第一半导体的微焊盘结构的一种形式；
图10-13以截面图的形式示出被形成用于连接至第二半导体的第一半导体的微焊盘结构的另一种形式；以及
图14-20以截面图的形式示出被形成用于连接至第二半导体的第一半导体的微焊盘结构的又一种形式。
本领域技术人员理解图中的元件出于简洁和清楚的目的而示出，并不一定按比例绘制。例如，图中某些元件的尺寸可以相对于其他元件被放大以帮助提高对本发明的实施例的理解。
具体实施方式
图1所示的是根据本发明的一种形式处理的半导体晶片10的一部分的截面图。示出半导体器件12，其中半导体器件12是半导体晶片10上的管芯的一部分。在半导体器件12内是具有晶体管和大量电接触件的衬底。为了便于例示，在半导体器件12的衬底内以接触件14的形式示出单个电接触件。接触件14是半导体器件12的外部接触件，并提供从半导体器件12的初始暴露表面到在半导体器件12的下层制造的有源电路(未示出)的电接触。在半导体器件12上以保留接触件14的主要部分被暴露的方式图案化的是钝化层16。钝化层16是电绝缘材料。在一种形式中，钝化层16是一层绝缘材料。在另一种形式中，钝化层16可以用多层绝缘材料实现。应该理解，可以使用诸如氮氧化硅、氮化硅、TEOS膜、等离子体增强氮化物及其组合的钝化材料。覆在钝化层16上面的是共形的阻挡层18。阻挡层18用于提升粘附力并用作对铜和锡的阻挡物。可以使用各种阻挡材料，包括钛钨(TiW)、氮化钛(TiN)或钨(w)。可以采用其它阻挡材料。阻挡层18直接形成于接触件14上。
图2所示的是半导体晶片10的进一步处理。形成覆在阻挡层18上面的共形的种子层20。在一种形式中，种子层20是铜。可以使用其它金属。在本实施例中使用铜，以期辅助作为在接触件14上覆盖铜的扩展中的种子。在形成种子层20之后，形成光致抗蚀剂22的图案化层，其中接触件14上方的区域在图案中敞开以暴露于随后的处理。使用传统的光致抗蚀剂材料作为光致抗蚀剂22的层。
图3所示的是半导体晶片10的进一步处理，其中半导体晶片10被暴露于铜电镀槽26。所使用的电镀溶液包含铜。在铜种子层20的辅助下，上覆接触件14和阻挡层18形成铜柱(copper stud)24。阻挡层18防止铜从种子层20迁移到接触件14。将半导体晶片10暴露到铜电镀槽26足够的时间量，并在该处理期间传递足够的电荷，以将铜柱24形成为上覆接触件14的期望高度。
图4所示的是半导体晶片10的进一步处理，其中半导体晶片10被从铜电镀槽26去除。还通过进行传统的湿法蚀刻去除光致抗蚀剂22的图案化层。因此，在处理中的此时，已经形成上覆接触件14的铜柱24，并且铜柱24在种子层的上表面上方延伸取决于处理条件的量，所述处理条件诸如是半导体晶片10在铜电镀槽26中的时间量和在铜电镀步骤期间传递的电荷量。
图5所示的是半导体晶片10的进一步处理，其中通过传统的湿法蚀刻移除种子层20和阻挡层18的暴露部分。在该湿法蚀刻之后，仅保留铜柱24下的种子层20和阻挡层18的这些部分。
图6所示的是半导体晶片10的进一步处理，其中将半导体晶片10放置在锡浸镀槽(tin immersion plating bath)28中预定时间量。锡浸镀槽28用于从铜柱24和种子层20中去除铜，并用纯锡(Sn)置换铜。锡至少置换铜柱24中的百分之九十五(95％)的铜，由此导致具有重量比小于百分之五(5％)的铜的锡微焊盘。随着铜离子进入镀槽28中的溶液，从铜柱24中去除铜。该反应是化学置换反应，其可以概括地表示为：
2Cu+Sn2+→2Cu++Sn
材料转移所需的时间量取决于各种因素，包括时间和温度。在一种形式中，锡浸镀槽28是含锡盐以及诸如络合剂和表面活性剂的其他成分的溶液，并被保持在大于等于60摄氏度一直到85摄氏度的温度范围内的温度下。
图7所示的是半导体晶片10的进一步处理，其中将半导体晶片10从锡浸镀槽28去除。结果导致纯锡微焊盘30存在，其中纯锡微焊盘30具有在1微米(0.001mm)到5微米(0.005mm)范围内的高度“L”。高度“L”大部分地由在图3中形成铜柱24时柱24的铜厚度的高度确定。
图8所示的是半导体晶片10的进一步处理，其中连接第二半导体晶片32以形成三维(3D)结构。第二半导体晶片32具有半导体器件34，半导体器件34具有连接至半导体器件34内的有源电路(未示出)的接触件38。与接触件38直接连接的是类似于半导体器件12的阻挡层18的阻挡层43。与阻挡层43连接的是铜微焊盘36。在纯锡微焊盘30具有在大致1微米至3微米范围内的高度的实施方式中，取决于微焊盘30的值，铜微焊盘36具有在3微米至10微米范围内的高度。在该范围内，铜微焊盘36是微焊盘30的高度的至少两倍，并且可以是三倍或更多倍高。与接触件38相邻的铜微焊盘36的基部由绝缘层41围绕。在一种形式中，绝缘层41是诸如氮化物或TEOS的钝化材料的层。利用压缩力40将半导体器件12物理接合到半导体器件34。当在足够高的温度下施加压缩力40以软化锡微焊盘30时，形成将接触件14电连接到接触件38的接合。在一种形式中，在超过锡的熔点(其为232摄氏度)的环境温度下将铜微焊盘36压向纯锡微焊盘30。
图9所示的是半导体晶片10和半导体晶片32的进一步处理。形成铜/锡金属间微接合(intermetallic microbond)42，其中微焊盘30的锡由微焊盘36的铜消耗以形成半导体器件12与半导体器件34之间的固态接合(solid bond)。铜微焊盘36的一部分保留铜，而不与微焊盘30的锡交互作用。因此，已经在两个半导体器件之间提供了改进的半导体接合焊盘。
图10所示的是形成晶片50的半导体器件52的微焊盘的另一实施例，其中微焊盘与另一半导体器件的另一微焊盘容易地接合。在所示的形式中，半导体器件52具有外部接触件54，接触件54连接至半导体器件52的衬底内的有源电路(未示出)。覆在半导体器件52上面的是图案化的钝化层56。在另一种形式中，图案化的钝化层56可以实现为多层。在一种形式中，图案化的钝化层56是诸如氮氧化硅、氮化硅、TEOS膜、等离子体增强氮化物及其组合的钝化材料。覆在图案化的钝化层56上面的是图案化的光致抗蚀剂58的层。图案化的光致抗蚀剂58的层具有暴露接触件54的敞口。在该敞口内且在接触件54上方形成选择性沉积的阻挡层62。阻挡层62与接触件54直接接触。可以使用各种选择性沉积的阻挡材料，例如钴钨硼(CoWB)、钴钨磷(CoWP)、钴钨磷硼(CoWPB)、钴钼硼(CoMoB)、钴钼磷(CoMoP)、镍钨磷(NiWP)或其组合。阻挡层62用于阻挡铜和锡与接触件54接触。在一种形式中，将半导体器件52放置在无电镀槽60中。无电镀槽60是作为市场可购得的无电镀溶液的溶液。
图11所示的是铜柱66的形成，作为将半导体器件52保留在无电镀槽64中相当量的时间以将铜沉积在阻挡层62上的结果。沉积铜柱66所需的时间量取决于许多变量，包括无电铜镀槽64中使用的铜溶液和温度。该时间量还由铜柱66的期望高度确定。在一种形式中，铜柱66形成为随后确定最终微焊盘结构的高度的高度。因此该高度可以改变。
图12所示的是半导体器件52的进一步处理，其中将半导体器件从无电铜镀槽64去除。随后通过湿法蚀刻或干法蚀刻去除图案化的光致抗蚀剂58。在去除图案化的光致抗蚀剂58的情况下，铜柱66从接触件54上的阻挡层62延伸。然后将半导体器件52放置在锡浸槽68中。锡浸槽68用于从铜柱66去除铜，并用基本上纯锡置换铜，其中锡的纯度至少为95％。优选地，纯度约为99％或更高。在一种形式中，利用任何市场可购得的产品形成锡浸槽68，该产品诸如为例如Rohmand Haas ElectronicMaterials的TINPOSITTM LT-34或Enthone的Stannostar GEM PLUSTM。在可以在诸如60-85摄氏度的可变范围内的温度下执行锡浸。应该清楚可以使用其它温度。
图13所示的是完整的微焊盘，其中形成具有高度“L”的锡微焊盘70。该高度典型地在1-3微米的范围内，但可以形成其它尺寸。从处理中的此时，半导体器件52可以被储存，而锡微焊盘70不变成金属间接合焊盘。当随后半导体器件52在锡微焊盘70处接合到另一集成电路的另一微焊盘时，锡将在相对低的接合温度下与铜微焊盘反应以变成固态且可靠的金属间接合。
图14所示的是用于接合半导体器件的微焊盘的另一种形式的截面图。晶片72的一部分被示为具有形成在衬底内的半导体器件74。半导体器件74具有暴露的凹入外部接触件78，外部接触件78连接至在半导体器件74的其它部分处形成的有源电路(未示出)。覆在半导体器件74上面的是钝化材料的绝缘层76，绝缘层76被图案化以暴露接触件78。利用湿法蚀刻工艺使接触件78的暴露部分凹入。绝缘层76的钝化材料可以是各种传统钝化材料中的任一种。
图15所示的是半导体器件74的进一步处理的截面图。形成覆在半导体器件74上面的共形阻挡层80。阻挡层80是用于阻挡锡和铜进入接触件78的钽(Ta)。钽对于这些目的的作用非常好。阻挡层80也可以利用钛(Ti)、氮化钛(TiN)和氮化钽(TaN)或其组合来实施。所有这些材料成功地阻挡了锡进入接触件78和污染接触件78。
图16所示的是半导体器件74的进一步处理的截面图。实施化学机械抛光(CMP)步骤，其中从覆在绝缘层76上面的这些区域去除阻挡层80。CMP处理导致平面的顶表面。在半导体器件74的处理中的此时，阻挡层80仅存在于覆在接触件78上的接触区中。
图17所示的是半导体器件74的进一步处理的截面图。形成覆在半导体器件74上面的共形种子层82。在一种形式中，该种子层是铜，因为期望形成覆在种子层82上面的铜。应该清楚，可以将其他金属用于种子层82，如果期望形成覆在种子层82上面的其他金属类型。形成覆在种子层82上面的图案化的光致抗蚀剂84的层，其中形成围绕接触区并覆在接触件78上面的敞口。然后将半导体器件74放置在电镀槽86中。可以将传统的市场上可购得的溶液用于电镀槽86。当将半导体器件74放置在电镀槽86中时，暴露的种子层82激发铜柱88在光致抗蚀剂84的图案化的层的敞口中形成。铜柱88形成为预定高度。
图18所示的是半导体器件74的进一步处理的截面图。从电镀槽86去除半导体器件74。通过湿法蚀刻或干法蚀刻去除图案化的光致抗蚀剂84的层。通过随后的湿法蚀刻还去除种子层82，以提供图18的结果结构，其中铜柱88暴露并覆在接触区上面以通过阻挡层80和种子层82与接触件78进行电接触。
图19所示的是半导体器件74的进一步处理的截面图。将半导体器件74浸在锡浸槽90中。锡浸槽90用于从铜柱88去除铜，并用基本上纯锡置换铜，其中锡的纯度至少为95％。优选地，纯度约为99％或更高。在一种形式中，利用任何市场可购得的产品形成锡浸槽90，该产品诸如为例如Rohm and Haas Electronic Materials的TINPOSITTMLT-34或Enthone的Stannostar GEM PLUS TM。在可以在诸如60-85摄氏度的可变范围内的温度下执行锡浸。应该清楚可以使用其它温度。
图20所示的是半导体器件74的进一步处理的截面图。在已经由种子层82和铜柱88的组合形成纯锡微焊盘92之后，从图19的锡浸槽90去除半导体器件74。纯锡微焊盘92具有高度“L”，高度“L”足以被接合到例如铜的另一微焊盘(未示出)并被完全消耗以形成金属间接合。因此，“L”的值可以取决于被接合至的另一微焊盘的高度而改变。应该注意，由图19的锡浸槽90发生的去除和用锡置换铜用于去除由纯锡置换的种子层82。纯锡具有至少95％的纯度，优选地纯度为约99％或更高。阻挡层80继续被凹入在半导体器件74的衬底中。
至此应该理解已经提供了一种具有提高的搁置寿命(shelf-life)的微焊盘及其形成方法，因为该微焊盘在成分上是纯锡或基本上纯锡。作为纯锡含量的结果，该微焊盘在室温下不易与其他金属形成金属间接合。这种金属间接合的形成将需要微焊盘的高度增加，由此使得微焊盘刚度更大。这些性质对于堆叠两个集成电路或两个半导体晶片都是显著不利的。可以使用不同的步骤形成纯锡微焊盘。在一种形式中，使用无电浸镀工艺。在另一种形式中，使用电镀槽工艺。在任一种形式中，由于在接合之前不存在铜，因此在半导体器件储存期间以及在温度跳升(ramp-up)期间，基本上去除在微焊盘内形成铜和锡金属间化合物的机会。作为结果，锡微焊盘的总的所需高度可以被最小化，因为在与另一半导体的另一微焊盘进行热压接合时会存在足够的锡。另外，在与另一半导体器件热压接合以形成3D堆叠封装体之前，半导体可以储存相当量的时间。产品接合之前的增加的搁置寿命允许制造商和最终用户具有关于何时将产品封装成多个芯片封装体的附加的灵活性，并允许附加的定制选项。
此处描述的半导体器件的半导体衬底可以是任何半导体材料或材料组合，例如砷化镓、硅锗、绝缘体上硅(SOI)、硅、单晶硅、类似物、以及上述材料的组合。并且，说明书和权利要求中的术语“前”、“后”、“顶”、“底”、“上”、“下”等(如果有的话)，被用于描述目的，而不一定用于描述永久的相对位置。应该理解，所使用的术语在适当的环境下是可互换的，从而使得此处描述的发明的实施例例如能够在不同于此处例示或描述的取向的其它取向下操作。
尽管此处参照具体实施例描述了本发明，但是可以作出各种修改和改变，而不脱离如在下面的权利要求中提出的本发明的范围。例如，虽然利用此处描述的实施例减小了纯锡微焊盘的尺寸，但是这些尺寸可以是各种高度、长度和宽度中的任一个。与纯锡微焊盘连接的半导体器件的接触件可以实施为各种结构形式中的任一种，包括环形。该接触件可以代表电源连接、多位信号总线的一部分或其它信号导体。虽然所示的实施例描述了用于产生纯锡微焊盘的铜柱的形式，但是可以使用用其它金属形成的柱来代替铜柱。
在一种形式中，此处提供了一种方法，其中提供具有外部接触件的第一半导体器件。在该外部接触件上形成铜柱，其中该柱在第一半导体器件的表面上延伸。将铜柱浸在锡溶液中，在该溶液中锡置换柱的至少95％的铜，导致产生具有小于5％的重量百分比的铜的锡微焊盘。在一种形式中，在半导体器件的顶表面上形成具有外部接触件上的敞口的钝化层。在另一种形式中，溶液包含锡盐，并且溶液的温度在60摄氏度至85摄氏度的范围内。在另一种形式中，在形成柱的步骤之前，在外部接触件上形成阻挡层。在又一中形式中，在半导体器件的顶表面上形成具有外部接触件上的敞口的钝化层。在这种形式中，通过在形成柱之前在钝化层和外部接触件上沉积金属层来形成阻挡层。对金属层进行化学机械抛光，以去除钝化层上的金属层并保留敞口中的金属层。在另一种形式中，通过在沉积金属层之前使外部接触件凹入来实施阻挡层的形成。在本实施例中，通过形成钽阻挡层来实施阻挡层的形成。在另一种形式中，通过在外部接触件上无电镀形成阻挡层。在又一形式中，通过将外部接触件浸入包含钴的槽中，利用无电镀来形成阻挡层。在再一形式中，在半导体器件的顶表面上形成具有外部接触件上的敞口的钝化层。在这种形式中，通过在形成柱之前在钝化层和外部接触件上形成金属层来形成阻挡层。使用柱作为掩模来蚀刻金属层以保留由柱覆盖的金属层的一部分作为阻挡层。在另一种形式中，还通过在形成金属层之后且在蚀刻金属层之前形成铜种子层来实施柱的形成。在另一种形式中，通过在超过锡熔点的环境温度下将铜微焊盘压向锡微焊盘，将具有该铜微焊盘的第二半导体器件接合至该半导体器件。在另一种形式中，通过在第一半导体器件的顶表面上形成具有外部接触件上的敞口的光致抗蚀剂层并使用该光致抗蚀剂层作为掩模进行电镀步骤，形成柱。
在另一种形式中，提供了一种方法，其中提供第一半导体器件，第一半导体器件具有从第一半导体器件的表面上的外部接触件延伸的铜柱。通过将该铜柱浸入在60摄氏度到85摄氏度的温度范围内的锡盐溶液的槽中，将该铜柱转换成具有小于5％的重量百分比的铜的锡微焊盘。在又一种形式中，提供第一半导体器件还通过在第一半导体器件上形成具有外部接触件上的敞口的光致抗蚀剂层而形成铜柱来实施。然后使用该光致抗蚀剂作为掩模进行电镀步骤。在又一种形式中，提供具有铜微焊盘的第二半导体器件。在超过锡熔点的环境温度下将铜微焊盘压向锡微焊盘。在另一种形式中，第一半导体器件的铜柱具有与外部接触件相邻的种子层。在又一种形式中，第一半导体器件具有位于种子层与外部接触件之间的阻挡层。在另一种形式中，提供在外部接触件与铜柱之间并与二者直接接触的阻挡层。
在另一种形式中，提供一种提供半导体器件的方法，该半导体器件具有表面和部分地被暴露的接触件。被暴露的接触件的一部分凹入低于该表面。形成从半导体器件的表面上的外部接触件延伸的铜柱。通过将该铜柱浸入在60摄氏度到85摄氏度的范围内的温度下的含锡溶液的槽中，将该铜柱转换成具有至少99％的重量百分比的锡的锡微焊盘。在另一种形式中，在接触件与铜柱之间形成钽阻挡层以防止铜和锡从上方渗透到接触件中。
因而，说明书和附图应该被认为是例示性的而不是限制性，并且意图将所有的这些修改包括在本发明的范围内。此处针对具体实施例描述的任何益处、优点或针对问题的解决方案不意图被解释为任何或全部权利要求的关键、所需或必要特征或元素。
此处使用的术语“耦接”并不意图被限制成直接耦接或机械耦接。
此外，此处使用的术语“一个”被定义为一个或多于一个。此外，权利要求中诸如“至少一个”和“一个或更多个”的引导词的使用不应该被解释为暗示由不定冠词“一个”引导的另一权利要求元素将包含如此引导的权利要求元素的任何特定权利要求限制成仅包含一个所述元素的发明，即使当同一个权利要求包括引导词“至少一个”或“一个或更多个”和诸如“一个”的不定冠词时。对于定冠词的使用同样适用。
除非另有表述，否则诸如“第一”和“第二”的术语用于在这些术语描述的元素之间任意地区分。因此，这些术语不一定意图表示这些元素的时间或其它优先次序。

Claims (20)

1.一种形成半导体器件的微焊盘的方法，包括以下步骤：
提供具有外部接触件的第一半导体器件；
在所述外部接触件上形成铜柱，其中所述铜柱在第一半导体器件的表面上延伸；以及
将所述铜柱浸在锡溶液中，在该溶液中锡置换所述铜柱的至少95％的铜，导致产生具有小于5％的重量百分比的铜的锡微焊盘。
2.如权利要求1所述的方法，还包括以下步骤：在第一半导体器件的顶表面上形成钝化层，所述钝化层具有所述外部接触件上的敞口。
3.如权利要求1所述的方法，其中将所述铜柱浸在锡溶液中的步骤的进一步特征在于：所述溶液包含锡盐溶液，并且所述溶液的温度在60摄氏度至85摄氏度的范围内。
4.如权利要求1所述的方法，还包括以下步骤：在形成柱的步骤之前，在所述外部接触件上形成阻挡层。
5.如权利要求4所述的方法，还包括以下步骤：
在第一半导体器件的顶表面上形成钝化层，所述钝化层具有所述外部接触件上的敞口；
其中形成所述阻挡层的步骤包括：
在形成所述柱之前在所述钝化层和所述外部接触件上沉积金属层；以及
对所述金属层进行化学机械抛光，以去除所述钝化层上的所述金属层并保留所述敞口中的所述金属层。
6.如权利要求5所述的方法，其中形成所述阻挡层的步骤还包括以下步骤：
在沉积所述金属层的步骤之前使所述外部接触件凹入，并且
其中形成所述阻挡层的步骤的进一步特征在于所述阻挡层包含钽。
7.如权利要求4所述的方法，其中形成所述阻挡层的步骤包括在所述外部接触件上进行无电镀。
8.如权利要求7所述的方法，其中形成所述阻挡层的步骤的进一步特征在于无电镀包括将所述外部接触件浸入包含钴的槽中。
9.如权利要求4所述的方法，还包括以下步骤：
在第一半导体器件的顶表面上形成钝化层，所述钝化层具有所述外部接触件上的敞口；
其中，形成所述阻挡层的步骤包括：
在形成所述柱的步骤之前在所述钝化层和所述外部接触件上形成金属层；以及
使用所述柱作为掩模来蚀刻所述金属层以保留由所述柱覆盖的所述金属层的一部分作为所述阻挡层。
10.如权利要求9所述的方法，其中形成所述柱的步骤的进一步特征在于：在形成所述金属层的步骤之后且在蚀刻所述金属层的步骤之前，形成铜种子层。
11.如权利要求1所述的方法，还包括以下步骤：
提供具有铜微焊盘的第二半导体器件；以及
在超过锡熔点的环境温度下将所述铜微焊盘压向所述锡微焊盘。
12.如权利要求11所述的方法，其中形成所述柱的步骤的进一步特征在于：
在第一半导体器件上形成光致抗蚀剂层，所述光致抗蚀剂层具有所述外部接触件上的敞口；以及
使用所述光致抗蚀剂层作为掩模进行电镀步骤。
13.一种形成半导体器件的微焊盘的方法，包括以下步骤：
提供第一半导体器件，第一半导体器件具有在第一半导体器件的表面上的从外部接触件延伸的铜柱；以及
通过将所述铜柱浸入在60摄氏度到85摄氏度的温度范围内的锡盐溶液的槽中，将所述铜柱转换成具有小于5％的重量百分比的铜的锡微焊盘。
14.如权利要求13所述的方法，其中提供第一半导体器件的步骤的进一步特征在于通过以下步骤形成所述铜柱：
在第一半导体器件上形成光致抗蚀剂层，所述光致抗蚀剂层具有所述外部接触件上的敞口；以及
使用所述光致抗蚀剂作为掩模进行电镀步骤。
15.如权利要求13所述的方法，还包括以下步骤：
提供具有铜微焊盘的第二半导体器件；以及
在超过锡熔点的环境温度下将所述铜微焊盘压向所述锡微焊盘。
16.如权利要求13所述的方法，其中提供第一半导体器件的步骤的进一步特征在于：第一半导体器件的所述铜柱具有与所述外部接触件相邻的种子层。
17.如权利要求16所述的方法，其中提供第一半导体器件的步骤的进一步特征在于：第一半导体器件具有位于所述种子层与所述外部接触件之间的阻挡层。
18.如权利要求16所述的方法，其中提供第一半导体器件的步骤的进一步特征在于：在所述外部接触件与所述铜柱之间并与二者直接接触的阻挡层。
19.一种形成半导体器件的微焊盘的方法，包括以下步骤：
提供半导体器件，该半导体器件具有表面和部分地被暴露的接触件，其中被暴露的所述接触件的一部分凹入低于所述表面；
形成在所述半导体器件的表面上的从外部接触件延伸的铜柱；以及
通过将所述铜柱浸入在60摄氏度到85摄氏度的范围内的温度下的含锡溶液的槽中，将所述铜柱转换成具有至少99％的重量百分比的锡的锡微焊盘。
20.如权利要求19所述的方法，还包括以下步骤：
在所述接触件与所述铜柱之间形成钽阻挡层以防止铜和锡从上方渗透到所述接触件中。
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US7807572B2 (en) 2010-10-05
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