TWI442476B - 半導體之微襯墊形成 - Google Patents

半導體之微襯墊形成 Download PDF

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Publication number
TWI442476B
TWI442476B TW097151677A TW97151677A TWI442476B TW I442476 B TWI442476 B TW I442476B TW 097151677 A TW097151677 A TW 097151677A TW 97151677 A TW97151677 A TW 97151677A TW I442476 B TWI442476 B TW I442476B
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Taiwan
Prior art keywords
copper
tin
semiconductor device
micropad
pillar
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TW097151677A
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English (en)
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TW200939348A (en
Inventor
Varughese Mathew
Eddie Acosta
Ritwik Chatterjee
Sam S Garcia
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Freescale Semiconductor Inc
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Publication of TW200939348A publication Critical patent/TW200939348A/zh
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Publication of TWI442476B publication Critical patent/TWI442476B/zh

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Description

半導體之微襯墊形成
本發明一般係關於半導體，且更明確而言，係關於外部電連接至半導體。
此申請案已於2008年1月4號在美國作為專利申請案第11/969,368號申請。此申請案係關於2006年10月25日申請之我方共同待審美國專利申請案第11/552,821號，其標題為"A Micropad For Bonding And A Method Therefor(用於接合之微襯墊及其方法)"，並讓渡給其受讓人。
藉由在三維(3D)堆疊中堆疊兩個或更多積體電路，積體電路係愈多地彼此連接。例如，此技術已用於藉由堆疊兩個記憶體積體電路來倍增記憶體之數量。一替代形式係使用一半導體晶圓來堆疊一積體電路。該等堆疊積體電路透過晶片接合來進行彼此電接觸。該晶片接合利用在一積體電路上的一接合墊，其與其他積體電路之另一接合墊接合。該些接合墊通常稱為"微襯墊"。來自兩個不同晶粒或晶圓之微襯墊的熱壓縮接合提供堆疊晶粒之機械及電性層間連接兩者。一習知接合程序使用在一第一積體電路之一接合墊處的一銅微襯墊以及在一第二積體電路之一接合墊處的銅及錫。將該兩個接合墊對齊並與將該第一積體電路之銅接合墊接合至該第二積體電路之錫接合墊來接合在一起。但是，該第二積體電路之接合墊之銅與錫的相互擴散在較低溫度(包括室溫)下發生以形成金屬間化合物，例如Cu3 Sn及Cu6 Sn5 。厚的金屬間化合物係脆化的且造成與接合墊相關聯的可靠性問題。例如，由一金屬間化合物製成的一剛性接合墊易於剪力及應力斷裂。當形成一明顯數量的金屬間化合物時，必須添加額外的錫以確保材料保持可接合。額外的錫增加非所需的厚度。並且，此類金屬間化合物係穩定直至極高溫度，諸如攝氏600度，並因而變得不可接合。此類高溫係過大以至於無法用於一接合材料，因為當遭受此高溫時，一完整積體電路之其他部分會劣化或失效。
圖1中解說依據本發明之一形式所處理的一半導體晶圓10之一部分之一斷面圖。解說一半導體裝置12，其中該半導體裝置12係半導體晶圓10上的一晶粒之一部分。具有電晶體及許多電接點之一基板係在半導體裝置12內。為方便解說，一單一電接點係以半導體裝置12之基板內的一接點14的形式來加以解說。接點14係半導體裝置12之一外部接點並自半導體裝置12之一初始曝露表面向於半導體裝置12之低層級處製造的主動電路(未顯示)提供電接觸。一鈍化層16係採用留下所曝露的接點14之一明顯部分的方式來在半導體裝置12之上圖案化。鈍化層16係一電絕緣材料。在一形式中，鈍化層16係一絕緣材料層。在其他形式中，鈍化層16可採用多個絕緣材料層來實施。應瞭解可使用鈍化材料，諸如氧氮化矽、氮化矽、TEOS膜、電漿增強氮化物及其組合。覆蓋該鈍化層16的係一保形阻障層18。阻障層18發揮作用以促進黏著並起作用為對銅及錫的一阻障。可使用各種阻障材料，包括鈦鎢(TiW)、氮化鈦(TiN)或鎢(W)。可實施其他阻障材料。阻障層18係直接形成於該接點14上。
圖2中解說半導體晶圓10之進一步處理。一晶種層20係覆蓋阻障層18而形成並係保形的。在一形式中，晶種層20係銅。可使用其他金屬。銅係在此具體實施例中用於打算在接點14之上逐漸形成覆蓋銅中輔助作為一晶種。在晶種層20形成之後形成一圖案化光阻層22，其中接點14之上的區域在該圖案中敞開用於曝露於後續處理下。傳統光阻材料係用作光阻層22。
圖3中解說半導體晶圓10之進一步處理，其中半導體晶圓10係曝露於一銅電鍍浴26中。所使用的電鍍溶液包含銅。在銅晶種層20的輔助下，形成一銅柱塊24，其覆蓋接點14及阻障層18。阻障層18防止銅自晶種層20遷移至接點14。半導體晶圓10係曝露在銅電鍍浴26下達一充足數量的時間並在此處理期間傳遞充足的電荷以形成銅柱塊24至覆蓋接點14的一所需高度。
圖4中解說半導體晶圓10之進一步處理，其中半導體晶圓10係自銅電鍍浴26移除。圖案化光阻層22亦藉由執行一傳統濕式蝕刻來移除。因此，在處理中的此刻已形成覆蓋接點14並延伸高過該晶種層之一上表面之一數量的一銅柱塊24，該數量量取決於處理條件，諸如半導體晶圓10在銅電鍍浴26中的時間數量以及在銅電鍍步驟期間所傳遞的電荷數量。
圖5中解說半導體晶圓10之進一步處理，其中晶種層20及阻障層18之曝露部分係藉由一傳統濕式蝕刻來加以移除。在該濕式蝕刻之後，僅保留在銅柱塊24下面的晶種層20及阻障層18之該等部分。
圖6中解說半導體晶圓10之進一步處理，其中半導體晶圓10係放置於一錫浸沒電鍍浴28中達一預定時間數量。錫浸沒電鍍浴28發揮作用以自銅柱塊24及晶種層20兩者移除銅並以純錫(Sn)取代銅。錫取代銅柱塊24中至少九十五百分比(95%)的銅以導致一具有小於五重量百分比(5%)銅的錫微襯墊。隨著銅離子進入至電鍍浴28中的溶液中，將銅自銅柱塊24移除。該反應係一化學取代反應，其一般而言可表示為：
2Cu+Sn2+ →2 Cu+ +Sn
材料轉移所需的時間數量取決於各種因素，包括時間及溫度。在一形式中，錫浸沒電鍍浴28係包含錫鹽及其他成分(諸如錯合劑及表面活性劑)的一溶液並維持一溫度下，該溫度係在等於或大於攝氏60度且高達攝氏85度的一溫度範圍內。
圖7中解說半導體晶圓10之進一步處理，其中半導體晶圓10係自錫浸鍍浴28移除。存在一所得純錫微襯墊30，其中純錫微襯墊30具有一高度"L"，其係在1微米(0.001mm)至5微米(0.005mm)之一範圍內。高度"L"係很大程度上由在圖3中形成柱塊24時該柱塊之銅厚度之高度來決定。
圖8中解說半導體晶圓10之進一步處理，其中一第二半導體晶圓32係連接以形成三維(3D)結構。第二半導體晶圓32具有一半導體裝置34，其具有一接點38，該接點係連接至半導體裝置34內的主動電路(未顯示)。直接連接至接點38的係一阻障層43，其類似於半導體裝置12之阻障層18。連接至該阻障層43的係一銅微襯墊36。在其中純錫微襯墊30具有在實質上1微米至3微米之一範圍內之一高度的一實施方案中，取決於微襯墊30之值，銅微襯墊36之高度係在3微米至10微米的一範圍內。在該範圍內，銅微襯墊36係微襯墊30之高度的至少兩倍且可以係三倍或更多倍高。與接點38相鄰之銅微襯墊36之基底係由一絕緣層41所圍繞。在一形式中，絕緣層41係一鈍化材料層，例如氮化物或TEOS。一壓縮力40係用於實體接合半導體裝置12至半導體裝置34。當在一足夠高的溫度下施加壓縮力40以軟化錫微襯墊30時，形成電連接接點14至接點38之一接合。在一形式中，在超過錫熔點(攝氏232度)的一周圍溫度下抵著在該純錫微襯墊30按壓銅微襯墊36。
圖9中解說半導體晶圓10及半導體晶圓32之進一步處理。形成一銅/錫金屬間微接合42，其中微襯墊30之錫係由微襯墊36之銅來消耗以在半導體裝置12與半導體裝置34之間形成一堅固接合。銅微襯墊36之一部分保留銅且不會與微襯墊30之錫反應。因此已提供一種在兩個半導體裝置之間的改良半導體接合墊。
圖10中解說為一晶圓50之一半導體裝置52形成一微襯墊之另一具體實施例，其中該微襯墊容易地與另一半導體裝置之另一微襯墊接合。在所解說形式中，半導體裝置52具有一外部接點54，其係連接至半導體裝置52之一基板內的主動電路(未顯示)。覆蓋該半導體裝置52的係一圖案化鈍化層56。在另一形式中，可採用多個層來實施圖案化鈍化層56。在一形式中，圖案化鈍化層56係一絕緣材料，諸如氮氧化矽、氮化矽、TEOS膜、電漿增強氮化物或其組合。覆蓋圖案化鈍化層56的係一圖案化光阻層58。圖案化光阻層58具有曝露接點54的一開口。在該開口內及在接點54之上形成一選擇性沈積阻障層62。阻障層62係與接點54直接接觸。可使用各種選擇性沈積阻障材料，諸如鈷鎢硼(CoWB)、鈷鎢磷(CoWP)、鈷鎢磷硼(CoWPB)、鈷鉬硼(CoMoB)、鈷鉬磷(CoMoP)、鎳鎢磷(NiWP)或其組合。阻障層62發揮作用以阻礙銅及錫接觸接點54。在此形式中，半導體裝置52係放置在一無電極電鍍浴60中。無電極電鍍浴60係一市售無電極電鍍溶液。
圖11中解說由於半導體裝置52保留在無電極銅電鍍浴64中達一明顯數量的時間以在阻障層62上沈積銅而形成一銅柱塊66。沈積銅柱塊66所需的時間數量取決於許多變數，包括溫度及無電極銅電鍍浴64中所用的銅溶液。該時間數量亦係藉由該銅柱塊66之一所需高度來加以決定。在一形式中，形成銅柱塊66至一高度，其隨後決定最終微襯墊結構之高度。因此此高度可變化。
圖12中解說半導體裝置52之進一步處理，其中該半導體裝置係自無電極銅電鍍浴64移除。隨後藉由一濕式蝕刻或一乾式蝕刻來移除圖案化光阻58。移除圖案化光阻58後，銅柱塊66自在接點54之上的阻障層62延伸。接著將半導體裝置52放置在一錫浸沒浴68中。錫浸沒浴68發揮作用以自銅柱塊66移除銅並以實質上至少九十五百分比的純錫來取代銅。較佳的係該純度約為九十九百分比或更大。在一形式中，藉由使用若干市售產品(例如，Rohm and Haas Electronic Materials的TINPOSITTM LT-34或Enthone的Stannostar GEM PLUSTM )之任一者來形成錫浸沒浴68。錫浸沒係在一溫度下執行，該溫度可能在一可變範圍內，諸如攝氏六十至八十五度。應明白可使用其他溫度。
圖13中解說一完成微襯墊，其中已形成具有一高度"L"之一錫微襯墊70。該高度一般係在1至3微米之一範圍內，但可形成其他尺寸。在該處理中的此刻，可儲存半導體裝置52而錫微襯墊70不會變成一金屬間接合墊。當半導體裝置52係在錫微襯墊70處隨後接合至另一積體電路之另一微襯墊時，該錫將在一相對較低接合溫度下與一銅微襯墊反應以變成一堅固且可靠的金屬間接合。
圖14中解說用於接合一半導體裝置之一微襯墊之另一形式之一斷面圖。解說一晶圓72之一部分，其具有形成於一基板內的一半導體裝置74。半導體裝置74具有一曝露凹陷外部接點78，其連接至已形成於半導體裝置74之其他部分處的主動電路(未顯示)。覆蓋半導體裝置74的係一鈍化材料絕緣層76，其係圖案化以曝露接點78。藉由使用一濕式蝕刻程序來凹陷接點78之該曝露部分。絕緣層76之鈍化材料可以係各種傳統鈍化材料之任一者。
圖15中解說半導體裝置74之進一步處理之一斷面圖。覆蓋半導體裝置74形成一保形阻障層80。阻障層80係鉭(Ta)，其用於阻止錫及銅進入接點78內。針對此等目的，鉭發揮極好地作用。還可藉由使用鈦(Ti)、氮化鈦(TiN)及氮化鉭(TaN)或其組合來實施阻障層80。所有該些材料均成功地阻止錫進入接點78內並污染接點78。
圖16中解說半導體裝置74之進一步處理之一斷面圖。實施一化學機械拋光(CMP)步驟，其中阻障層80係自覆蓋該絕緣層76之該些區域移除。一平坦頂部表面自該CMP處理產生。在半導體裝置74之處理中的此刻，阻障層80係僅處於覆蓋接點78之接觸區域內。
圖17中解說半導體裝置74之進一步處理之一斷面圖。覆蓋該半導體裝置74形成一保形晶種層82。在一形式中，該晶種層係銅，因為需要覆蓋晶種層82形成銅。應明白若需要覆蓋晶種層82形成其他金屬類型，則其他金屬也可用於晶種層82。覆蓋晶種層82形成一圖案化光阻層84，其中一開口係在該接觸區域周圍並覆蓋接點78而形成。接著將半導體裝置74放置在一電鍍浴86中。一傳統市售溶液可用於電鍍浴86。當將半導體裝置74放置於電鍍浴86中時，所曝露晶種層82促使在圖案化光阻層84之開口中形成銅柱塊88。銅柱塊88係形成至一預定高度。
圖18中解說半導體裝置74之進一步處理之一斷面圖。半導體裝置74係自該電鍍浴86移除。藉由一濕式蝕刻或一乾式蝕來移除圖案化光阻層84。還藉由一後續濕式蝕刻來移除晶種層82以提供圖18之所得結構，其中銅柱塊88係曝露且覆蓋該接觸區域以經由阻障層80及晶種層82與接點78進行電接觸。
圖19中解說半導體裝置74之進一步處理之一斷面圖。半導體裝置74係浸沒於一錫浸沒浴90中。錫浸沒浴90發揮作用以自銅柱塊88移除銅並以實質上至少九十五百分比的純錫取代銅。較佳的係該純度約為九十九百分比或更大。在一形式中，藉由使用市售產品(例如，Rohm and Haas Electronic Materials的TINPOSITTM LT-34或Enthone的Stannostar GEM PLUSTM )之任一者來形成錫浸沒浴90。該錫浸沒係在一溫度下執行，該溫度可能在一可變範圍內，諸如攝氏六十至八十五度。應明白可使用其他溫度。
圖20中解說半導體裝置74之進一步處理之一斷面圖。在已自晶種層82及銅柱塊88之組合形成一純錫微襯墊92之後，將半導體裝置74自圖19之錫浸沒浴90移除。純錫微襯墊92具有一高度"L"，其係足以接合至另一(例如)銅微襯墊(未顯示)，並完全消耗以形成一金屬間接合。因此，"L"值可取決於正受接合之其他微襯墊之高度而變化。應注意在圖19之錫浸沒浴90發生之銅移除及以錫取代發揮作用以移除由純錫取代之晶種層82。該純錫具有至少95%之一純度，且該純度較佳的係約99%或更大。阻障層80繼續在該半導體裝置74之基板中凹陷。
至此應瞭解已提供一種具有改進保存期限之微襯墊及其形成方法，此係因為該微襯墊在組成上為純錫或實質為純錫。由於該純錫含量，該微襯墊不易在室溫下與另一金屬形成金屬間接合。此一金屬間接合之形成將要求該微襯墊高度增加，由此使得該微襯墊更具剛性。此些特徵兩者係顯然不利於堆疊兩個積體電路或兩個半導體晶圓。可使用不同步驟來形成該純錫微襯墊。在一形式中，使用一無電極電鍍程序。在另一形式中，使用一電鍍浴程序。在任一形式中，由於在接合之前不存在銅，故在該半導體裝置之儲存期間以及在一溫度爬升期間實質上去除在微襯墊內形成銅及錫金屬間化合物的機會。結果，在與另一半導體之另一微襯墊進行一熱壓縮接合時，由於存在足夠的錫，故可最小化該錫微襯墊之總所需高度。此外，在與另一半導體裝置熱壓縮接合以形成一3D堆疊封裝之前，該半導體可儲存達一明顯數量的時間。該產品在接合之前的增加保存期限准許一製造者及一終端使用者兩者在何時將產品封裝成多個晶片封裝方面具有額外靈活性，且准許額外訂制選項。
本文中所說明之半導體裝置之半導體基板可以係任何半導體材料或材料組合，諸如砷化鎵、鍺化矽、絕緣物上矽(SOI)、矽、單晶矽等及以上之組合。而且，在本說明書及申請專利範圍中"前"、"後"、"頂部"、"底部"、"之上"、"底下"等術語(若存在的話)係用於說明目的且不一定用於說明永久性相對位置。應明白，在適當情形下，可互換如此使用的術語，使得本文中所說明的本發明之具體實施例(例如)能夠以本文中所解說或另外說明之該等方位以外的方位來操作。
儘管本文中參考特定具體實施例來說明本發明，但是可進行各種修改及變更而不脫離以下專利申請範圍所提出之本發明之範疇。例如，雖然係藉由使用本文中所說明之具體實施例來減低純錫微襯墊之尺寸，但是該些尺寸可以係任何各種高度、長度及寬度。該純錫微襯墊所連接之半導體裝置之接點可實施成任何各種結構形式，包括圓形。該接點可代表電源供應連接、一多位元信號匯流排之一部分或其他信號導體。雖然所解說之具體實施例說明用於建立該等純錫微襯墊之銅柱塊的形成，但是可使用其他金屬替代該銅柱塊。
在一形式中，本文中提供一種方法，其中提供具有一外部接點的一第一半導體裝置。在該外部接點之上形成一銅柱塊，其中該柱塊延伸高過該第一半導體裝置之一表面。該銅柱塊係浸沒於一錫溶液中，其中該錫取代該柱塊之至少95%的銅，導致具有小於5重量%銅的一錫微襯墊。在一形式中，在於外部接點上具有一開口的該半導體裝置之一頂部表面之上形成一鈍化層。在另一形式中，該溶液包含一錫鹽，且該溶液之一溫度係在攝氏60度至攝氏85度的一範圍內。在另一形式中，在形成一柱塊之步驟之前，在該外部接點之上形成一阻障層。在又另一形式中，在該外部接點之上具有一開口的該半導體裝置之一頂部表面之上形成一鈍化層。在此形式中，在形成該柱塊之前，藉由在該鈍化層及該外部接點之上沈積一金屬層來形成該阻障層。執行在該金屬層上的化學機械拋光使得在該鈍化層之上移除該金屬層並保持在該開口中。在另一形式中，在沈積該金屬層之前，藉由凹陷該外部接點來實施形成該阻障層。在此具體實施例中，藉由形成一鉭阻障層來實施形成該阻障層。在另一形式中，藉由在該外部接點上的無電極電鍍來形成該阻障層。在又另一形式中，藉由將該外部接點浸沒於一包含鈷的浴中由無電極電鍍來形成該阻障層。在又另一形式中，在該外部接點上具有一開口的該半導體裝置之一頂部表面之上形成一鈍化層。在此形式中，在形成該柱塊之前，藉由在該鈍化層及該外部接點之上形成一金屬層來形成該阻障層。將該柱塊作為一遮罩來蝕刻該金屬層以留下由作為該阻障層的該柱塊覆蓋的該金屬層之一部分。在又另一形式中，在形成該金屬層之後並在蝕刻該金屬層之前藉由形成一銅晶種層來進一步實施形成該柱塊。在又另一形式中，具有一銅微襯墊的一第二半導體裝置係藉由在超過錫熔點的一周圍溫度下抵著該錫微襯墊上按壓該銅微襯墊來接合至該半導體裝置。在另一形式中，藉由在該外部接點之上具有一開口的該第一半導體裝置之上形成一光阻層並使用該光阻層作為一遮罩執行一電鍍步驟來形成該柱塊。
在又另一形式中，提供一種方法，其中提供一第一半導體裝置，其具有一銅柱塊，該銅柱塊自該第一半導體裝置之一表面上方之上之一外部接點延伸。藉由將該銅柱塊浸沒於處於自攝氏60度至攝氏85度之一溫度範圍內的一錫鹽溶液浴中，將該銅柱塊轉換成小於5重量百分比銅的一錫微襯墊。在又另一形式中，藉由在該外部接點之上具有一開口的該第一半導體裝置之上形成一光阻層形成該銅柱塊來進一步實施提供該第一半導體裝置。接著將該光阻層作為一遮罩來執行一電鍍步驟。在又另一形式中，提供具有一銅微襯墊之一第二半導體裝置。在超過錫熔點之一周圍溫度下抵著該錫微襯墊按壓該銅微襯墊。在另一形式中，該第一半導體裝置之銅柱塊具有鄰近於該外部接點的一晶種層。在又另一形式中，該第一半導體裝置在該晶種層與該外部接點之間具有一阻障層。在另一形式中，提供一阻障層於該外部接點與該銅柱塊之間並與其直接接觸。
在另一形式中，提供一種提供具有一表面及一部分曝露接觸之一半導體裝置之方法。所曝露接點之一部分係凹陷低於該表面。形成一銅柱塊，其自一外部接點延伸高過該半導體裝置之一表面。藉由將該銅柱塊浸沒於處於攝氏60度至攝氏85度之一溫度範圍中的一含錫溶液浴中，將該銅柱塊轉換成至少九十九重量百分比錫的一錫微襯墊。在另一形式中，在該接點及該銅柱塊之間形成一鉭阻障層以防止銅及錫自之上滲入至該接點內。
據此，應在一解說性而非一限制性意義上考量本說明書及圖式，並且期望所有此類修改均涵蓋在本發明之範疇內。不期望將本文中關於特定具體實施例所說明之任何好處、優點或問題解決方案視為任一或所有請求項之一關鍵、必要或本質特徵或要素。
本文中所使用的術語"耦合"並不意在侷限於一直接耦合或一機械耦合。
而且，本文中所使用的術語"一"或"一個"係定義為一或一個以上。並且，在申請專利範圍中使用諸如"至少一"及"一或多個"之介紹性短語不應視為暗示著藉由不定冠詞"一"或"一個"介紹另一申請項元件會將包含此介紹申請項元件之任何特定申請項限制於僅包含一此類元件之發明，即使相同的申請專利範圍包括介紹性短語"一或多個"或"至少一"及諸如"一"或"一個"之不定冠詞。此亦適用於定冠詞之用法。
除非另有聲明，諸如"第一"及"第二"之術語係用來任意區分此類術語所說明的元件。因而，該些術語不一定意在指示此類元件之時間或其他優先性。
10．．．半導體晶圓
12．．．第一半導體裝置
14．．．外部接點
16．．．鈍化層
18．．．阻障層
20．．．銅柱塊/銅晶種層
22．．．光阻層
24．．．銅柱塊
26．．．銅電鍍浴
28．．．錫/錫浸鍍浴
30．．．微襯墊/錫微襯墊
32．．．第二半導體晶圓
34．．．半導體裝置
36．．．銅微襯墊
38．．．接點
40．．．壓縮力
41．．．絕緣層
42．．．微襯墊/銅/錫金屬間微接合
43．．．阻障層
50．．．晶圓
52．．．第一半導體裝置
54．．．外部接點
56．．．鈍化層
58．．．光阻層
60．．．無電極電鍍浴
62．．．阻障層
64．．．無電極銅電鍍浴
66．．．銅柱塊
68．．．錫浸沒浴
70．．．微襯墊/錫微襯墊
72．．．晶圓
74．．．第一半導體裝置
76．．．鈍化材料絕緣層
78．．．外部接點
80．．．阻障層
82．．．銅柱塊/晶種層
84．．．光阻層
86．．．電鍍浴
88．．．銅柱塊
90．．．錫浸沒浴
92．．．純錫微襯墊
L．．．高度
本發明已藉由範例予以解說且不受附圖限制，其中相同參考符號指示相似元件。在該等圖式中的元件係出於簡化及清楚而解說且不一定依比例繪製。
圖1至9以斷面圖形式解說形成用於連接至一第二半導體裝置的一第一半導體裝置之一微襯墊結構之一形式；
圖10至13以斷面圖形式解說形成用於連接至一第二半導體裝置的一第一半導體裝置之一微襯墊結構之另一形式；以及
圖14至20以斷面圖形式解說形成用於連接至一第二半導體裝置的一第一半導體裝置之一微襯墊結構之又另一形式。
習知此項技術人士應瞭解，圖式中的該等元件係為簡化及清楚而解說且不一定依比例繪製。例如，為了有助於增進對本發明具體實施例的理解，圖式中一些元件的尺寸可相對於其他元件來加以放大。
10．．．半導體晶圓
12．．．第一半導體裝置
14．．．外部接點
16．．．鈍化層
18．．．阻障層
20．．．銅柱塊/銅晶種層
24．．．銅柱塊
28．．．錫/錫浸鍍浴

Claims (5)

  1. 一種方法，其包含：提供具有一外部接點的一第一半導體裝置；在該外部接點之上形成一銅柱塊，其中該柱塊延伸高過該第一半導體裝置之一表面；以及將該銅柱塊浸沒於一錫溶液中，其中該錫取代該柱塊至少百分之九十五的銅，導致形成具有銅的重量百分比少於百分之五的一錫微襯墊。
  2. 一種方法，其包含：提供具有一外部接點的一第一半導體裝置；在該外部接點之上形成一銅柱塊，其中該柱塊延伸高過該第一半導體裝置之一表面；將該銅柱塊浸沒於一錫溶液中，其中該錫取代該柱塊至少百分之九十五的銅，導致形成具有銅的重量百分比少於百分之五的一錫微襯墊；以及在該外部接點之上具有一開口的該第一半導體裝置之一頂部表面之上形成一鈍化層。
  3. 一種方法，其包含：提供具有一外部接點的一第一半導體裝置；在該外部接點之上形成一銅柱塊，其中該柱塊延伸高過該第一半導體裝置之一表面；將該銅柱塊浸沒於一錫溶液中，其中該錫取代該柱塊之至少百分之九十五的銅，導致形成具有銅的重量百分比少於百分之五的一錫微襯墊；以及 在形成一柱塊之該步驟之前，在該外部接點之上形成一障礙層。
  4. 一種方法，其包含：提供一第一半導體裝置，其具有從一外部接點延伸至該第一半導體裝置的一表面上方之一銅柱塊；以及藉由將該銅柱塊浸沒於溫度範圍在攝氏60度至攝氏85度的一錫鹽溶液之浴池中，使該銅柱塊轉換成具有銅的重量百分比少於百分之五的一錫微襯墊。
  5. 一種方法，其包含：提供具有一表面和一部分暴露的接點之一半導體裝置，其中該暴露的接點之一部分是凹下而低於該表面；形成從一外部接點延伸至該半導體裝置的一表面上方之一銅柱塊；以及藉由將該銅柱塊浸沒於溫度範圍在攝氏60度至攝氏85度的一含錫溶液浴池，使該銅柱塊轉換成錫的重量百分比至少百分之九十九的一錫微襯墊。
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US20090176366A1 (en) 2009-07-09
US7807572B2 (en) 2010-10-05
JP2011508983A (ja) 2011-03-17
JP5248627B2 (ja) 2013-07-31
WO2009088659A2 (en) 2009-07-16
CN101911292A (zh) 2010-12-08
WO2009088659A3 (en) 2009-09-03
TW200939348A (en) 2009-09-16

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