CN109411434B - 扇出型半导体封装件 - Google Patents
扇出型半导体封装件 Download PDFInfo
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- CN109411434B CN109411434B CN201810933219.5A CN201810933219A CN109411434B CN 109411434 B CN109411434 B CN 109411434B CN 201810933219 A CN201810933219 A CN 201810933219A CN 109411434 B CN109411434 B CN 109411434B
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Abstract
本公开提供一种扇出型半导体封装件,所述扇出型半导体封装件包括:芯构件,包括多个绝缘层和多个布线层并且具有贯穿所述多个绝缘层的一部分的盲腔;半导体芯片,设置在所述盲腔中;包封剂,包封所述芯构件的至少部分和所述半导体芯片的有效表面的至少部分并且填充所述盲腔的至少部分;及连接构件,设置在所述芯构件和所述半导体芯片的所述有效表面上并且包括重新分布层,所述重新分布层连接到所述连接焊盘。所述多个布线层包括天线图案和接地图案,所述天线图案和所述接地图案设置在不同的水平面上,并且所述天线图案通过所述重新分布层连接到所述连接焊盘。
Description
本申请要求于2017年8月18日和于2017年12月6日提交到韩国知识产权局的第10-2017-0104569号和第10-2017-0166562号韩国专利申请的优先权的权益,所述韩国专利申请的公开内容通过引用被全部包含于此。
技术领域
本公开涉及一种形成有天线图案和接地图案的扇出型半导体封装件。
背景技术
使用10GHz或更高的毫米波的应用已经被广泛用于检测运动以增加用户界面(I/F)便利性的运动传感器产品、用于在预定空间中确认入侵者的安全性的动作监测传感器产品、用于汽车的近场检测和远场检测的24GHz和77GHz的雷达系统等以及用于移动通信或60GHz通信的第五代(5G)通信。在如上所述使用毫米波的产品的情况下,当信号从射频集成电路(RFIC)传输到天线或者从天线传输到RFIC时,信号应当被传输为使得尽量不产生信号损耗。通常,为此目的,RFIC和天线通过同轴线缆彼此连接以使信号衰减最小化,这在空间和成本方面是低效的。
近来,在60GHz的通信系统中,已经开始使用如下方式:使用诸如低温共烧陶瓷(LTCC)等的材料设计60GHz天线,然后将60GHz天线附着到RFIC上以显著地减小组件之间的距离。另外,在用于汽车的雷达系统中,已经使用如下方式:将RFIC安装在主印刷电路板(PCB)上,在主PCB上形成作为图案的天线并且将作为图案的天线连接到主PCB,或者将单独的天线模块安装到主PCB。然而,以这种方式,也难以充分地防止组件之间的线路到线路的损耗的产生。
近来,根据封装技术的发展,已经开发了在RFIC封装件中形成天线的方法,并且在一些情况下,已经使用在RFIC封装件的重新分布层(RDL)上形成天线图案的方式。然而,以这种方式,在确保天线的辐射性能方面也存在多种设计局限性,或者也存在将发生性能错误的可能性。因此,已经需要能够在设计时具有灵活的自由度并且显著地减小设计误差的稳定的RFIC和天线集成封装设计技术。
发明内容
本公开的一方面可提供一种扇出型半导体封装件,在该扇出型半导体封装件中,可通过显著地减小半导体芯片和天线图案之间的距离防止信号传输的损耗,可在单个封装件中确保稳定的天线性能,可减小封装件的整体尺寸,并且可简化工艺。
根据本公开的一方面,可提供一种扇出型半导体封装件,在该扇出型半导体封装件中,半导体芯片和天线使用盲腔集成在单个封装件中。
根据本公开的一方面,一种扇出型半导体封装件可包括:芯构件,包括多个绝缘层和多个布线层并且具有贯穿所述多个绝缘层的一部分的盲腔;半导体芯片,设置在所述盲腔中并且具有有效表面和与所述有效表面背对的无效表面,所述有效表面上设置有连接焊盘;包封剂,包封所述芯构件的至少部分和所述半导体芯片的所述有效表面的至少部分并且填充所述盲腔的至少部分;及连接构件,设置在所述芯构件和所述半导体芯片的所述有效表面上并且包括重新分布层,所述重新分布层连接到所述连接焊盘,其中,所述多个布线层包括天线图案和接地图案,所述天线图案和所述接地图案设置在不同的水平面上,并且所述天线图案通过所述重新分布层连接到所述连接焊盘。所述多个布线层还可包括屏障图案,所述屏障图案的一部分可通过所述盲腔暴露,并且所述半导体芯片的所述无效表面可附着到所述屏障图案的被暴露的所述一部分。
附图说明
通过结合附图进行的以下详细描述,本公开的以上和其他方面、特征及优点将被更加清楚地理解,在附图中:
图1是示出电子装置系统的示例的示意性框图;
图2是示出电子装置的示例的示意性透视图;
图3A和图3B是示出扇入型半导体封装件在被封装之前和封装之后的状态的示意性截面图;
图4是示出扇入型半导体封装件的封装工艺的示意性截面图;
图5是示出扇入型半导体封装件安装在球栅阵列(BGA)基板上并且最终安装在电子装置的主板上的情况的示意性截面图;
图6是示出扇入型半导体封装件嵌入在BGA基板中并且最终安装在电子装置的主板上的情况的示意性截面图;
图7是示出扇出型半导体封装件的示意性截面图;
图8是示出扇出型半导体封装件安装在电子装置的主板上的情况的示意性截面图;
图9是示出扇出型半导体封装件的示例的示意性截面图;
图10是示出当从上方观察时图9的扇出型半导体封装件的示意性平面图;
图11A和图11B是示出当从上方观察时图9的扇出型半导体封装件的各种示例的示意性平面图;
图12是示出用于制造图9的扇出型半导体封装件的面板的示例的示意图;
图13A和图13B是示出制造图9的扇出型半导体封装件的工艺的示例的示意图;
图14是示出扇出型半导体封装件的另一示例的示意性截面图;
图15是示出扇出型半导体封装件的另一示例的示意性截面图;
图16是示出扇出型半导体封装件的另一示例的示意性截面图;
图17是示出根据现有技术的扇出型半导体封装件应用到主板的示例的示意性截面图;
图18是示出根据现有技术的堆叠型天线集成模块的示例的示意性截面图;及
图19是示出根据现有技术的堆叠型天线集成模块的另一示例的示意性截面图。
具体实施方式
在下文中,将参照附图描述本公开中的示例性实施例。在附图中,为清楚起见,可夸大或者缩小组件的形状、尺寸等。
这里使用的术语“示例性实施例”不是指相同的示例性实施例,而是被提供来强调与另一示例性实施例的特定特征或特性不同的特定特征或特性。然而,这里提供的示例性实施例被认为能够通过彼此全部或部分地组合来实现。例如,除非其中提供了相反或相矛盾的描述,否则即使特定示例性实施例中描述的一个元件未在另一示例性实施例中描述,该元件仍可被理解为与另一示例性实施例相关的描述。
在说明书中,组件与另一组件的“连接”的含义包括通过第三组件的间接连接以及两个组件之间的直接连接。另外,从概念上讲,术语“电连接或者按照信号方式连接”包括物理连接和物理断开。可理解的是,当利用诸如“第一”和“第二”的术语来提及元件时,该元件不会由此受限。它们可仅用于将元件与其他元件相区分的目的,并且可不限制元件的顺序或重要性。在一些情况下,在不脱离这里所阐述的权利要求的范围的情况下,第一元件可被称为第二元件。类似地,第二元件也可被称为第一元件。
这里,上部、下部、上侧、下侧、上表面、下表面等在附图中被确定。例如,第一连接构件设置在重新分布层的上方的水平面上。然而,权利要求不限于此。另外,竖直方向指的是向上的方向和向下的方向,水平方向指的是与上述向上的方向和向下的方向垂直的方向。在这种情况下,竖直截面指的是沿着在竖直方向上的平面截取的情况,其示例可以为附图中示出的截面图。另外,水平截面指的是沿着在水平方向上的平面截取的情况,其示例可以为附图中示出的平面图。
电子装置
图1是示出电子装置系统的示例的示意性框图。
参照图1,电子装置1000可将主板1010容纳在其中。主板1010可包括物理连接或者电连接到其的芯片相关组件1020、网络相关组件1030、其他组件1040等。这些组件可通过各种信号线1090连接到以下将描述的其他组件。
芯片相关组件1020可包括:存储芯片,诸如易失性存储器(例如,动态随机存取存储器(DRAM))、非易失性存储器(例如,只读存储器(ROM))、闪存等;应用处理器芯片,诸如中央处理器(例如,中央处理单元(CPU))、图形处理器(例如,图形处理单元(GPU))、数字信号处理器、密码处理器、微处理器、微控制器等;及逻辑芯片,诸如模拟数字转换器(ADC)、专用集成电路(ASIC)等。然而,芯片相关组件1020不限于此,而是还可包括其他类型的芯片相关组件。此外,芯片相关组件1020可彼此组合。
网络相关组件1030可包括被指定为根据诸如以下的协议操作的组件:无线保真(Wi-Fi)(电工电子工程师协会(IEEE)802.11族等)、全球微波接入互操作性(WiMAX)(IEEE802.16族等)、IEEE 802.20、长期演进技术(LTE)、演进数据最优化(Ev-DO)、高速分组接入+(HSPA+)、高速下行链路分组接入+(HSDPA+)、高速上行链路分组接入+(HSUPA+)、增强型数据GSM环境(EDGE)、全球移动通信系统(GSM)、全球定位系统(GPS)、通用分组无线业务(GPRS)、码分多址(CDMA)、时分多址(TDMA)、数字增强型无绳电信(DECT)、蓝牙、3G协议、4G协议和5G协议以及在上述协议之后指定的任何其他无线协议和有线协议。然而,网络相关组件1030不限于此,而是还可包括被指定为根据各种其他无线标准或协议或者有线标准或协议操作的组件。此外,网络相关组件1030可与上述芯片相关组件1020一起彼此组合。
其他组件1040可包括高频电感器、铁氧体电感器、功率电感器、铁氧体磁珠、低温共烧陶瓷(LTCC)、电磁干扰(EMI)滤波器、多层陶瓷电容器(MLCC)等。然而,其他组件1040不限于此,而是还可包括用于各种其他目的的无源组件等。此外,其他组件1040可与上述芯片相关组件1020或网络相关组件1030一起彼此组合。
根据电子装置1000的类型,电子装置1000可包括可物理连接或电连接到主板1010或者可不物理连接或电连接到主板1010的其他组件。这些其他组件可包括例如相机1050、天线1060、显示器1070、电池1080、音频编解码器(未示出)、视频编解码器(未示出)、功率放大器(未示出)、指南针(未示出)、加速计(未示出)、陀螺仪(未示出)、扬声器(未示出)、大容量存储单元(例如,硬盘驱动器)(未示出)、光盘(CD)驱动器(未示出)、数字通用光盘(DVD)驱动器(未示出)等。然而,这些其他组件不限于此,而是还可根据电子装置1000的类型等而包括用于各种目的的其他组件。
电子装置1000可以是智能电话、个人数字助理(PDA)、数字摄像机、数码相机、网络系统、计算机、监视器、平板PC、膝上型PC、上网本PC、电视机、视频游戏机、智能手表、汽车组件等。然而,电子装置1000不限于此,而可以是处理数据的任何其他电子装置。
图2是示出电子装置的示例的示意性透视图。
参照图2,在如上所述的各种电子装置1000中可使用用于各种目的的半导体封装件。例如,母板1110可容纳在智能电话1100的主体1101中,并且各种电子组件1120可物理连接或者电连接到母板1110。另外,可物理连接或者电连接到母板1110或者可不物理连接或者电连接到母板1110的其他组件(诸如,相机模块1130)可容纳在主体1101中。电子组件1120中的一些可以是芯片相关组件(例如,半导体封装件1121),但不限于此。电子装置不必须限制于智能电话1100,而可以是如上所述的其他电子装置。
半导体封装件
通常,半导体芯片中集成了大量的微电子电路。然而,半导体芯片本身可能不能用作成品的半导体产品,并且可能会由于外部物理冲击或者化学冲击而损坏。因此,半导体芯片本身可能不会被使用,但半导体芯片可被封装并且在封装的状态下用在电子装置等中。
这里,就电连接而言,由于半导体芯片和电子装置的主板之间的电路宽度存在差异,因此需要半导体封装。详细地,半导体芯片的连接焊盘的尺寸和半导体芯片的连接焊盘之间的间距非常精细,而电子装置中使用的主板的组件安装焊盘的尺寸和主板的组件安装焊盘之间的间距显著地大于半导体芯片的连接焊盘的尺寸和半导体芯片的连接焊盘之间的间距。因此,可能难以将半导体芯片直接安装在主板上,并且需要用于缓解半导体芯片和主板之间的电路宽度的差异的封装技术。
通过封装技术制造的半导体封装件可根据其结构和目的而分为扇入型半导体封装件和扇出型半导体封装件。
在下文中,将参照附图更详细地描述扇入型半导体封装件和扇出型半导体封装件。
扇入型半导体封装件
图3A和图3B是示出扇入型半导体封装件在被封装之前和封装之后的状态的示意性截面图。
图4是示出扇入型半导体封装件的封装工艺的示意性截面图。
参照图3A、图3B以及图4,半导体芯片2220可以是例如处于裸态的集成电路(IC),并且包括:主体2221,包括硅(Si)、锗(Ge)、砷化镓(GaAs)等;连接焊盘2222,形成在主体2221的一个表面上,并且包括诸如铝(Al)等的导电材料;及诸如氧化物膜、氮化物膜等的钝化层2223,形成在主体2221的一个表面上并且覆盖连接焊盘2222的至少部分。在这种情况下,由于连接焊盘2222可能会非常小,因此可能会难以将集成电路(IC)安装在中等尺寸等级的印刷电路板(PCB)上以及电子装置的主板等上。
因此,连接构件2240可根据半导体芯片2220的尺寸形成在半导体芯片2220上,以使连接焊盘2222重新分布。连接构件2240可通过如下步骤形成:使用诸如感光介电(PID)树脂的绝缘材料在半导体芯片2220上形成绝缘层2241,形成使连接焊盘2222敞开的通路孔2243h,然后形成布线图案2242和过孔2243。然后,可形成保护连接构件2240的钝化层2250,可形成开口2251,并且可形成凸块下金属层2260等。也就是说,可通过一系列工艺制造包括例如半导体芯片2220、连接构件2240、钝化层2250和凸块下金属层2260的扇入型半导体封装件2200。
如上所述,扇入型半导体封装件可具有半导体芯片的所有的连接焊盘(例如,输入/输出(I/O)端子)设置在半导体芯片的内部的封装件形式,可具有优异的电特性并且可按照低成本生产。因此,安装在智能电话中的许多元件已经按照扇入型半导体封装件形式来制造。详细地,安装在智能电话中的许多元件已经被开发为在具有紧凑的尺寸的同时实现快速的信号传输。
然而,在扇入型半导体封装件中,由于所有的I/O端子需要设置在半导体芯片的内部,因此扇入型半导体封装件具有很大的空间局限性。因此,难以将这样的结构应用于具有大量的I/O端子的半导体芯片或者具有紧凑的尺寸的半导体芯片。另外,由于上述缺点,可能不能在电子装置的主板上直接安装并使用扇入型半导体封装件。原因是:即使在半导体芯片的I/O端子的尺寸和半导体芯片的I/O端子之间的间距通过重新分布工艺被增大的情况下,半导体芯片的I/O端子的尺寸和半导体芯片的I/O端子之间的间距可能仍不足以将扇入型半导体封装件直接安装在电子装置的主板上。
图5是示出扇入型半导体封装件安装在球栅阵列(BGA)基板上并且最终安装在电子装置的主板上的情况的示意性截面图。
图6是示出扇入型半导体封装件嵌入在BGA基板中并且最终安装在电子装置的主板上的情况的示意性截面图。
参照图5,在扇入型半导体封装件2200中,半导体芯片2220的连接焊盘2222(即,I/O端子)可通过BGA基板2301重新分布,并且在扇入型半导体封装件2200安装在BGA基板2301上的状态下,扇入型半导体封装件2200可最终安装在电子装置的主板2500上。在这种情况下,焊球2270等可通过底部填充树脂2280等固定,并且半导体芯片2220的外侧可利用模制材料2290等覆盖。可选地,参照图6,扇入型半导体封装件2200可嵌入在单独的BGA基板2302中,在扇入型半导体封装件2200嵌入在BGA基板2302中的状态下,半导体芯片2220的连接焊盘2222(即,I/O端子)可通过BGA基板2302重新分布,并且扇入型半导体封装件2200可最终安装在电子装置的主板2500上。
如上所述,可能会难以在电子装置的主板上直接安装并使用扇入型半导体封装件。因此,扇入型半导体封装件可安装在单独的BGA基板上然后通过封装工艺安装在电子装置的主板上,或者可在扇入型半导体封装件嵌入在BGA基板中的状态下在电子装置的主板上安装并使用扇入型半导体封装件。
扇出型半导体封装件
图7是示出扇出型半导体封装件的示意性截面图。
参照图7,在扇出型半导体封装件2100中,例如,半导体芯片2120的外侧可通过包封剂2130保护,并且半导体芯片2120的连接焊盘2122可通过连接构件2140重新分布到半导体芯片2120的外部。在这种情况下,钝化层2150还可形成在连接构件2140上,并且凸块下金属层2160还可形成在钝化层2150的开口中。焊球2170还可形成在凸块下金属层2160上。半导体芯片2120可以是包括主体2121、连接焊盘2122、钝化层(未示出)等的集成电路(IC)。连接构件2140可包括:绝缘层2141;重新分布层2142,形成在绝缘层2141上;及过孔2143,使连接焊盘2122和重新分布层2142彼此电连接。
如上所述,扇出型半导体封装件可具有半导体芯片的I/O端子通过形成在半导体芯片上的连接构件重新分布并且设置在半导体芯片的外部的形式。如上所述,在扇入型半导体封装件中,半导体芯片的所有的I/O端子需要设置在半导体芯片的内部。因此,当半导体芯片的尺寸减小时,球的尺寸和节距需要减小,使得在扇入型半导体封装件中可能无法使用标准化的球布局。另一方面,如上所述,扇出型半导体封装件具有半导体芯片的I/O端子通过形成在半导体芯片上的连接构件重新分布并且设置在半导体芯片的外部的形式。因此,即使在半导体芯片的尺寸减小的情况下,仍可在扇出型半导体封装件中按照原样使用标准化的球布局,使得扇出型半导体封装件可在不使用单独的BGA基板的情况下安装在电子装置的主板上,如下所述。
图8是示出扇出型半导体封装件安装在电子装置的主板上的情况的示意性截面图。
参照图8,扇出型半导体封装件2100可通过焊球2170等安装在电子装置的主板2500上。也就是说,如上所述,扇出型半导体封装件2100包括连接构件2140,连接构件2140形成在半导体芯片2120上并且能够使连接焊盘2122重新分布到半导体芯片2120的尺寸的外部的扇出区域,使得可在扇出型半导体封装件2100中按照原样使用标准化的球布局。结果,扇出型半导体封装件2100可在不使用单独的BGA基板等的情况下安装在电子装置的主板2500上。
如上所述,由于扇出型半导体封装件可在不使用单独的BGA基板的情况下安装在电子装置的主板上,因此扇出型半导体封装件可按照比使用BGA基板的扇入型半导体封装件的厚度小的厚度实现。因此,扇出型半导体封装件可被小型化和纤薄化。另外,扇出型半导体封装件具有优异的热特性和电特性,使得其特别适合于移动产品。因此,扇出型半导体封装件可按照比使用印刷电路板(PCB)的普通的层叠封装(POP)类型的形式更紧凑的形式实现,并且可解决由于翘曲现象的发生而引起的问题。
同时,扇出型半导体封装指的是如上所述的用于将半导体芯片安装在电子装置的主板等上并且保护半导体芯片免受外部冲击的影响的封装技术,并且是与诸如BGA基板等的印刷电路板(PCB)(具有与扇出型半导体封装件的尺寸、用途等不同的尺寸、用途等,并且具有嵌在其中的扇入型半导体封装件)的概念不同的概念。
在下文中,将参照附图描述其中引入了芯构件的扇出型半导体封装件,其中,芯构件中形成有天线图案和接地图案。
扇出型半导体封装件
图9是示出扇出型半导体封装件的示例的示意性截面图。
图10是示出当从上方观察时图9的扇出型半导体封装件的示意性平面图。
图11A和图11B是示出当从上方观察时图9的扇出型半导体封装件的各种示例的示意性平面图。
参照图9至图11A和图11B,根据本公开中的示例性实施例的扇出型半导体封装件100A可包括:芯构件110,具有其第一表面被屏障图案112aM封闭的盲腔110H;半导体芯片120,具有其上设置有连接焊盘120P的有效表面和与有效表面背对的无效表面,并且设置在芯构件110的盲腔110H中,使得无效表面附着到屏障图案112aM;包封剂130,包封芯构件110的至少部分和半导体芯片120的有效表面的至少部分,并且填充盲腔110H的至少部分;及连接构件140,设置在芯构件110和半导体芯片120的有效表面上并且包括连接到连接焊盘120P的重新分布层142。如果必要,具有使重新分布层142的至少部分暴露的开口的钝化层150可设置在连接构件140上,连接到暴露的重新分布层142的凸块下金属层160和/或电连接结构170可设置在钝化层150上。另外,覆盖天线图案112dA-1和112dA-2的覆盖层180可设置在芯构件110上。
芯构件110可包括:多个绝缘层111a、111b和111c;多个布线层112a、112b、112c和112d;及多个过孔113a、113b和113c。在这种情况下,第四布线层112d可包括天线图案112dA-1和112dA-2。另外,第三布线层112c可包括接地图案112cG。天线图案112dA-1和112dA-2可通过馈线113F-1和113F-2连接到重新分布层142,并且可通过重新分布层142连接到连接焊盘120P。另外,天线图案112dA-1和112dA-2和接地图案112cG可在多个绝缘层111a、111b和111c的堆叠方向上彼此至少部分地叠置。如上所述,在根据示例性实施例的扇出型半导体封装件100A中,具有呈盲孔形式的盲腔110H的芯构件110可被引入以在单个扇出型半导体封装件100A中集成半导体芯片120以及天线图案112dA-1和112dA-2。
同时,在天线与射频集成电路(RFIC)一起形成在一个封装件中的情况下,需要考虑如何实现天线、接地面、介电材料、馈线等,以确定天线的谐振频率和带宽。例如,对天线的特性具有敏感的影响的天线和接地面之间的距离(也就是说,空气层的厚度或者介电材料的厚度)需要被恒定地保持和管理,以确保天线的稳定的辐射特性。
在现有技术的情况下,如通过图17中的示例的方式示出的,使用了在封装件200的重新分布层240上形成天线242A并且在主板300上形成接地面302G的方式。在这种情况下,需要通过封装件200A的焊球270的高度确保天线242A和接地面302G之间的厚度或距离d。因此,当封装件200安装在主板300上时,根据焊球被压实的高度水平可能会产生厚度差。另外,在这种情况下,空气被用作介电层的材料,并且因此增大了天线242A的尺寸。另外,在这种情况下,助焊剂(flux)或者外来材料可能会插入到天线242A和接地面302G之间的空间中,结果对天线242A的特性产生显著的影响。另外,在这种情况下,当RFIC 220中产生热时,难以确保充足的散热路径,因此,在使用大量的电力的产品中使用这样的方式存在局限性。
另外,在现有技术的情况下,如通过图18和图19中的示例的方式示出的,使用了通过在天线板250A或者250B上堆叠按照现有的方式封装在60GHz通信系统中的RFIC封装件280而制造的集成模块。在这些产品中,包括天线图案和接地层(ground)的天线图案部b以及用于RFIC信号重新分布的布线部a在具有多层PCB形式的天线板250A或250B上实现,并且RFIC封装件280附着到天线板250A或250B的下表面。因此,封装模块的整体厚度增大,使得在移动产品或者小型物联网(IoT)产品中使用封装模块可能会存在局限性,并且制造封装模块的工艺复杂。另外,一些产品具有上述的诸如确保焊球270的高度的问题。
另一方面,在根据示例性实施例的扇出型半导体封装件100A中,可引入芯构件110,天线图案112dA-1和112dA-2以及接地图案112cG可形成在芯构件110的上部中,具有盲孔形式的盲腔110H可形成在芯构件110的下部中,诸如RFIC等的半导体芯片120可设置在盲腔110H中,并且馈线113F-1和113F-2可通过芯构件110的过孔113a、113b和113c实现。因此,可在单个封装件中稳定地确保天线图案112dA-1和112dA-2与接地图案112cG之间的距离,而不论外部环境如何变化,以保持天线图案112dA-1和112dA-2的辐射特性。同时,可显著地减小天线图案112dA-1和112dA-2与诸如RFIC等的半导体芯片120之间的信号路径,以确保稳定的射频(RF)特性。另外,可使用芯构件110的各个绝缘层111a、111b和111c的介电常数减小天线图案112dA-1和112dA-2的尺寸,以减小扇出型半导体封装件100A的整体尺寸,结果提高空间效率并且降低成本。另外,外来材料将设置在天线图案112dA-1和112dA-2与接地图案112cG之间的空间中的可能性可以是非常低的,从而可防止由于外来材料而导致天线图案112dA-1和112dA-2的性能劣化。另外,电连接结构170不限于焊球,并且可以按照小厚度实现。
同时,从概念上讲,这里的术语“连接”包括组件彼此电连接或者按照信号方式连接的情况以及组件彼此物理连接的情况。另外,术语‘连接’是包括间接连接以及直接连接的概念。另外,术语“电连接或者按照信号方式连接”是包括物理连接和物理断开的概念。
在下文中,将更详细地描述根据示例性实施例的扇出型半导体封装件100A的组件。
芯构件110可设置有天线图案112dA-1和112dA-2、接地图案112cG、用于连接焊盘120P的各种重新分布图案等。芯构件110可根据特定材料提高扇出型半导体封装件100A的刚性,并且用于确保包封剂130的厚度的均匀性。芯构件110可具有盲腔110H。盲腔110H的第一表面可被屏障图案112aM封闭,并且半导体芯片120的无效表面可通过诸如芯片附着膜(DAF,die attach film)的粘合构件120B附着到盲腔110H的屏障图案112aM。半导体芯片120的侧表面可被芯构件110的盲腔110H的壁围绕。盲腔110H可通过喷砂工艺形成。在这种情况下,盲腔110H的截面可具有锥形形状。也就是说,盲腔110H的壁可相对于屏障图案112aM或者多个布线层112a至112d中的一者具有锐角的斜度。在这种情况下,对齐半导体芯片120的工艺可以是容易的,并且因此可提高半导体芯片120的良率。
芯构件110可包括:第一绝缘层111a;第一布线层112a,设置在第一绝缘层111a的第一表面上;第二布线层112b,设置在第一绝缘层111a的第二表面上;第二绝缘层111b,设置在第一绝缘层111a的第一表面上并且覆盖第一布线层112a;第三布线层112c,设置在第二绝缘层111b上;第三绝缘层111c,设置在第二绝缘层111b上并且覆盖第三布线层112c;及第四布线层112d,设置在第三绝缘层111c上。另外,芯构件110可包括:第一过孔113a,贯穿第一绝缘层111a并且使第一布线层112a和第二布线层112b彼此连接;第二过孔113b,贯穿第二绝缘层111b并且使第一布线层112a和第三布线层112c彼此连接;及第三过孔113c,贯穿第三绝缘层111c并且使第三布线层112c和第四布线层112d彼此连接。第一布线层112a、第二布线层112b、第三布线层112c和第四布线层112d可通过重新分布层142连接到半导体芯片120的连接焊盘120P。
屏障图案112aM可设置在第一绝缘层111a的第一表面上,屏障图案112aM的第一表面可被第二绝缘层111b覆盖,并且屏障图案112aM的与屏障图案112aM的第一表面背对的第二表面的至少一部分可通过盲腔110H暴露。盲腔110H可贯穿第一绝缘层111a。形成在第一绝缘层111a中的盲腔110H的壁可具有锐角的斜度。屏障图案112aM的与第一绝缘层111a接触的边缘区域的厚度可大于屏障图案112aM的通过盲腔110H从第一绝缘层111a暴露的区域的厚度。原因是:暴露的区域的一部分在喷砂工艺中还可被去除。屏障图案112aM可以是包括铜(Cu)的金属板。然而,屏障图案112aM不限于此,而是也可以为包括感光材料的绝缘膜(诸如,干膜)。
绝缘层111a、111b和111c中的每个的材料没有具体地限制。例如,绝缘材料可用作绝缘层111a、111b和111c中的每个的材料。在这种情况下,绝缘材料可以为诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂、诸如玻璃纤维(或玻璃布或玻璃织物)的芯材料与无机填料一起浸入在热固性树脂或者热塑性树脂中的树脂(例如,半固化片、ABF(Ajinomoto Build up Film)、FR-4、双马来酰亚胺三嗪(BT))等。各个绝缘层111a、111b和111c可包括相同的材料或者包括不同的材料。作为非限制性示例,第一绝缘层111a的材料可以为具有用于减小滤波器的损耗的低介电常数特性的材料,并且第三绝缘层111c的材料可以为具有用于减小天线的尺寸的高介电常数特性的材料,或者,反之亦然。在第一绝缘层111a、第二绝缘层111b和第三绝缘层111c中,其上直接设置有天线图案112dA-1和112dA-2的绝缘层111c可具有最大的介电常数。第一绝缘层111a的厚度和第三绝缘层111c的厚度可大于第二绝缘层111b的厚度。第一绝缘层111a可具有与半导体芯片120的厚度相对应的厚度,并且第三绝缘层111c可具有足够确保天线图案112dA-1和112dA-2与接地图案112cG之间的距离的厚度。
布线层112a、112b、112c和112d中的每个的材料可以为诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金的导电材料。布线层112a、112b、112c和112d可根据相应的层的设计执行各种功能。第一布线层112a和第二布线层112b可包括诸如信号线、电力线、接地线、信号焊盘、电力焊盘、接地焊盘等的通用的重新分布图案。第二布线层112b可包括也可用作接地层的屏障图案112aM。第三布线层112c可包括接地图案112cG。接地图案112cG可占据第二绝缘层111b的上表面的大部分。接地图案112cG可用作各种信号图案等以及天线图案112dA-1和112dA-2的接地层。第四布线层112d可包括天线图案112dA-1和112dA-2。天线图案112dA-1和112dA-2可以为贴片天线或者阵列天线。可选地,天线图案112dA-1和112dA-2可以为折叠偶极天线或者是共面贴片天线。可选地,天线图案112dA-1和112dA-2可以为环形天线、回路天线等,并且各个天线可具有诸如矩形形状、正方形形状、圆形形状、放射状等的各种形状。同时,天线图案112dA-1和112dA-2可以为发送(Tx)天线图案和接收(Rx)天线图案被形成为如图11A中所示的单个天线图案112dA,或者可以为如图11B中所示的具有更多数量并且彼此分开的多个天线图案112dA-1、112dA-2、112dA-3和112dA-4。同时,第四布线层112d可包括诸如微带线、带状线等的滤波器图案(未示出)。
过孔113a、113b和113c可使形成在不同的层上的布线层112a、112b、112c和112d彼此连接。过孔113a、113b和113c可包括用于信号连接的过孔或者用于接地连接的过孔。过孔113a、113b和113c中的每个的材料可以为诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金的导电材料。可以利用导电材料完全填充过孔113a、113b和113c中的每个,或者也可沿着过孔中的每个的壁形成导电材料。另外,过孔113a、113b和113c中的每个可具有沙漏形状、圆柱形形状、锥形形状等。过孔113a、113b和113c可提供用于天线图案112dA-1和112dA-2的馈线113F-1和113F-2。
半导体芯片120可以为按照数百至数百万或更多的数量的元件集成在单个芯片中设置的处于裸态的集成电路(IC)。集成电路(IC)可以为例如射频集成电路(RFIC)。也就是说,根据示例性实施例的扇出型半导体封装件100A可以为RFIC和毫米波/5G天线彼此集成的封装件。半导体芯片120可包括其上形成有各种电路的主体,并且连接焊盘120P可形成在主体的有效表面上。主体可在例如有效晶圆的基础上形成。在这种情况下,主体的基体材料可以为硅(Si)、锗(Ge)、砷化镓(GaAs)等。连接焊盘120P可使半导体芯片120连接到其他组件,并且连接焊盘120P中的每个的材料可以为诸如铝(Al)的导电材料,但不限于此。半导体芯片120的有效表面指的是半导体芯片120的其上设置有连接焊盘120P的表面,半导体芯片120的无效表面指的是半导体芯片120的与有效表面背对的表面。在示例性实施例中,半导体芯片120可设置在芯构件110的盲腔110H中使得半导体芯片120的无效表面附着到屏障图案112aM。粘合构件120B等可用于将半导体芯片120的无效表面附着到屏障图案112aM。
包封剂130可被构造为保护半导体芯片120并且提供绝缘区域。包封剂130的包封形式没有具体地限制,并且可以为包封剂130围绕半导体芯片120的至少部分的形式。例如,包封剂130可覆盖芯构件110的下表面并且覆盖半导体芯片120的侧表面和有效表面。另外,包封剂130可填充盲腔110H中的空间。包封剂130的特定材料没有具体地限制,而可以是诸如ABF的绝缘材料。可选地,感光包封剂(PIE)可用包封剂130的材料。
连接构件140可用于将根据示例性实施例的扇出型半导体封装件100A连接到外部组件。另外,连接构件140可使半导体芯片120的连接焊盘120P重新分布。连接构件140可包括设置在包封剂130上的重新分布层142和贯穿包封剂130并且使重新分布层142连接到第二布线层112b和连接焊盘120P的过孔143。在示例性实施例中,示出了重新分布层142和过孔143形成在包封剂130上和包封剂130中的情况,但是如果必要,可通过将通过另外涂覆PID等并使其硬化而形成的绝缘层添加到包封剂130来形成更多数量的重新分布层和过孔。
重新分布层142可用于使半导体芯片120的连接焊盘120P重新分布,并且重新分布层142的材料可以为诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金的导电材料。重新分布层142可根据相应的层的设计执行各种功能。例如,重新分布层142可包括接地线、信号线等。另外,重新分布层142可包括用于接地的焊盘、用于信号的焊盘等。同时,可使用扇出型面板级封装(FO-PLP)技术对RFIC执行单个芯片封装,仅用于天线馈线和接地连接的输入/输出(I/O)端子可形成在RFIC的芯部的顶表面上,并且用于RF输入、控制信号、电力、接地连接等的I/O端子可形成在其底表面上。
过孔143可使形成在不同的层上的重新分布层142、连接焊盘120P、第二布线层112b等彼此电连接。过孔143中的每个的材料可以为诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金的导电材料。可以利用导电材料完全填充过孔143中的每个,或者也可沿着过孔中的每个的壁形成导电材料。另外,过孔143中的每个可具有锥形形状等。过孔143还可包括用于接地的过孔和用于信号的过孔等。
钝化层150可被另外构造为保护连接构件140免受外部物理损坏或化学损坏。钝化层150可具有使连接构件140的重新分布层142c的至少部分暴露的开口。形成在钝化层150中的开口的数量可以为数十至数百万。钝化层150的材料没有具体地限制。例如,绝缘材料可用作钝化层150的材料。在这种情况下,绝缘材料可以为诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂、热固性树脂或热塑性树脂与无机填料混合或诸如玻璃纤维(或玻璃布或玻璃织物)的芯材料与无机填料一起浸在热固性树脂或热塑性树脂中的树脂(例如,半固化片、ABF、FR-4、BT)等。可选地,也可使用阻焊剂。
凸块下金属层160可被另外构造为提高电连接结构170的连接可靠性,以提高扇出型半导体封装件100A的板级可靠性。凸块下金属层160可连接到连接构件140的通过钝化层150的开口暴露的重新分布层142。凸块下金属层160可通过任意已知的金属化方法使用任意已知的导电材料(诸如,金属)形成在钝化层150的开口中,但不限于此。
电连接结构170可被另外构造为使扇出型半导体封装件100A物理连接或者电连接到外部。例如,扇出型半导体封装件100A可通过电连接结构170安装在电子装置的主板上。电连接结构170中的每个可利用例如焊料等的导电材料形成。然而,这仅是示例,电连接结构170中的每个的材料不被具体地限制于此。电连接结构170中的每个可以为焊盘、焊球、引脚等。电连接结构170可形成为多层结构或单层结构。当电连接结构170形成为多层结构时,电连接结构170可包括铜(Cu)柱和焊料。当电连接结构170形成为单层结构时,电连接结构170可包括锡-银焊料或铜(Cu)。然而,这仅是示例,电连接结构170不限于此。电连接结构170的数量、间距、布置形式等没有具体地限制,而本领域技术人员可根据设计细节进行充分地修改。例如,电连接结构170可根据连接焊盘120P的数量按照数十至数千的数量设置,或者可按照数十至数千或更多或者数十至数千或更少的数量设置。
电连接结构170中的至少一个可设置在扇出区域中。扇出区域指的是除了设置有半导体芯片120的区域之外的区域。与扇入型封装件相比,扇出型封装件可具有优异的可靠性,可实现多个输入/输出(I/O)端子,并且可促进3D互连。此外,与球栅阵列(BGA)封装件、栅格阵列(LGA)封装件等相比,扇出型封装件可被制造为具有小的厚度,并且可具有价格竞争力。
覆盖层180可保护芯构件110免受外部物理损坏或化学损坏。覆盖层180的材料没有具体地限制。例如,绝缘材料可用作覆盖层的材料。在这种情况下,绝缘材料可以为诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂、热固性树脂或热塑性树脂与无机填料混合或诸如玻璃纤维(或玻璃布或玻璃织物)的芯材料与无机填料一起浸在热固性树脂或热塑性树脂中的树脂(例如,半固化片、ABF、FR-4、BT)等。可选地,也可使用阻焊剂。
图12是示出用于制造图9的扇出型半导体封装件的面板的示例的示意图。
参照图12,芯构件110可使用具有大的面积的面板500形成。例如,当包括天线图案112dA-1和112dA-2、接地图案112cG、馈线113F-1和113F-2等的芯构件110在具有大的面积的多层PCB面板上按照阵列形式实现时,具有盲孔形式的盲腔110H形成在各个芯构件110中,半导体芯片120附着到各个盲腔110H,天线图案112dA-1和112dA-2的馈线113F-1和113F-2以及半导体芯片120的通用控制信号图案通过形成重新分布层142彼此连接,以制造单个扇出型半导体封装件,单个扇出型半导体封装件通过切割工艺被切割为各个扇出型半导体封装件100A,并且可通过执行一次工艺制造大量的扇出型半导体封装件100A。同时,当使用面板500时,制造工艺可以是简单的并且可降低成本。例如,用于天线图案112dA-1和112dA-2的接地层或者各种其他信号图案可仅通过接地图案112cG解决。另外,在控制如上所述的在单个面板500的基础上形成的芯构件110围绕半导体芯片120的扇出型半导体封装件100A的翘曲方面可以是更有效的,并且当金属层形成在芯构件110的盲腔110H的壁上时,金属层可无缝地围绕半导体芯片120,并且散热效果或者电磁波阻挡效果可因此非常优异。
图13A和图13B是示出制造图9的扇出型半导体封装件的工艺的示例的示意图。
参照图13A,可制备芯构件110。可通过如下步骤制备芯构件110:使用覆铜层压板(CCL)等形成第一绝缘层111a、形成在第一绝缘层111a上和第一绝缘层111a的下方的第一布线层112a和第二布线层112b以及形成在第一绝缘层111a中的第一过孔113a;使用ABF等在第一绝缘层111a上形成第二绝缘层111b;在第二绝缘层111b上形成第三布线层112c并且在第二绝缘层111b中形成第二过孔113b;使用CCL等在第二绝缘层111b上形成第三绝缘层111c;以及在第三绝缘层111c上形成第四布线层112d并且在第三绝缘层111c中形成第三过孔113c。可通过任意已知的镀覆工艺形成布线层112a、112b、112c和112d,可通过激光钻孔等形成通路孔然后通过镀覆填充通路孔而形成过孔113a、113b和113c。可使用ABF等在芯构件110上形成覆盖层180。然后,可使用第二布线层112b的屏障图案112aM作为止挡件来形成盲腔110H。可使用机械钻孔和/或激光钻孔形成盲腔110H或者可通过喷砂等形成盲腔110H,并且当使用喷砂时,盲腔可具有呈锥形形状的倾斜。然后,可在盲腔110H中设置半导体芯片120。半导体芯片120可被设置为使得无效表面附着到屏障图案112aM,并且可使用粘合构件120B等将半导体芯片120的无效表面附着到屏障图案112aM。
然后,参照图13B,可形成包封剂130。可通过堆叠处于b阶段的膜然后使该膜硬化来形成包封剂130,或者可通过任意已知的涂覆方法涂覆用于形成包封剂130的液相材料然后使该液相材料硬化来形成包封剂130。然后,可在包封剂130上形成重新分布层142并且在包封剂130中形成过孔143以形成连接构件140,并且可形成钝化层150、凸块下金属层160和电连接结构170。同时,可通过任意已知的镀覆工艺形成重新分布层142,可通过形成通路孔然后通过镀覆填充通路孔而形成过孔143。可通过层叠ABF等形成钝化层150,可通过任意已知的金属化方法形成凸块下金属层160,可通过形成诸如锡(Sn)-铝(Al)-铜(Cu)合金的低熔点金属然后对低熔点金属执行回流工艺来形成电连接结构170。然而,形成钝化层150、凸块下金属层160和电连接结构170的方法不限于此。
图14是示出扇出型半导体封装件的另一示例的示意性截面图。
参照图14,在根据本公开中的另一示例性实施例的扇出型半导体封装件100B中,芯构件110可包括:第一绝缘层111a;第一布线层112a,设置在第一绝缘层111a的第一表面上;第二布线层112b,设置在第一绝缘层111a的第二表面上;第二绝缘层111b,设置在第一绝缘层111a的第一表面上并且覆盖第一布线层112a;及第三布线层112c,设置在第二绝缘层111b上。另外,芯构件110可包括:第一过孔113a,贯穿第一绝缘层111a并且使第一布线层112a和第二布线层112b彼此电连接;及第二过孔113b,贯穿第二绝缘层111b并且使第一布线层112a和第三布线层112c彼此电连接。第一布线层112a、第二布线层112b和第三布线层112c可通过重新分布层142连接到半导体芯片120的连接焊盘120P。也就是说,与根据上述示例性实施例的扇出型半导体封装件100A相比,减少了一个绝缘层、一个布线层和一个过孔层。
各个绝缘层111a和111b可包括相同的材料或者包括不同的材料。作为非限制性示例,第一绝缘层111a的材料可以为具有用于减小滤波器的损耗的低介电常数特性的材料,第二绝缘层111b的材料可以为具有用于减小天线的尺寸的高介电常数特性的材料,或者,反之亦然。第一绝缘层111a可具有与半导体芯片120的厚度对应的厚度,第二绝缘层111b可具有足够确保天线图案112cA-1和112cA-2与接地图案112aG之间的距离的厚度。
第一布线层112a可包括诸如信号线、电力线、接地线、信号焊盘、电力焊盘、接地焊盘等的通用的重新分布图案。第一布线层112a可包括也可被用作接地图案112aG的屏障图案112aM。接地图案112aG可用作各种信号图案等以及天线图案112cA-1和112cA-2的接地层。第三布线层112c可包括天线图案112cA-1和112cA-2。同时,第三布线层112c可包括诸如微带线、带状线等的滤波器图案(未示出)。
其他构造和制造工艺与上述其他构造和制造工艺重复,因此省略其详细描述。
图15是示出扇出型半导体封装件的另一示例的示意性截面图。
参照图15,根据本公开中的另一示例性实施例的扇出型半导体封装件100C除了芯构件110的第一布线层112a包括诸如微带线、带状线等的滤波器图案112aR之外可与上述根据示例性实施例的扇出型半导体封装件100A大体上相同。滤波器图案112aR可具有连接到半导体芯片120的连接焊盘120P的一端和连接到天线图案112dA-1和112dA-2的馈线113F-1和113F-2的另一端。连接焊盘120P以及天线图案112dA-1和112dA-2可按照信号方式通过滤波器图案112aR彼此连接。在一些情况下,滤波器图案112aR也可形成在第二布线层112b上。接地图案112cG可用作用于滤波器图案112aR的接地层。同时,盲腔110H可贯穿第一绝缘层111a和第二绝缘层111b,屏障图案112cM还可被用作接地图案112cG。也就是说,屏障图案112cM可设置在第二绝缘层111b的第一表面上,屏障图案112cM的第一表面可被第三绝缘层111c覆盖,并且屏障图案112cM的与屏障图案112cM的第一表面背对的第二表面的至少一部分可通过盲腔110H暴露。盲腔110H可贯穿第一绝缘层111a和第二绝缘层111b。形成在第一绝缘层111a和111b中的盲腔110H的壁可具有锐角的斜度。屏障图案112cM的与第二绝缘层111b接触的边缘区域的厚度可大于屏障图案112cM的通过盲腔110H从第二绝缘层111b暴露的区域的厚度。原因是:暴露的区域的一部分在喷砂工艺中还可被去除。
其他构造和制造工艺与上述其他构造和制造工艺重复,因此省略其详细描述。
图16是示出扇出型半导体封装件的另一示例的示意性截面图。
参照图16,根据本公开中的另一示例性实施例的扇出型半导体封装件100D除了芯构件110的第二布线层112b包括诸如微带线、带状线等的滤波器图案112bR之外可与上述根据另一示例性实施例的扇出型半导体封装件100B大体上相同。滤波器图案112bR可具有连接到半导体芯片120的连接焊盘120P的一端和连接到天线图案112cA-1和112cA-2的馈线113F-1和113F-2的另一端。连接焊盘120P以及天线图案112cA-1和112cA-2可按照信号方式通过滤波器图案112bR彼此连接。接地图案112aG可用作用于滤波器图案112bR的接地层。
其他构造和制造工艺与上述其他构造和制造工艺重复,因此省略其详细描述。
在上述的根据本公开的扇出型半导体封装件中,可开发毫米波天线集成RFIC产品,可开发毫米波天线/滤波器/RFIC集成封装模块,可确保毫米波天线的稳定的天线辐射特性,可仅通过封装件本身保持天线辐射特性以保持对主PCB的周围变化的稳健性,可减小贴片天线图案和接地平面之间的误差以确保稳定的性能,可确保稳定的性能而不论封装件的底表面是否被污染,可对每个产品应用选择性结构,从RFIC产生的热可有效地散发到主PCB以改善RF性能从而增强散热特性、确保低的损耗特性等,具有高介电常数的材料可用作芯层的材料以减小天线的尺寸并且因此减小封装件的整体尺寸,可通过盲腔结构和堆叠型封装模块提供与现有的封装件相比具有显著的减小的尺寸的封装件,具有高介电常数的材料可用作天线部的材料以减小天线的尺寸,具有低介电常数的材料可选择性地用作底部封装件的材料以减小馈线的损耗。
如以上所阐述的,根据本公开中的示例性实施例,可提供一种扇出型半导体封装件,在该扇出型半导体封装件中,可通过显著地减小半导体芯片和天线图案之间的距离而防止信号传输的损耗,可在单个封装件中确保稳定的天线性能,可减小封装件的整体尺寸,并且可简化工艺。
虽然以上已经示出和描述了示例性实施例,但对本领域技术人员来说将明显的是,在不脱离由所附权利要求限定的本发明的范围的情况下,可进行修改和变型。
Claims (20)
1.一种扇出型半导体封装件,包括:
芯构件,包括多个绝缘层和多个布线层并且具有贯穿所述多个绝缘层的一部分的盲腔;
半导体芯片,设置在所述盲腔中并且具有有效表面和与所述有效表面背对的无效表面,所述有效表面上设置有连接焊盘;
包封剂,包封所述芯构件的至少部分和所述半导体芯片的所述有效表面的至少部分并且填充所述盲腔的至少部分;及
连接构件,设置在所述芯构件和所述半导体芯片的所述有效表面上并且包括重新分布层,所述重新分布层连接到所述连接焊盘,
其中,所述多个布线层包括天线图案和接地图案,
所述天线图案和所述接地图案设置在不同的水平面上,并且
所述天线图案通过所述重新分布层连接到所述连接焊盘,并且
其中,所述多个布线层还包括屏障图案,所述屏障图案的一部分通过所述盲腔从所述多个绝缘层的所述一部分暴露,并且所述半导体芯片的所述无效表面附着到所述屏障图案的被暴露的所述一部分。
2.根据权利要求1所述的扇出型半导体封装件,其中,所述多个布线层还包括滤波器图案,并且
所述天线图案按照信号方式通过所述滤波器图案和所述重新分布层连接到所述连接焊盘。
3.根据权利要求1所述的扇出型半导体封装件,其中,所述芯构件包括:第一绝缘层;第一布线层,设置在所述第一绝缘层的第一表面上;第二布线层,设置在所述第一绝缘层的第二表面上;第一过孔,贯穿所述第一绝缘层并且使所述第一布线层和所述第二布线层彼此连接;第二绝缘层,设置在所述第一绝缘层的所述第一表面上并且覆盖所述第一布线层;第三布线层,设置在所述第二绝缘层上;及第二过孔,贯穿所述第二绝缘层并且使所述第一布线层和所述第三布线层彼此连接,
所述第一布线层包括所述接地图案和所述屏障图案,
所述第三布线层包括所述天线图案,并且
所述盲腔贯穿所述第一绝缘层。
4.根据权利要求3所述的扇出型半导体封装件,其中,所述第二布线层包括滤波器图案,并且
所述天线图案按照信号方式通过所述滤波器图案和所述重新分布层连接到所述连接焊盘。
5.根据权利要求3所述的扇出型半导体封装件,其中,所述屏障图案用作所述接地图案。
6.根据权利要求3所述的扇出型半导体封装件,其中,所述第二绝缘层的介电质的介电常数大于所述第一绝缘层的介电质的介电常数。
7.根据权利要求1所述的扇出型半导体封装件,其中,所述芯构件包括:第一绝缘层;第一布线层,设置在所述第一绝缘层的第一表面上;第二布线层,设置在所述第一绝缘层的第二表面上;第一过孔,贯穿所述第一绝缘层并且使所述第一布线层和所述第二布线层彼此连接;第二绝缘层,设置在所述第一绝缘层的所述第一表面上并且覆盖所述第一布线层;第三布线层,设置在所述第二绝缘层上;第二过孔,贯穿所述第二绝缘层并且使所述第一布线层和所述第三布线层彼此连接;第三绝缘层,设置在所述第二绝缘层上并且覆盖所述第三布线层;第四布线层,设置在所述第三绝缘层上;及第三过孔,贯穿所述第三绝缘层并且使所述第三布线层和所述第四布线层彼此连接,
第三布线层包括所述接地图案,并且
所述第四布线层包括所述天线图案。
8.根据权利要求7所述的扇出型半导体封装件,其中,所述第一布线层和所述第二布线层中的至少一者包括滤波器图案,并且
所述天线图案按照信号方式通过所述滤波器图案和所述重新分布层连接到所述连接焊盘。
9.根据权利要求7所述的扇出型半导体封装件,其中,所述第一布线层包括所述屏障图案,并且
所述盲腔贯穿所述第一绝缘层。
10.根据权利要求7所述的扇出型半导体封装件,其中,所述第三布线层包括所述屏障图案,并且
所述盲腔贯穿所述第一绝缘层和所述第二绝缘层。
11.根据权利要求10所述的扇出型半导体封装件,其中,所述屏障图案用作所述接地图案。
12.根据权利要求7所述的扇出型半导体封装件,其中,所述第三绝缘层的介电质的介电常数大于所述第一绝缘层的介电质的介电常数。
13.根据权利要求1所述的扇出型半导体封装件,其中,所述屏障图案为金属板。
14.根据权利要求1所述的扇出型半导体封装件,其中,所述屏障图案的与所述多个绝缘层中的一者接触的边缘区域的厚度大于所述屏障图案的通过所述盲腔从所述多个绝缘层的所述一部分暴露的区域的厚度。
15.根据权利要求1所述的扇出型半导体封装件,其中,所述天线图案包括发送天线图案和接收天线图案。
16.根据权利要求1所述的扇出型半导体封装件,其中,所述盲腔的壁相对于所述多个布线层中的一者具有锐角的斜度。
17.根据权利要求1所述的扇出型半导体封装件,其中,所述天线图案和所述接地图案在所述多个绝缘层的堆叠方向上彼此至少部分地叠置。
18.根据权利要求1所述的扇出型半导体封装件,其中,在所述多个绝缘层中,直接设置有所述天线图案的所述绝缘层具有最大的介电常数。
19.一种扇出型半导体封装件,包括:
芯构件,包括多个绝缘层和多个布线层并且具有贯穿所述多个绝缘层的一部分的盲腔;
半导体芯片,设置在所述盲腔中并且具有有效表面和与所述有效表面背对的无效表面,所述有效表面上设置有连接焊盘;
包封剂,包封所述芯构件的至少部分和所述半导体芯片的所述有效表面的至少部分并且填充所述盲腔的至少部分;及
连接构件,设置在所述芯构件和所述半导体芯片的所述有效表面上并且包括重新分布层,所述重新分布层连接到所述连接焊盘,
其中,所述多个布线层包括天线图案和接地图案,
所述天线图案和所述接地图案设置在不同的水平面上,
所述天线图案通过所述重新分布层连接到所述连接焊盘,并且
其中,所述盲腔的壁相对于所述多个布线层中的一者具有锐角的斜度。
20.一种扇出型半导体封装件,包括:
芯构件,包括多个绝缘层和多个布线层并且具有贯穿所述多个绝缘层的一部分的盲腔;
半导体芯片,设置在所述盲腔中并且具有有效表面和与所述有效表面背对的无效表面,所述有效表面上设置有连接焊盘;
包封剂,包封所述芯构件的至少部分和所述半导体芯片的所述有效表面的至少部分并且填充所述盲腔的至少部分;及
连接构件,设置在所述芯构件和所述半导体芯片的所述有效表面上并且包括重新分布层,所述重新分布层连接到所述连接焊盘,
其中,所述多个布线层包括天线图案和接地图案,
所述天线图案和所述接地图案设置在不同的水平面上,
所述天线图案通过所述重新分布层连接到所述连接焊盘,并且
其中,在所述多个绝缘层中,直接设置有所述天线图案的所述绝缘层具有最大的介电常数。
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