CN108352300B - 半导体装置处理方法、系统及设备 - Google Patents

半导体装置处理方法、系统及设备 Download PDF

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CN108352300B
CN108352300B CN201680065565.5A CN201680065565A CN108352300B CN 108352300 B CN108352300 B CN 108352300B CN 201680065565 A CN201680065565 A CN 201680065565A CN 108352300 B CN108352300 B CN 108352300B
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cavity
atomic layer
layer deposition
semiconductor device
processing method
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CN108352300A (zh
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寇迪斯·勒施基斯
史帝文·维哈佛贝可
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Applied Materials Inc
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Applied Materials Inc
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks

Abstract

一种半导体装置处理方法、系统及设备。所述方法可包括：在层中提供空腔；将高能通量引导到所述空腔的底表面；执行将所述空腔暴露到含水分的环境；以及利用原子层沉积(ALD)工艺将填充材料引入所述空腔中，其中所述填充材料相对于所述空腔的侧壁选择性地沉积在所述空腔的底表面上。

Description

半导体装置处理方法、系统及设备
相关申请
本申请主张在2015年11月13日提出申请且名称为“利用选择性表面修改填充结构的技术(TECHNIQUES FOR FILLING A STRUCTURE USING SELECTIVE SURFACEMODIFICATION)”的美国临时专利申请第62/255,017号的优先权，所述美国临时专利申请全文并入本申请供参考。
技术领域
本发明实施例涉及处理装置结构，且更具体来说涉及半导体装置处理方法、系统及设备。
背景技术
当前，装置制作(例如半导体装置制作)可能需要对例如沟槽、孔或其他结构等小空腔进行填充。可利用金属材料、绝缘体材料或其他材料来填充此类空腔。由于此类空腔的尺寸按比例缩放到较小的大小，因此填充空腔的能力变得更具挑战性。举例来说，对沟槽或通孔结构进行填充可能在给定结构的纵横比(深度/宽度)高时尤其困难。在一些实例中，沟槽可具有大于1(尤其是大于2)的纵横比。在各种已知的填充沟槽的沉积技术中，当向沟槽中引入填充材料时，可能会在多个被暴露表面(包括沟槽的底部以及沟槽侧壁)上发生填充材料的沉积。这种类型的沉积可能导致悬垂(overhang)及在沟槽内形成埋孔(buriedhole)，从而致使所得装置结构具有所不期望的性质。
鉴于这些及其他考虑因素，提供本公开。
发明内容
在一个实施例中，一种装置处理方法可包括：在层中提供空腔；将高能通量(energetic flux)引导到所述空腔的底表面；执行将所述空腔暴露到含水分的环境；以及利用原子层沉积(atomic layer deposition，ALD)工艺将填充材料引入所述空腔中。所述填充材料可相对于所述空腔的侧壁选择性地沉积在所述空腔的所述底表面上。
在另一实施例中，一种系统可包括传送腔室(transfer chamber)，其中所述传送腔室被安排成在多个位置之间输送衬底。所述系统可包括高能通量腔室，其中所述高能通量腔室耦合到所述传送腔室以接纳所述衬底，其中所述高能通量腔室以定向方式(directional fashion)将高能通量引导到所述衬底。所述系统还可包括水分腔室(moisture chamber)，所述水分腔室耦合到所述传送腔室且为所述衬底提供H2O环境。所述系统还可包括原子层沉积腔室，所述原子层沉积腔室耦合到所述传送腔室且向所述衬底提供第一反应剂及第二反应剂，所述第一反应剂及所述第二反应剂形成填充材料的至少一个单层。所述系统可包括刻蚀腔室，所述刻蚀腔室耦合到所述传送腔室且将刻蚀剂引导到所述衬底以对所述填充材料进行刻蚀。
在再一实施例中，一种处理设备可包括：处理腔室，用于容纳衬底；高能通量来源，所述高能通量来源以定向方式向所述衬底提供高能通量；及水分来源，所述水分来源向所述衬底提供H2O；以及原子层沉积来源。所述原子层沉积来源可向所述衬底提供至少两种物质，以利用原子层沉积工艺将填充材料沉积在所述衬底上。所述高能通量来源、所述水分来源及所述原子层沉积来源可耦合到所述处理腔室。
附图说明
图1A到图1D示出根据本公开的实施例的一种方法中所涉及的示例性操作的示意图。
图2A到图2C示出根据本公开的其他实施例的示例性操作的示意图。
图3A到图3C示出根据本公开的额外实施例的示例性操作的示意图。
图4示出在原子层沉积工艺之前暴露到高能通量情况下衬底上的膜生长与在原子层沉积工艺之前不暴露到高能通量情况下衬底上的膜生长的傅立叶变换红外光谱(Fourier transform Infrared spectra)比较结果。
图5是示出在执行原子层沉积之前在暴露到高能通量情况下与在不暴露到高能通量情况下利用原子层沉积在衬底上进行膜生长的比较的复合图。
图6呈现根据本公开的实施例的示例性工艺流程的示意图。
图7呈现根据本公开的实施例的示例性系统的示意图。
图8呈现根据本公开的实施例的示例性设备的示意图。
附图未必按比例绘制。附图只是表示图，而并非旨在描绘本公开的具体参数。附图旨在示出本公开的示例性实施例，且因此不应被视为对范围进行限制。在附图中，相同编号表示相同元件。
此外，为使说明清晰起见，一些图中的某些元件可被省略或不按比例示出。为使说明清晰起见，剖视图可呈“切片”或“近视”剖视图的形式，以省略原本会在“真实的”剖视图中可见的某些背景线。此外，为清晰起见，可在某些附图中省略一些参考编号。
具体实施方式
现在将参照其中示出一些实施例的附图在下文中更充分地阐述本发明实施例。本公开的主题可被实施为诸多不同形式，而不应被视为仅限于本文所述的实施例。提供这些实施例是为了使本公开内容将透彻及完整，且将向所属领域中的技术人员充分传达所述主题的范围。在附图中，相同编号自始至终指代相同元件。
本文所述的实施例提供新颖的装置处理，包括用于对衬底中的空腔(例如沟槽或通孔)进行填充的处理。在各种实施例中，提供各种技术来改善对包括其中纵横比大于1的高纵横比空腔在内的空腔的沟槽填充或通孔填充。所述实施例在此上下文中不受限制。
图1A到图1D示出根据本公开的实施例的一种填充空腔的方法中所涉及的示例性操作的示意图。在各种实施例中，可在例如衬底基部或设置在衬底基部上的层等结构中提供空腔。衬底基部可例如为例如形成衬底的主要部分的半导体材料、绝缘体材料或其他材料等材料。可在衬底基部上设置任何数量的层。
现在转向图1A，示出被安排在结构(被示出为层106)内的空腔100。在各种实施例中，层106可表示衬底基部或可为安排在衬底(图中未示出)内或衬底上的层。在一些实施例中，层106可由氧化硅、氮化硅或碳氧化硅构成。所述实施例在此上下文中不受限制。
根据本公开的各种实施例，空腔100可具有不同的结构。在一些实施例中，空腔100可具有其中所述空腔在根据所示笛卡尔座标系统(Cartesian coordinate system)的X-Y平面内具有椭圆形或圆形形状的通孔结构。在这些实施例中，侧壁104可能只是用于界定空腔100的侧面的一个侧壁。在其他实施例中，空腔具有其中沟槽包括一对相对的侧壁(被示出为侧壁104)的沟槽结构。另外，此种沟槽可包括相对的端壁(图中未示出)。空腔100还可包括底表面102，如图所示。在一些实施例中，空腔在X-Y平面内可具有复杂的形状(例如要填充的任何目标沟槽图案)。
根据各种实施例，空腔100的侧壁及底表面可被表面物质108(例如氧)封端(terminated)。如下所详述，设置在空腔100的表面上的表面物质108可被配置成与沉积工艺中所提供的某些反应性物质发生反应，以有利于目标材料(例如绝缘体或金属)的沉积。
现在转向图1B，示出其中将高能通量112引导到空腔100的底表面102的操作。在各种实施例中，可将高能通量112设置在高能通量腔室中，其中高能通量112可为离子、电子或光子或者其组合。可以定向方式将高能通量112提供到空腔100的底表面102，其中底表面102相比于侧壁104会优先受到撞击。在其中离子构成高能通量112的实施例中，可以准直方式将所述离子朝向底表面102引导。在特定实施例中，离子可以含有具有平行轨迹的离子的离子束形式被引导。举例来说，离子可被设置成具有与侧壁104平行的轨迹。在其中位于沟槽的相对侧上的侧壁104大体彼此平行设置的情况下，可平行于侧壁104引导平行的离子束以冲撞底表面102而不冲撞侧壁104。以此种方式，离子或其他高能通量可选择性地改变底表面102而不改变侧壁104。根据一些实施例，在图1B所示操作中，可利用能够提供准直离子的已知的束线离子植入机、紧凑式离子束来源、等离子体来源或其他已知来源来提供高能离子。
根据各种实施例，高能通量的能量可被安排成提供足以改变被暴露到高能通量的空腔100的表面的能量，以使得所述表面更易于形成氢氧化物(OH)封端(termination)。在利用离子改变空腔的表面的实施例中，可对离子的离子能量进行定制以提供足够的能量使得被撞击表面易于形成氢氧化物，同时不会使被撞击表面受到过度损坏。在一些实施例中，被提供作为高能通量112的离子的离子能量可介于5eV与500eV之间。在一些实施例中，离子可以惰性气体离子(包括Ar离子)的形式提供，或可为反应性离子(包括O2离子)。在其中使用光子作为高能通量112的实施例中，光子可以处于紫外线(ultraviolet，UV)能量范围内的紫外线光子或者处于真空紫外线(vacuum ultraviolet，VUV)能量范围内的真空紫外线光子形式提供。在特定实施例中，用作高能通量112的光子的光子能量可介于7eV到10eV的范围内。
根据本公开的实施例，可将空腔100暴露到含水分(H2O)的环境且一起暴露到高能通量112。在各种实施例中，含水分的环境可在提供高能通量112之后提供。现在转向图1C，示出在暴露到高能通量112之后以及在暴露到含水分的环境之后空腔100的情境。在此实例中，高能通量112已被选择性地引导到底表面102而不撞击侧壁104，如图1B所示。如图所示，底表面102现在可被OH基团封端，而侧壁104不会被OH基团封端。这种差异可引起利用高能通量112以及H2O来改变沟槽底部的结果。当侧壁104在将空腔暴露到含水分的环境期间暴露到H2O时，未被高能通量112改变的侧壁104不会与H2O发生反应而在其表面上形成OH反应产物。
在底表面102处选择性地形成OH封端表面之后，根据本公开的实施例，可将空腔100暴露到沉积工艺(例如原子层沉积(ALD))。原子层沉积一般会涉及依序暴露到两种或更多种反应剂以沉积给定单层材料。在各种实施例中，可执行原子层沉积工艺来选择性地沉积例如氧化物、氮化物或金属(例如Ta)等材料。在一些实施例中，氧化物可为高介电常数材料，其中高介电常数材料的实例包括Al2O3、HfO2、Ta2O5及其中介电常数大于SiO2的介电常数的其他材料。所述实施例在此上下文中不受限制。
根据本公开的实施例，可相对于侧壁104选择性地在底表面102上促进利用原子层沉积工艺对填充材料进行沉积。具体来说，以某些材料为例，底表面102的OH-封端可促进含铝的反应剂、含铪的反应剂或含钽的反应剂的沉积。在不同的实例中，此OH-封端可相应地使Al2O3、HfO2、Ta2O5或钽金属在底表面102而非侧壁104上选择性地生长。在各种实施例中，给定原子层沉积工艺可循环地执行以产生给定材料的自下而上填充，如由图1D中示出的填充材料120所示。换句话说，在改善平行于底表面102的层生长的同时，一般可抑制从侧壁104的生长。此生长即使对于高纵横比沟槽或通孔仍可有助于避免夹断(pinch-off)。
为了进一步阐释，图2A到图2C示出根据本发明实施例的选择性原子层沉积的序列。尽管示出了平坦的衬底构型，然而图2A到图2C的工艺也可用于图1A到图1C所示的上述程序。在图2A中，提供介电衬底200。介电衬底200在一些实例中可表示空腔100的表面。换句话说，介电衬底200的平坦的表面可能存在与空腔100的表面相同的材料。在图2B中，选择性地改变介电衬底200的一部分202，以在所述部分202上产生官能基204，而不在部分206上产生官能基204。以此种方式，可在部分202上促进选择性原子层沉积，其中原子层沉积工艺因存在官能基204而得到改善。如图2C所示，随后可通过原子层沉积在部分202上沉积层208，而没有层在部分206上生长。
现在转向图3A到图3C，示出根据本公开的实施例的图2A到图2C的工艺的具体实作方式。在此实例中，在图3A处，提供碳氧化硅衬底300(例如BDIIx)。在图3B中，提供掩模302以掩蔽碳氧化硅衬底300的一部分304。同时，将高能通量308引导到碳氧化硅衬底300的未掩蔽部分306。在各种实施例中，产生高能通量308的高能通量腔室可为紫外线腔室，其中紫外线腔室包含紫外线辐射源。在一些实施例中，举例来说，紫外线辐射源可发射波长处于150nm与200nm之间的辐射。在此特定实例中，高能通量可为172nm的紫外线辐射(NBUV)。在暴露到HfO2原子层沉积工艺之前，也将部分304及部分306暴露到含水分的环境。因此，通过将整个碳氧化硅衬底300暴露到随后的原子层沉积工艺来选择性地生长HfO2层310。如图所示，HfO2层310只在未掩蔽部分306上生长而不在部分304上生长。
图4示出在执行原子层沉积工艺之前暴露到高能通量的区中碳氧化硅衬底300上的膜生长与在执行原子层沉积工艺之前不暴露到高能通量的区中碳氧化硅衬底300上的膜生长的傅立叶变换红外光谱比较结果。如图所示，在未掩蔽部分306中截取的光谱402在3400的波数范围内显示出吸收峰，即膜形成的特征。在部分304中截取的光谱404未显示出表示膜形成的峰。
根据本公开的额外的实施例，可通过执行原子层沉积与刻蚀的组合来促进给定材料在目标表面上的选择性沉积。在一些实施例中，原子层沉积及刻蚀(例如，HF刻蚀)可循环地执行。所述实施例在此上下文中不受限制。图5是示出在执行原子层沉积之前暴露到紫外线光子通量情况下与在执行原子层沉积之前不暴露到紫外线光子通量情况下利用原子层沉积在衬底上进行膜生长的比较(即比较衬底的多个区)的复合图。具体来说，示出在碳氧化硅上对HfO2进行选择性原子层沉积的实例。图5的曲线示出沉积在衬底样本上的氧化铪的量随着所执行的原子层沉积循环的数量而变化。氧化铪的量是由用于测量给定样本的X射线光电子分光光谱(X-ray photoelectron spectroscopy，XPS)信号的强度来表示。曲线502表示在原子层沉积之前被暴露到紫外线通量及水分的衬底部分上所沉积的氧化铪的量，其被示出为随着原子层沉积循环的数量而变化。曲线504表示在原子层沉积之前被暴露到水分但不被暴露到紫外线通量的衬底部分上所沉积的氧化铪。在此实验中，在执行刻蚀工艺之前执行初始一系列20个原子层沉积循环。如图所示，氧化铪的量在上述两种情况下随着原子层沉积循环的数量而增加，而经紫外线暴露的衬底部分中的沉积速率可能是未暴露衬底部分中的沉积速率的三倍到四倍。
在20个原子层沉积循环之后，对衬底的经受紫外线通量的被暴露区以及未暴露区进行刻蚀，其中所述刻蚀会移除目标量的氧化铪材料。所述两个样本中在刻蚀之后残留的氧化铪的相应量是由点506及点508示出。如图所示，在刻蚀之后没有氧化铪残留在所述未暴露部分上，而氧化铪层残留在所述被暴露部分上。随后，再执行一系列20个原子层沉积循环，然后进行第二刻蚀。在此工艺结束时，没有氧化铪残留在所述未暴露部分上，而氧化铪残留在所述被暴露部分上。此结果是通过附图来确认，附图示出在各种处理阶段中的经紫外线暴露的样本及未暴露样本的剖视电子显微图。如右上部的附图所示，在此实例中在40个原子层沉积循环之后沉积了近似3nm的氧化铪层。
在平坦的衬底上执行的图5的上述实例是示例性的，且可用于改善自下而上的沟槽填充或通孔填充工艺。举例来说，可通过以下方式来改善对空腔的自下而上填充：将底表面选择性地暴露到高能通量且一起暴露到水分，随后将填充材料原子层沉积到空腔中，且在原子层沉积工艺之后对填充材料进行刻蚀。以此种方式，可移除在原子层沉积程序之后在沟槽的侧壁上发生的任何不需要的沉积。此移除可有利于改善自下而上的沟槽填充工艺，从而避免会造成空隙形成或其他不需要的微结构的生长类型。
举例来说，为了进行说明，在一种情境中，在执行20个原子层沉积循环之后，一般可自下而上地在沟槽中沉积4nm厚的填充材料层，如图1D所示。随后，可执行刻蚀以移除0.5nm的填充材料。此刻蚀可有效地从在沟槽中的填充材料的表面上方被暴露出的侧壁移除任何残余填充材料。换句话说，在刻蚀工艺之后，没有填充材料可存在于位于填充材料的表面上方的侧壁的被暴露区上。所述刻蚀也可使填充材料凹陷0.5nm。随后，可执行额外的原子层沉积工艺以继续进行自下而上的沟槽填充工艺。此程序可根据需要进行重复，直到沟槽被完全填充或填充到目标水平。
图6呈现根据本公开的实施例的示例性工艺流程600的示意图。在方框602中，执行在层中提供空腔的操作。在方框604中，将高能通量引导到空腔的底表面。在各种实施例中，高能离子通量可包括具有目标离子能量(例如500eV或小于500eV的离子能量)的离子。
在方框606中，执行将空腔暴露到含水分的环境。根据各种实施例，可在方框604之后进行暴露到含水分的环境。
在方框608中，利用原子层沉积工艺将填充材料引入空腔中，其中填充材料相对于空腔的侧壁选择性地沉积在空腔的底表面上。在各种实施例中，填充材料可为氧化物(例如高介电常数材料)或金属。
在方框610中，执行刻蚀工艺。刻蚀工艺可被安排成移除预定量的填充材料。在决定方框612中，对填充工艺是否完成作出判断。如果填充工艺完成，则流程结束。如果填充工艺未完成，则流程返回到方框608。
图7呈现根据本公开的实施例的示例性系统(被示出为系统700)的俯视平面图(X-Y平面)。系统700可用于执行根据本文所公开的实施例的填充工艺。系统700可被配置成集群工具，包括装载锁(loadlock)702以及传送腔室704以将衬底720输送到各种处理腔室以及在各种处理腔室之间输送衬底720。传送腔室704及处理腔室可耦合到排空设备(例如已知的泵抽系统(图中未示出))以将传送腔室704及下文所述的其他处理腔室维持在真空条件下或维持在受控的环境条件下。因此，衬底720可在各种处理腔室与传送腔室704之间输送而不会暴露到周围环境。系统700可包括耦合到传送腔室704的等离子体浸没腔室706，其中衬底720被暴露到被平行地引导到衬底720中的空腔中的离子。系统700还可包括水分腔室708，水分腔室708耦合到传送腔室704且提供向H2O的受控暴露。系统700还可包括原子层沉积腔室(被示出为原子层沉积腔室710)，所述原子层沉积腔室耦合到传送腔室704且根据已知的设备被安排成将衬底720暴露到给定材料系统(例如(举例来说)Al2O3、HfO2、Ta2O5或钽金属)的原子层沉积工艺。原子层沉积腔室710可例如耦合到要可控地引导到原子层沉积腔室710中的蒸气物质的两个或更多个来源以执行原子层沉积工艺。系统700还可包括耦合到传送腔室704的刻蚀腔室712，其中衬底720可在刻蚀腔室712内暴露到刻蚀剂(例如HF或其他刻蚀剂)以移除预定量的在填充空腔期间的材料。系统700可另外包括紫外线腔室714，紫外线腔室714耦合到传送腔室704且将处于预定波长范围的紫外线辐射引导到衬底720。举例来说，并非在等离子体浸没腔室706中对衬底720进行处理，衬底720可被传送到紫外线腔室714中，其中紫外线辐射可以受控的方式被引导到衬底720中的空腔的底部，如图1B大体所示。衬底720因此可在系统700的各种处理腔室之间传送，而不会暴露到外部环境。在特定实施例中，紫外线腔室714可包含高能灯，所述高能灯产生峰值能量处于172nm范围内且能量范围介于近似7eV到10eV之间的辐射。
系统700还可包括控制器730以在系统700的不同处理腔室之间引导及协调衬底720的输送及处理。举例来说，控制器730可包括软件与硬件的任何组合(包括逻辑、存储器及用户介面)以控制衬底在系统700的多个处理腔室(包括等离子体浸没腔室706、水分腔室708、原子层沉积腔室710及刻蚀腔室712)之间的处理。作为一个实例，控制器730可将衬底720引导成根据填充空腔的方式(recipe)在循环工艺中在系统700的各种处理腔室之间传送。循环工艺可使衬底720传送到给定处理腔室中以及传送出给定处理腔室多次，且可使衬底720在不同处理腔室之间传送多次以完成空腔填充工艺。在处理方式的一个具体实例中，可将衬底720输送到紫外线腔室714中以第一次暴露到高能光子从而改变衬底720内的空腔的底表面。随后可将衬底720经由传送腔室704输送到水分腔室708以进行第二次暴露，其中空腔的底表面被OH封端，如以上关于图1C所述。随后，可将衬底720输送到原子层沉积腔室710以进行初始原子层沉积处理程序，其中衬底720被暴露到第一数量个原子层沉积循环。第一数量个原子层沉积循环可为被安排成将填充材料在空腔中沉积到预定厚度的预定数量个原子层沉积循环。在初始原子层沉积处理程序之后，可将衬底720输送到刻蚀腔室712以将填充材料刻蚀到预定量。对填充材料的此种刻蚀可使得填充材料从未直接暴露到紫外线辐射的不需要的表面完全移除，其中填充材料的生长速率可低得多，如以上关于图5所述。然后可将衬底传送回到原子层沉积腔室710以进行额外数量个原子层沉积循环。举例来说，可执行第二原子层沉积处理程序，其中衬底720被暴露到第二数量个原子层沉积循环以增大空腔中的填充材料的厚度。在此第二原子层沉积处理程序之后可将衬底720传送回到刻蚀腔室712以进行第二刻蚀工艺。原子层沉积腔室710与刻蚀腔室712之间的循环可根据优化对空腔的自下而上填充的预定方式来执行。在对衬底720的整个处理过程中，在进入装载锁702中之后，可对衬底720进行处理而不暴露到系统700外部的环境。
尽管根据本公开的实施例系统700可提供用于执行空腔填充工艺的涉及集群工具(cluster tool)构型的一种方式，然而在其他实施例中，可利用不同的设备来执行空腔填充工艺。举例来说，在一些实施例中，执行空腔填充工艺的处理设备可包括较少的处理腔室，例如仅一个处理腔室。在一个实施例中，如图8所示，设备800可包括用于容纳衬底(例如衬底720)的处理腔室802。设备800还可包括以定向方式向衬底提供高能通量的高能通量来源804以及水分来源806，其中水分来源806向衬底720提供H2O。设备800还可包括原子层沉积来源808，其中原子层沉积来源808向衬底提供至少两种物质以利用原子层沉积工艺将填充材料沉积在衬底720上。原子层沉积来源具体来说可包括多种气体来源或蒸气来源，其中给定气体来源或蒸气来源提供原子层沉积工艺的一个要素。在一些实例中，高能通量来源804、水分来源806及原子层沉积来源808可全部耦合到处理腔室802以用于要在其中执行的不同处理。
本发明实施例通过利于仅在目标表面(例如沟槽的底部)上的生长来提供填充窄的沟槽及具有高纵横比的沟槽且无埋空隙(buried void)的优点。另外，本发明实施例还提供缩放到较小尺寸的可缩放性的另一优点，这是因为空腔(例如沟槽)可自下而上进行填充。
本公开的范围不受本文所述的具体实施例限制。事实上，通过前述说明及附图，除本文所述的本公开的实施例以外的其他各种实施例及修改将对所属领域中的一般技术人员显而易见。因此，此类其他实施例及修改旨在落在本公开的范围内。此外，本文已出于特定目的在特定环境中的特定实作方式的上下文中阐述了本公开。所属领域中的一般技术人员将认识到其适用性并非仅限于此，且本公开可出于任何数量的目的在任何数量的环境中有益地实作。因此，以上所述的权利要求应根据本文所述的本公开的全部广度及精神来解释。

Claims (10)

1.一种半导体装置处理方法，其特征在于，包括：
在层中提供空腔；
将高能通量引导到所述空腔的底表面；
执行将所述空腔暴露到含水分的环境；以及
利用原子层沉积工艺将填充材料引入所述空腔中，其中所述填充材料相对于所述空腔的侧壁选择性地沉积在所述空腔的所述底表面上以完全填充所述空腔，其中所述侧壁及所述底表面包括相同的材料，其中所述侧壁垂直于所述底表面定向，且其中所述高能通量平行于所述侧壁定向且不撞击所述空腔的所述侧壁。
2.根据权利要求1所述的半导体装置处理方法，其中所述高能通量包括离子，所述离子具有平行的轨迹。
3.根据权利要求2所述的半导体装置处理方法，其中所述离子包含平行于所述空腔的所述侧壁进行取向的轨迹。
4.根据权利要求2所述的半导体装置处理方法，其中所述离子包含500eV或小于500eV的离子能量。
5.根据权利要求1所述的半导体装置处理方法，其中所述底表面在暴露之后形成OH封端表面，且其中所述侧壁在暴露之后不形成OH封端表面。
6.根据权利要求1所述的半导体装置处理方法，其中所述填充材料是高介电常数材料。
7.根据权利要求1所述的半导体装置处理方法，其中所述填充材料是金属。
8.根据权利要求1所述的半导体装置处理方法，其中所述空腔设置在包含氧化硅、氮化硅或碳氧化硅的材料中。
9.根据权利要求1所述的半导体装置处理方法，其中所述高能通量包括真空紫外线光子或电子。
10.根据权利要求1所述的半导体装置处理方法，其中所述原子层沉积工艺被执行预定数量个原子层沉积循环，所述装置处理方法还包括在所述预定数量个原子层沉积循环之后执行刻蚀工艺，所述刻蚀工艺移除预定量的所述填充材料。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102582496B1 (ko) * 2018-05-28 2023-09-26 가부시키가이샤 코쿠사이 엘렉트릭 반도체 장치의 제조 방법, 기판 처리 장치 및 기록 매체
US10707100B2 (en) 2018-06-07 2020-07-07 Tokyo Electron Limited Processing method and plasma processing apparatus
US10916420B2 (en) 2018-06-07 2021-02-09 Tokyo Electron Limited Processing method and plasma processing apparatus
CN110783187B (zh) 2018-07-25 2024-04-19 东京毅力科创株式会社 等离子体处理方法和等离子体处理装置
CN110777361B (zh) 2018-07-26 2023-08-01 东京毅力科创株式会社 等离子体处理方法和等离子体处理装置
WO2020061417A1 (en) * 2018-09-21 2020-03-26 Applied Materials, Inc. Gap-fill with aluminum-containing films
JP2020136677A (ja) * 2019-02-20 2020-08-31 エーエスエム・アイピー・ホールディング・ベー・フェー 基材表面内に形成された凹部を充填するための周期的堆積方法および装置
JP6783888B2 (ja) * 2019-03-15 2020-11-11 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置及び記録媒体
JP2022063748A (ja) * 2020-10-12 2022-04-22 東京エレクトロン株式会社 埋め込み方法及び成膜装置
TW202237882A (zh) * 2021-03-02 2022-10-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 用於形成包含釩及氧的層之方法及系統

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5342792A (en) * 1986-03-07 1994-08-30 Canon Kabushiki Kaisha Method of manufacturing semiconductor memory element
TW422890B (en) * 1998-02-24 2001-02-21 Applied Materials Inc Oxygen enhancement of ion metal plasma (IMP) sputter deposited barrier layers
CN1397993A (zh) * 2001-06-19 2003-02-19 联华电子股份有限公司 栓塞金属层的形成方法
CN101061253A (zh) * 2004-11-22 2007-10-24 应用材料股份有限公司 使用批式制程腔室的基材处理装置
CN101553597A (zh) * 2005-09-21 2009-10-07 应用材料股份有限公司 批次处理原子层沉积反应器的处理制程
US7625820B1 (en) * 2006-06-21 2009-12-01 Novellus Systems, Inc. Method of selective coverage of high aspect ratio structures with a conformal film
CN103184430A (zh) * 2011-12-27 2013-07-03 东京毅力科创株式会社 成膜方法
CN104517892A (zh) * 2013-09-30 2015-04-15 朗姆研究公司 使用复合peald和pecvd方法的可变深宽比特征的间隙填充

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US651382A (en) * 1898-10-14 1900-06-12 Simon E Pettee Mail-canceling machine.
JPH0233153A (ja) * 1988-07-22 1990-02-02 Toshiba Corp 半導体装置の製造方法
US6228720B1 (en) * 1999-02-23 2001-05-08 Matsushita Electric Industrial Co., Ltd. Method for making insulated-gate semiconductor element
US6391785B1 (en) * 1999-08-24 2002-05-21 Interuniversitair Microelektronica Centrum (Imec) Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
US6300219B1 (en) * 1999-08-30 2001-10-09 Micron Technology, Inc. Method of forming trench isolation regions
US6498091B1 (en) * 2000-11-01 2002-12-24 Applied Materials, Inc. Method of using a barrier sputter reactor to remove an underlying barrier layer
US6861334B2 (en) * 2001-06-21 2005-03-01 Asm International, N.V. Method of fabricating trench isolation structures for integrated circuits using atomic layer deposition
JP3477462B2 (ja) * 2001-08-21 2003-12-10 松下電器産業株式会社 半導体装置の製造方法
US6531382B1 (en) * 2002-05-08 2003-03-11 Taiwan Semiconductor Manufacturing Company Use of a capping layer to reduce particle evolution during sputter pre-clean procedures
JP2006505127A (ja) * 2002-10-29 2006-02-09 エーエスエム　インターナショナル　エヌ．ヴェー． 酸素架橋構造及び方法
DE10261466B4 (de) * 2002-12-31 2007-01-04 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer leitenden Barrierenschicht mit verbesserten Haft- und Widerstandseigenschaften
US7842605B1 (en) * 2003-04-11 2010-11-30 Novellus Systems, Inc. Atomic layer profiling of diffusion barrier and metal seed layers
CN100541736C (zh) * 2003-11-11 2009-09-16 东京毅力科创株式会社 基板处理方法
DE102004005702A1 (de) * 2004-02-05 2005-09-01 Siltronic Ag Halbleiterscheibe, Vorrichtung und Verfahren zur Herstellung der Halbleiterscheibe
JP2007019191A (ja) * 2005-07-06 2007-01-25 Fujitsu Ltd 半導体装置とその製造方法
TWI366876B (en) * 2006-05-30 2012-06-21 Applied Materials Inc A novel deposition-plasma cure cycle process to enhance film quality of silicon dioxide
CN101466864A (zh) * 2006-06-08 2009-06-24 东京毅力科创株式会社 成膜装置、成膜方法、计算机程序和存储介质
WO2008005773A2 (en) * 2006-07-03 2008-01-10 Applied Materials, Inc. Cluster tool for advanced front-end processing
US20080119057A1 (en) * 2006-11-20 2008-05-22 Applied Materials,Inc. Method of clustering sequential processing for a gate stack structure
DE102006056626A1 (de) * 2006-11-30 2008-06-05 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum selektiven Herstellen einer leitenden Barrierenschicht durch ALD
JP2008141125A (ja) * 2006-12-05 2008-06-19 Sekisui Chem Co Ltd 半導体装置及びその製造方法
US20080242097A1 (en) * 2007-03-28 2008-10-02 Tim Boescke Selective deposition method
JP4720808B2 (ja) * 2007-09-21 2011-07-13 セイコーエプソン株式会社 接着シート、接合方法および接合体
US7964504B1 (en) * 2008-02-29 2011-06-21 Novellus Systems, Inc. PVD-based metallization methods for fabrication of interconnections in semiconductor devices
US7943527B2 (en) * 2008-05-30 2011-05-17 The Board Of Trustees Of The University Of Illinois Surface preparation for thin film growth by enhanced nucleation
US7981763B1 (en) * 2008-08-15 2011-07-19 Novellus Systems, Inc. Atomic layer removal for high aspect ratio gapfill
KR20100093349A (ko) * 2009-02-16 2010-08-25 삼성전자주식회사 기상 박막 형성 방법 및 반도체 집적 회로 장치의 제조 방법
US8945305B2 (en) * 2010-08-31 2015-02-03 Micron Technology, Inc. Methods of selectively forming a material using parylene coating
CN103515207B (zh) * 2012-06-19 2016-08-10 中芯国际集成电路制造(上海)有限公司 氧化层、hkmg结构中界面层、mos晶体管形成方法及mos晶体管
US20140374907A1 (en) * 2012-06-21 2014-12-25 Applied Materials, Inc. Ultra-thin copper seed layer for electroplating into small features
US9040465B2 (en) * 2012-11-19 2015-05-26 Intermolecular, Inc. Dielectric doping using high productivity combinatorial methods
US9171960B2 (en) * 2013-01-25 2015-10-27 Qualcomm Mems Technologies, Inc. Metal oxide layer composition control by atomic layer deposition for thin film transistor
JP5931780B2 (ja) * 2013-03-06 2016-06-08 東京エレクトロン株式会社 選択エピタキシャル成長法および成膜装置
US9217201B2 (en) * 2013-03-15 2015-12-22 Applied Materials, Inc. Methods for forming layers on semiconductor substrates
CN105047600B (zh) * 2014-04-24 2019-01-18 台湾积体电路制造股份有限公司 半导体结构及其制造方法
US9997373B2 (en) * 2014-12-04 2018-06-12 Lam Research Corporation Technique to deposit sidewall passivation for high aspect ratio cylinder etch

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5342792A (en) * 1986-03-07 1994-08-30 Canon Kabushiki Kaisha Method of manufacturing semiconductor memory element
TW422890B (en) * 1998-02-24 2001-02-21 Applied Materials Inc Oxygen enhancement of ion metal plasma (IMP) sputter deposited barrier layers
CN1397993A (zh) * 2001-06-19 2003-02-19 联华电子股份有限公司 栓塞金属层的形成方法
CN101061253A (zh) * 2004-11-22 2007-10-24 应用材料股份有限公司 使用批式制程腔室的基材处理装置
CN101553597A (zh) * 2005-09-21 2009-10-07 应用材料股份有限公司 批次处理原子层沉积反应器的处理制程
US7625820B1 (en) * 2006-06-21 2009-12-01 Novellus Systems, Inc. Method of selective coverage of high aspect ratio structures with a conformal film
CN103184430A (zh) * 2011-12-27 2013-07-03 东京毅力科创株式会社 成膜方法
CN104517892A (zh) * 2013-09-30 2015-04-15 朗姆研究公司 使用复合peald和pecvd方法的可变深宽比特征的间隙填充

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
《Blocking the Lateral Film Growth at the Nanoscale in Area-Selective Atomic Layer Deposition》;Robin H. A. Ras et al;《Journal of the American Chemical Soc》;20080731;第130卷(第34期);正文全文 *
CVD金刚石薄膜衬底表面预处理技术进展;黄元盛等;《中国表面工程》;20010923(第03期);正文全文 *

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