CN107980172A - Vnand拉伸厚teos氧化物 - Google Patents

Vnand拉伸厚teos氧化物 Download PDF

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Publication number
CN107980172A
CN107980172A CN201680047305.5A CN201680047305A CN107980172A CN 107980172 A CN107980172 A CN 107980172A CN 201680047305 A CN201680047305 A CN 201680047305A CN 107980172 A CN107980172 A CN 107980172A
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Prior art keywords
oxide layer
layer
oxygen
angstroms
gas
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CN201680047305.5A
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CN107980172B (zh
Inventor
M·W·蒋
P·P·杰哈
韩新海
金柏涵
金相赫
朱明勋
朴亨珍
金伦宽
孙镇哲
S·格纳纳威路
M·G·库尔卡尼
S·巴录佳
M·K·莎莱扎
J·K·福斯特
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Applied Materials Inc
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Applied Materials Inc
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Abstract

本公开的实施例一般涉及一种用于形成介电膜堆栈的改进方法，该介电膜堆栈用于3D NAND结构中的层间电介质(ILD)层。在一个实施例中，该方法包括提供具有栅堆栈沉积于其上的基板，使用第一RF功率及第一处理气体在该栅堆栈的暴露表面上形成第一氧化层，第一处理气体包含TEOS气体与第一含氧气体，及使用第二RF功率与第二处理气体在该第一氧化层上形成第二氧化层，第二处理气体包含硅烷气体与第二含氧气体。

Description

VNAND拉伸厚TEOS氧化物
技术领域
本公开的实施例一般涉及用于沉积介电膜堆栈的改进方法和用作层间电介质(ILD)层的介电膜堆栈。
背景技术
随着制造越加致密的器件的持续压力，半导体器件工业正转换到三维(3D)存储器结构的使用。例如，NAND闪存已经从平面配置移动到垂直配置(VNAND)。这种垂直配置允许以显著更大的位密度来形成存储器器件。在制造3D半导体芯片的堆栈时，通常使用阶梯状(stair-like)结构以允许多个互连结构设置于其上，而形成高密度的垂直晶体管器件。层间电介质(ILD)可设置在互连层之间的阶梯状结构之上，以绝缘(isolate)设置在互连层中的导体层。然而，由于层间电介质与互连层之间的热膨胀差异可能导致的层间电介质中的物理应力，裂纹或缺陷常被引入半导体芯片中，而影响器件的整体性能。
因此，在本领域中，提供抑制在半导体芯片中裂纹和缺陷发生的改进方法是有所需求的。
发明内容
本公开的实施例一般涉及一种用于形成介电膜堆栈的改进方法，该介电膜堆栈用于3D NAND结构中的层间电介质(ILD)层。在一个实施例中，该方法包括提供具有栅堆栈沉积于其上的基板，使用第一RF功率及第一处理气体在该栅堆栈的暴露表面上形成第一氧化层，第一处理气体包含TEOS气体与第一含氧气体，及使用第二RF功率与第二处理气体在该第一氧化层上形成第二氧化层，第二处理气体包含硅烷气体与第二含氧气体。
在另一个实施例中，该方法包括以下步骤：在基板上形成具有阶梯状截面的层堆栈，以第一氧化层覆盖该层堆栈的暴露表面，该第一氧化层具有约10000埃(angstroms)至约30000埃的厚度及约80MPa至约300MPa的拉伸应力，该第一氧化层用以下方式形成：每分钟约3000至约6500毫克的TEOS气体流率，约1200sccm至约21000sccm的含氧气体流率，约1000sccm至约9000sccm的载体气体流率，该载体气体包含氦或氩，约150W至约850W的在13.56MHz的频率的RF功率，约350℃至约650℃的腔室温度，及约2Torr至约14Torr的腔室压力，在该第一氧化层上形成具有约8000埃至约15000埃的厚度的第二氧化层，该第二氧化层用以下方式形成：约100sccm至约600sccm的硅烷气体流率，约2500sccm至约8000sccm的含氧气体流率，约1000sccm至约9000sccm的载体气体流率，该载体气体包含氦或氩，约150W至约850W的在13.56MHz的频率的RF功率，约350℃至约650℃的腔室温度，及约2Torr至约14Torr的腔室压力，及使基板在约700℃至约850℃的温度下的富含氮的环境中经受热退火处理。
在又另一个实施例中，提供了一种在基板上的NAND结构。该结构包括：层堆栈，该层堆栈包含交替的共形的(conformal)氧化层与氮化层，或交替的多晶硅层和氧化层，形成于该层堆栈上的第一氧化层，该第一氧化层具有约10000埃至约30000埃的厚度及约80MPa至约300MPa的拉伸应力，并且该第一氧化层使用第一处理气体形成，该第一处理气体包含TEOS气体与第一含氧气体，及形成在该第一氧化层上的第二氧化层，该第二氧化层具有约8000埃至约15000埃的厚度，该第二氧化层使用第二处理气体形成，该第二处理气体包含硅烷气体与第二含氧气体。
附图说明
本公开的实施例已简要概述于前，并在以下有更详尽的讨论，可以通过参考所附附图中描绘的本公开的示例性实施例以作了解。然而，值得注意的是，所附附图只描绘了本发明的典型实施例，而由于本公开可允许其他等效的实施例，因此所附附图并不会视为对本发明范围的限制。
图1描绘根据本公开的一些实施例的用于在基板顶上形成三维NAND结构的方法。
图2A至2G根据本公开的一些实施例分别描绘通过用于在基板顶上形成三维NAND结构的方法的不同阶段的基板。
为便于理解，在可能的情况下，已使用相同的数字编号代表附图中相同的组件。为求清楚，附图未依比例绘制且可能被简化。可以预期的是，一个实施例的组件与特征可有利地用于其他实施例中而无需赘述。
具体实施方式
图1根据本公开的一些实施例描绘用于在基板顶上形成三维NAND结构的一部分的示例性方法。参照图2A至2G而示例性地描述图1，图2A至2G根据图1流程图示出通过用于在基板顶上形成三维NAND结构的方法的不同阶段的基板的横截面视图。本领域技术人员将进一步认识到用于形成完整三维NAND结构和相关结构的完整过程没有图示于附图中或描述于本说明书中。相反地，为简单和清楚起见，只描绘与描述对于本公开的理解必要的某些过程。此外，虽然各个不同步骤图示于附图中且描述于本说明书中，但没有暗示关于该等步骤的次序或中间步骤的有无的限制。除非明确指定，否则如顺序所示或所述的步骤仅用作解释的目的，而不排除实际上各个步骤如果不是全部也至少部分地以同时或重叠的方式执行的可能性。
该方法开始于102，其中提供基板给处理腔室。处理腔室可以是适合执行如本说明书所述的一或多个沉积处理的任何类型的处理腔室，例如化学气相沉积(CVD)处理腔室、等离子体增强化学气相沉积(PECVD)处理腔室、或适合于执行本说明书所述实施例的任何沉积腔室。
基板可以是适合于半导体器件制造的任何类型基板。例如，参考图2A，基板200可以是硅基板(例如结晶硅(如Si<100>或Si<111>)、氧化硅、应变硅、掺杂或未掺杂的多晶硅或类似物)、III-V族或II-VI族化合物基板、硅锗(SiGe)基板、外延基板、绝缘体上硅(SOI)基板、显示基板(如液晶显示器(LCD))、等离子体显示器、电致发光(EL)灯显示器、太阳能阵列、太阳能板、发光二极管(LED)基板、半导体晶片或类似物。
在一些实施例中，一或多个层可被设置在基板200的顶部。例如，具有多个层(如层206、208)的栅堆栈204可设置在基板200顶上，如图2A所示。多个层可包括适合制造所需器件的任何材料。例如，在一些实施例中，多个层可包括一或多个多晶硅层、一或多个氧化层(例如氧化硅或类似物)、一或多个氮化层(如氮化硅或类似物)或以上各者的任意组合。术语“多晶硅层”考虑其他材料，例如，诸如杂质可以以少量或可追踪量存在于多晶硅层中。
在一些实施例中，多个层可包括交替的氧化层和氮化层，或交替的多晶硅层和氧化层。例如，在一些实施例中，第一层(如层208)可包括氮化层或多晶硅层，而设置在第一层顶上的第二层(如层206)可包括氧化层。图案(例如包括氮化层或多晶硅层的第一层及包括氧化层的第二层)可重复任何所需的次数以形成具有所需厚度的栅堆栈204。
各层可具有适于方便制造所需器件的任何厚度。例如，在一些实施例中，各层可以是约100埃至约600埃厚，或在一些实施例中，可以是约300埃厚。在一些实施例中，所述层可全部具有相同的厚度，或者在一些实施例中，所述层可具有不同的厚度。
在一些实施例中，光致抗蚀剂层202可被设置在栅堆栈204顶上，如图2A所示。光致抗蚀剂层202可包括适合提供模板以帮助蚀刻具有所需特征(如下所述)的栅堆栈204的任何光致抗蚀剂材料。例如，在一些实施例中，光致抗蚀剂层202可以是正或负的光致抗蚀剂和/或DUV或EUV(深紫外线或极紫外线)光致抗蚀剂且可包括以下各者中的一或多者：聚合物、有机化合物(如包含碳、氢和氧)、非晶碳；诸如高级图案化膜(APF)(可自位于加利福尼亚州圣克拉拉市的应用材料公司取得)、三层抗蚀剂(如光致抗蚀剂层、富含Si的抗反射涂层(ARC)和富含碳的ARC或底部ARC(BARC)层)、上旋硬掩模(SOH)或类似物。光致抗蚀剂层202可由任何合适处理形成，例如，图案化的蚀刻处理、旋涂(spin coating)处理、光学光刻技术等。可将光致抗蚀剂层202形成为适合于蚀刻栅堆栈204中所需数量特征的任何厚度。例如，在一些实施例中，光致抗蚀剂层可高达约10μm厚，如约1μm或约5μm厚。
接着，在104，蚀刻光致抗蚀剂层202以暴露交替的氧化层和氮化层或交替的多晶硅层和氧化层(统称为“交替层”)中的至少一部分，并限定将要形成在栅堆栈204的交替层中的特征210，如图2B所示。可经由适合于选择性地蚀刻光致抗蚀剂层202的任何蚀刻处理来蚀刻光致抗蚀剂层202以限定特征210。在一些实施例中，蚀刻处理可以是各向同性蚀刻处理，以减少光致抗蚀剂层202的厚度和宽度同时最小化光致抗蚀剂层202的显著过切(undercutting)。例如，在一些实施例中，光致抗蚀剂层202可经由干法蚀刻处理而被蚀刻，如将光致抗蚀剂层202暴露于含氧等离子体达所需的时间量。
接着，在106，所需数量的交替层被蚀刻以形成NAND结构的特征212，如图2C所示。可蚀刻任何数量的层以形成特征212。在一些实施例中，这些层可依组蚀刻，其中每组包括一个氮化层或多晶硅层和一个氧化层。在此类实施例中，任何数量的组可被蚀刻，例如1至10组的层。例如，在一些实施例中，包括一个氮化层或多晶硅层(如层208)和一个氧化层(如层206)的第一组层220可经蚀刻以形成特征212，如图2C所示。在此类实施例中，特征212可被蚀刻通过氮化层或多晶硅层(层208)，使得特征212的底部226包括下面氧化层(如层228)的暴露部分。
在一些实施例中，在106处形成NAND结构的特征212之后，可至少部分地重复方法100以形成额外的特征。在此类实施例中，在106处形成NAND结构的特征212之后，方法100可回到104(如箭头118指示)，其中可重复光致抗蚀剂层202的蚀刻以限定额外的特征214，如图2D所示。方法100可接着继续再次通过106以在栅堆栈204中形成额外的特征216，如图2E所示。
在每次迭代(iteration)，栅堆栈204的上面层的暴露部分可作为用于栅堆栈204的下面层蚀刻的掩模。例如，如图2D和2E所示，在将特征216蚀刻到层206、208中时，层206、208的暴露部分作为掩模，从而将特征212延伸到设置在第一组层220下方的下一组层。
可重复该处理任意次数，以形成所需数量的特征以至少部分地形成NAND结构。例如，在一些实施例中，可形成多个相邻的特征(如七个特征)以至少部分地形成NAND结构218于基板200顶上。在此类实施例中，多个特征中的每个特征的深度可自基板200的边缘222向基板200的中心224减小，以形成“阶梯状”截面(如NAND阶梯状结构)，如图2F中所示。栅堆栈204可具有约1μm至15μm或以上的总厚度。
在108，一旦阶梯状结构已形成，第一氧化层230共形地形成于栅堆栈204上以覆盖栅堆栈204的暴露表面，如图2G所示。可采用化学气相沉积(CVD)方法、等离子体增强化学气相沉积(PECVD)方法或类似方法来形成第一氧化层230。在一个实施例中，第一氧化层230可由包含四乙氧基硅烷(TEOS)和一氧化二氮(N2O)的处理气体形成。在另一个实施例中，第一氧化层230可由包含TEOS和氧(O2)的处理气体形成。在任一情况下，处理气体可包括一或多种载体气体(例如惰性气体(如氦(He)或氩(Ar)))，以利于处理腔室内处理气体的输送和分配。在一个示例中，处理气体包含TEOS、N2O和Ar。在另一示例中，处理气体包含TEOS、He和O2。如果需要，处理气体可包括P型或N型掺杂剂气体。示例性的掺杂剂气体可包括如含磷气体或含硼气体。相较于未掺杂氧化物，P型掺杂氧化物可表现出较好的耐破裂性。本发明人已观察到，用本说明书所述的第一氧化层230覆盖栅堆栈204改善了栅堆栈204的热稳定性，同时为下面的栅堆栈204提供良好的接缝覆盖。否则，如果栅堆栈204被由硅烷和氧或一氧化二氮形成的氧化层覆盖，这些接缝缺陷将出现于阶梯状结构的角落处或附近。
可以以每分钟约1200毫克(mgm)至约8000mgm的流率提供TEOS，例如约3000mgm至约6500mgm，如约3700mgm。可以以约每分钟1000标准立方厘米(sccm)至约28000sccm的流率提供含氧气体(如N2O或O2)，如约1200sccm至约21000sccm，例如约1600sccm至约10000sccm。使用较高O2:TEOS比例(如约2:1至约6:1，例如约3:1至约4:1)来沉积第一氧化层230可通过减少膜的应力差(delta stress)来帮助减少或最小化NAND结构218中的应力。本说明书所述的应力差为栅堆栈204后退火(post-anneal)中的应力减去栅堆栈204预退火(pre-anneal)中的应力的绝对值。因此，第一氧化层230用于减少跨基板200和栅堆栈204接口的应力差量。
可以以约1000sccm至约9000sccm的流率提供载体气体，如约3000sccm至约5400sccm，例如约3700sccm。TEOS与含氧气体以及任何载体气体(如果使用的话)的流动时间(即开启气体时间)可以是约5秒至约15秒，如约10秒。
腔室压力可以是约1至约400Torr，如约2Torr至约14Torr，例如约4.8Torr。腔室温度可以是约350℃至约650℃，如约400℃至约600℃，例如约550℃。电极间隔可以是约200至约550mil，例如约220mil。一旦处理气体已引入到处理腔室中，RF功率便被提供到电极以点燃处理气体以形成等离子体。等离子体可由约2MHz或以上的高频(HF)RF功率、约100kHz至约1MHz的低频(LF)RF功率或它们的组合形成。对于300mm基板，RF功率的功率电平是在约5W至约3000W的范围内。在一个实施例中，以约100W在约350KHz的低频提供RF功率。在一个实施例中，以约150W在约13.56MHz提供HF RF功率，同时关闭LF RF。在一个实施例中，以约300W在约13.56MHz提供HF RF功率，同时关闭LF RF。在一个实施例中，以约850W在约13.56MHz提供HF RF功率，同时关闭LF RF。在一些实施例中，可使用HF和LF RF的组合来控制离子轰击。在此类情况下，可使用以约100W在350kHz运行的LF RF功率与约300W在13.56MHz运行的HF RF功率的组合。可增加LF:HF的比例以提高膜的致密化，从而产生拉伸第一氧化层230。
沉积时间可以是约150秒至约350秒，例如约200秒至约260秒。沉积速率可以是约5000至约10000埃/分钟，例如约6500至约7600埃/分钟。在各种实施例中，第一氧化层230可形成为约5000埃至约35000埃的厚度，如约10000埃至约30000埃，例如约15000埃至约25000埃，这取决于下面栅堆栈的高度。典型地，第一氧化层230形成有约80MPa至约300MPa的拉伸应力，如约100MPa至约200MPa，例如150MPa。
可利用额外的处理参数来促成等离子体点燃和稳定。例如，在一些实施例中，在等离子体点燃之前，处理腔室可维持在约50℃至约150℃的温度。在一些实施例中，在第一氧化层230的沉积之前，惰性气体(如Ar)可流入处理腔室中，以帮助点燃等离子体。
高拉伸膜可以是多孔的且在后退火处理后具有高厚度收缩率。已经观察到，由于第一氧化层230的收缩率或应力变化造成的膜破裂可能导致第二氧化层232(下面将要讨论)与栅堆栈204的分离。因此，在一些实施例中，一旦已达到第一氧化层230的所需厚度，就可任选地使RF功率从150W斜线上升至约200W，以形成在第一氧化层230上的氧化物初始层(未示出)。TEOS和含氧气体(如N2O或O2)以及载体气体(如果使用的话)的流动可在初始层的形成期间继续。相信RF功率的增加会产生高密度氧化物初始层，及因此有助于第一氧化层230黏附于后续沉积的第二氧化层232。在一个实施例中，RF功率的斜线上升可持续约1秒至约5秒，例如约2秒。另外地或替代地，一旦已达到第一氧化层230的所需厚度，TEOS的流动便可斜线上升以产生高密度氧化物初始层。TEOS流动的斜线上升可持续约1秒至约5秒，例如约2秒。
替代地或另外地，可以任选地在第一氧化层230上或在氧化物初始层(如果存在的话)上形成氧化物的过渡层(未示出)。过渡层可通过将RF功率从约150W(或者，如果期望的是初始层的话，从200W)增加到约400W同时逐渐减少TEOS的流动来形成。在一些实施例中，过渡层的形成可通过将RF功率从约150W(或者，如果期望的是初始层的话，从200W)增加到约400W，同时关闭TEOS的流动以产生过渡层。过渡层可用作应力释放层，以使在第一氧化层230处的应力集中平滑(smoothen out)。初始层和过渡层亦提供与第一氧化层230和沉积在其上的任何后续层的良好黏附。
在110，在第一氧化层230已经形成在栅堆栈204上以后，或在初始层和/或过渡层已经形成在第一氧化层230上之后，第二氧化层232共形地沉积在第一氧化层230上，如图2G所示。在一个实施例中，第二氧化层232可由包括硅烷(SiH4)和一氧化二氮(N2O)的处理气体形成。在另一个实施例中，第二氧化层232可以由包括SiH4和氧(O2)的处理气体来形成。在任一情况下，处理气体可包括一或多种载体气体(例如惰性气体，如氦(He)或氩(Ar))，以利于处理腔室内处理气体的输送和分配。第二氧化层232用作覆盖层以通过将第一氧化层230与诸如通过化学机械研磨(CMP)的平坦化之类的后续处理步骤隔离来保护第一氧化层230，通过化学机械研磨(CMP)的平坦化可能对第一氧化层230的完整性与性质会有显著的不利影响。第二氧化层232亦阻挡第一氧化层230的吸湿、除气和不希望的化学侵蚀。具体来说，发明人已观察到以第二氧化层232覆盖第一氧化层230可以帮助防止在后退火之后第一氧化层230的破裂。另外，第二氧化层232可有助于下面层或结构的应力。具体而言，因为第一氧化层230在退火之后变得更为压缩，所以第二氧化层232有助于使第一氧化层在退火之后更有拉伸性(且因此可具有抵消效应)。
第二氧化层232和第一氧化层230可在相同或不同的处理腔室中沉积。可以以约100sccm至约600sccm的流率提供SiH4，如约150sccm至约300sccm，例如约200sccm。可以以约1000sccm至约15000sccm的流率提供含氧气体(如N2O或O2)，如约2500sccm至约8000sccm，例如约3520sccm至约6480sccm。可以以约1000sccm至约9000sccm的流率提供载体气体，如约3000sccm至约5400sccm，例如约3500sccm。
腔室压力可以是约1至约400Torr，如约2Torr至约14Torr，例如约5.3Torr。腔室温度可以是约350℃至约650℃，如约400℃至约600℃，例如约550℃。电极间隔可以是约200至约550mil，例如约220mil。一旦处理气体已引入到处理腔室中，RF功率便被提供到电极以点燃处理气体以形成等离子体。等离子体可由约2MHz或以上的高频(HF)RF功率、约100kHz至约1MHz的低频(LF)RF功率或它们的组合形成。对于300mm基板，RF功率的功率电平是在约5W至约3000W的范围内。在一个实施例中，以约300W在约13.56MHz提供HF RF功率，同时关闭LFRF。在一个实施例中，以约150W在约13.56MHz提供HF RF功率，同时关闭LF RF。在一个实施例中，以约850W在约13.56MHz提供HF RF功率，同时关闭LF RF。
沉积时间可以是约50秒至约200秒，例如约110秒。在各种实施例中，第二氧化层232可形成为约5000埃至约25000埃的厚度，如约8000埃至约15000埃，例如约10000埃，这取决于下面栅堆栈的高度。第一氧化层230和第二氧化层232的总厚度可在约30000埃至约50000埃之间的范围内。
在112，基板200在约700℃至约850℃的温度(如约750℃)下的富含氮(N2)的环境中经受热退火处理。热退火处理为第二氧化层232提供气密(hermetic)密封表面，以防止膜破裂。热退火处理可在用于沉积处理的相同处理腔室中原位地执行，或可在炉(furnace)或快速热退火(RTA)腔室中执行。炉中的热退火处理可以执行一小时。对于快速热退火室，热退火处理可执行约1秒至约300秒，如约15秒至约120秒，例如约30秒。在后退火处理之后，厚度收缩率小于约3％。已经观察到这个后退火处理为后沉积的致密化增加提供一个起始点，如通过厚度收缩率测定的，从约10％至约25％。已经观察到，具有较高拉伸应力的第一氧化层230可能在热退火处理之后产生较高的收缩率。
热退火处理可在第一氧化层230和第二氧化层232的沉积之间执行。例如，在一些实施例中，处理顺序可包括第一氧化层230(厚度约15000埃)的沉积-热退火处理-第二氧化层232(厚度约15000埃)的沉积。在一些实施例中，处理顺序可包括第一氧化层230(厚度约15000埃)的沉积-热退火处理-第二氧化层232(厚度约15000埃)的沉积-热退火处理。
在114，可执行任选的平坦化过程(如化学机械研磨(CMP))以移除第二氧化层230的一部分到所需的厚度。如果需要的话，平坦化过程可在热退火处理之前执行。
对于基板顶上的3D NAND阶梯状结构，本公开的实施例提供双层膜堆栈。用TEOS与N2O或O2形成的底部氧化层为下面的栅堆栈提供良好的缝隙覆盖，而用SiH4与N2O或O2形成的上部氧化层将底部氧化层隔离以免吸湿、除气和不必要的化学侵蚀以及在后退火处理之后的底部氧化层破裂。用TEOS和N2O形成的底部氧化层和气密的上部氧化层实现了用于NAND阶梯状结构的高质量的拉伸氧化膜堆栈。
虽然前面所述是针对本公开的实施例，但在不背离本发明基本范围下，可设计本公开的其他与进一步的实施例。

Claims (15)

1.一种用于处理基板的方法，包括以下步骤：
提供具有栅堆栈的基板，所述栅堆栈沉积在所述基板上；
使用第一RF功率及第一处理气体在所述栅堆栈的暴露表面上形成第一氧化层，所述第一处理气体包含TEOS气体与第一含氧气体；及
使用第二RF功率及第二处理气体在所述第一氧化层上形成第二氧化层，所述第二处理气体包含硅烷气体与第二含氧气体。
2.如权利要求1所述的方法，其中所述第一含氧气体和所述第二含氧气体包括O2或N2O。
3.如权利要求1所述的方法，其中所述栅堆栈具有阶梯状截面。
4.如权利要求1所述的方法，其中所述第一含氧气体和所述TEOS气体以第一含氧气体:TEOS气体为约2:1至约6:1的比例提供。
5.如权利要求1所述的方法，其中以约150W至约850W并且在13.56MHz的高频来提供所述第一RF功率。
6.如权利要求1所述的方法，进一步包括以下步骤：
在所述第一氧化层达到了预定厚度之后，斜线上升增加所述第一RF功率以在所述第一氧化层上形成初始层。
7.如权利要求1所述的方法，进一步包括以下步骤：
在所述第一氧化层达到了预定厚度之后，斜线上升增加所述TEOS气体以在所述第一氧化层上形成初始层。
8.如权利要求1所述的方法，其中所述第一RF功率是以约100瓦以350kHz运行的低频RF功率与以约300瓦在13.56MHz运行的高频RF功率的组合。
9.如权利要求1所述的方法，其中以约150W至约850W并且在13.56MHz的频率来提供所述第二RF功率。
10.如权利要求1所述的方法，其中所述第一氧化层具有约10000埃至约30000埃的厚度，而所述第二氧化层具有约8000埃至约15000埃的厚度。
11.如权利要求1所述的方法，进一步包括以下步骤：
在形成所述第二氧化层后，所述基板在约700℃至约850℃的温度下的富含氮的环境中经受热退火处理。
12.一种用于处理基板的方法，包括以下步骤：
在基板上形成具有阶梯状截面的层堆栈；
以第一氧化层覆盖所述层堆栈的暴露表面，所述第一氧化层具有约10000埃至约30000埃的厚度及约80MPa至约300MPa的拉伸应力，所述第一氧化层用以下方式形成：
每分钟约3000至约6500毫克的TEOS气体流率；
约1200sccm至约21000sccm的含氧气体流率；
约1000sccm至约9000sccm的载体气体流率，所述载体气体包含氦或氩；
约150W至约850W的在13.56MHz的频率的RF功率；
约350℃至约650℃的腔室温度；及
约2Torr至约14Torr的腔室压力；
在所述第一氧化层上形成具有约8000埃至约15000埃的厚度的第二氧化层，所述第二氧化层用以下方式形成：
约100sccm至约600sccm的硅烷气体流率；
约2500sccm至约8000sccm的含氧气体流率；
约1000sccm至约9000sccm的载体气体流率，所述载体气体包含氦或氩；
约150W至约850W的在13.56MHz的频率的RF功率；
约350℃至约650℃的腔室温度；及
约2Torr至约14Torr的腔室压力；及
使所述基板在约700℃至约850℃的温度下的富含氮的环境中经受热退火处理。
13.如权利要求12所述的方法，其中所述第一含氧气体和所述第二含氧气体包括O2或N2O。
14.如权利要求12所述的方法，其中在所述第一氧化层的形成期间，所述含氧气体和所述TEOS气体以含氧气体:TEOS气体为约2:1至约6:1的比例提供。
15.一种在基板上的NAND结构，包括：
层堆栈，所述层堆栈包含交替的共形的氧化层与氮化层，或交替的多晶硅层和共形氧化层；
第一氧化层，所述第一氧化层形成于所述层堆栈上，所述第一氧化层具有约10000埃至约30000埃的厚度及约80MPa至约300MPa的拉伸应力，并且所述第一氧化层由第一处理气体形成，所述第一处理气体包含TEOS气体与第一含氧气体；及
第二氧化层，所述第二氧化层形成在所述第一氧化层上，所述第二氧化层具有约8000埃至约15000埃的厚度，所述第二氧化层由第二处理气体形成，所述第二处理气体包含硅烷气体与第二含氧气体。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107731836A (zh) * 2017-08-28 2018-02-23 长江存储科技有限责任公司 台阶结构的形成方法
CN110867449A (zh) * 2019-11-12 2020-03-06 长江存储科技有限责任公司 三维存储器及其制备方法
CN110942974A (zh) * 2018-09-25 2020-03-31 长鑫存储技术有限公司 半导体结构的形成方法及在晶圆上形成氧化硅膜的方法
CN112342531A (zh) * 2020-10-19 2021-02-09 绍兴同芯成集成电路有限公司 一种利用低频射频电浆制备ild绝缘层的晶圆制造工艺

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170092492A1 (en) * 2015-09-28 2017-03-30 Applied Materials, Inc. Methods for forming a silicon containing dielectric film using a gas mixture with ar gas dilusion
JP6674406B2 (ja) * 2017-03-23 2020-04-01 キオクシア株式会社 半導体装置及びその製造方法
JP6767302B2 (ja) * 2017-04-14 2020-10-14 東京エレクトロン株式会社 成膜方法
US10358717B2 (en) * 2017-04-21 2019-07-23 Lam Research Corporation Method for depositing high deposition rate, thick tetraethyl orthosilicate film with low compressive stress, high film stability and low shrinkage
US10355012B2 (en) * 2017-06-26 2019-07-16 Sandisk Technologies Llc Multi-tier three-dimensional memory device with stress compensation structures and method of making thereof
KR102614427B1 (ko) * 2018-09-19 2023-12-18 삼성전자주식회사 반도체 소자 및 그 형성 방법
CN113892168A (zh) * 2019-03-28 2022-01-04 朗姆研究公司 蚀刻停止层
KR20220038784A (ko) * 2019-08-07 2022-03-29 어플라이드 머티어리얼스, 인코포레이티드 3d nand를 위한 수정된 스택들

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103210479A (zh) * 2010-11-12 2013-07-17 应用材料公司 用以降低超低k介电薄膜的黏着层厚度并提高抗破坏性的工艺
CN104795352A (zh) * 2014-01-21 2015-07-22 瑞萨电子株式会社 制造半导体器件的方法

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0562625B1 (en) * 1992-03-27 1997-06-04 Matsushita Electric Industrial Co., Ltd. A semiconductor device and process
US5271972A (en) * 1992-08-17 1993-12-21 Applied Materials, Inc. Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity
JP3571129B2 (ja) * 1995-11-10 2004-09-29 株式会社半導体エネルギー研究所 プラズマｃｖｄ法および薄膜トランジスタの作製方法
US6013584A (en) 1997-02-19 2000-01-11 Applied Materials, Inc. Methods and apparatus for forming HDP-CVD PSG film used for advanced pre-metal dielectric layer applications
US5908672A (en) * 1997-10-15 1999-06-01 Applied Materials, Inc. Method and apparatus for depositing a planarized passivation layer
US6121164A (en) 1997-10-24 2000-09-19 Applied Materials, Inc. Method for forming low compressive stress fluorinated ozone/TEOS oxide film
EP0959496B1 (en) 1998-05-22 2006-07-19 Applied Materials, Inc. Methods for forming self-planarized dielectric layer for shallow trench isolation
US6025279A (en) 1998-05-29 2000-02-15 Taiwan Semiconductor Manufacturing Company Method of reducing nitride and oxide peeling after planarization using an anneal
US6372664B1 (en) 1999-10-15 2002-04-16 Taiwan Semiconductor Manufacturing Company Crack resistant multi-layer dielectric layer and method for formation thereof
US6451390B1 (en) * 2000-04-06 2002-09-17 Applied Materials, Inc. Deposition of TEOS oxide using pulsed RF plasma
US6511923B1 (en) 2000-05-19 2003-01-28 Applied Materials, Inc. Deposition of stable dielectric films
US6521302B1 (en) * 2000-09-26 2003-02-18 Applied Materials, Inc. Method of reducing plasma-induced damage
TWI289329B (en) * 2002-04-03 2007-11-01 Taiwan Semiconductor Mfg Method and apparatus for controlling spacer width
US6828255B2 (en) 2002-11-22 2004-12-07 Taiwan Semiconductor Manufacturing Co., Ltd Crack inhibited composite dielectric layer
US7807225B2 (en) 2003-01-31 2010-10-05 Sharp Laboratories Of America, Inc. High density plasma non-stoichiometric SiOxNy films
US7544625B2 (en) 2003-01-31 2009-06-09 Sharp Laboratories Of America, Inc. Silicon oxide thin-films with embedded nanocrystalline silicon
US7157331B2 (en) 2004-06-01 2007-01-02 Macronix International Co., Ltd. Ultraviolet blocking layer
US7273823B2 (en) 2005-06-03 2007-09-25 Applied Materials, Inc. Situ oxide cap layer development
KR100668745B1 (ko) 2005-12-29 2007-01-29 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 형성 방법
US7780865B2 (en) 2006-03-31 2010-08-24 Applied Materials, Inc. Method to improve the step coverage and pattern loading for dielectric films
US7297376B1 (en) * 2006-07-07 2007-11-20 Applied Materials, Inc. Method to reduce gas-phase reactions in a PECVD process with silicon and organic precursors to deposit defect-free initial layers
JP2008078404A (ja) 2006-09-21 2008-04-03 Toshiba Corp 半導体メモリ及びその製造方法
US7741171B2 (en) 2007-05-15 2010-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Oxygen-rich layers underlying BPSG
US8508997B2 (en) 2009-12-23 2013-08-13 Intel Corporation Multi-cell vertical memory nodes
US20120149213A1 (en) * 2010-12-09 2012-06-14 Lakshminarayana Nittala Bottom up fill in high aspect ratio trenches
DE102014208859B4 (de) * 2013-05-20 2021-03-11 Semiconductor Energy Laboratory Co., Ltd. Halbleitervorrichtung
US8937021B2 (en) 2013-06-20 2015-01-20 Applied Materials, Inc. Methods for forming three dimensional NAND structures atop a substrate
US9236255B2 (en) 2013-06-26 2016-01-12 Applied Materials, Inc. Methods for forming three dimensional NAND structures atop a substrate
KR102147911B1 (ko) * 2013-07-02 2020-10-14 삼성전자주식회사 반도체 메모리 소자 및 그 제조방법
KR102270101B1 (ko) * 2015-02-10 2021-06-29 삼성전자주식회사 반도체 소자 및 그 제조 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103210479A (zh) * 2010-11-12 2013-07-17 应用材料公司 用以降低超低k介电薄膜的黏着层厚度并提高抗破坏性的工艺
CN104795352A (zh) * 2014-01-21 2015-07-22 瑞萨电子株式会社 制造半导体器件的方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
李娟: "CVD采用TEOS-O3沉积二氧化硅薄膜", 《河北大学硕士论文》 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107731836A (zh) * 2017-08-28 2018-02-23 长江存储科技有限责任公司 台阶结构的形成方法
CN110942974A (zh) * 2018-09-25 2020-03-31 长鑫存储技术有限公司 半导体结构的形成方法及在晶圆上形成氧化硅膜的方法
CN110867449A (zh) * 2019-11-12 2020-03-06 长江存储科技有限责任公司 三维存储器及其制备方法
CN112342531A (zh) * 2020-10-19 2021-02-09 绍兴同芯成集成电路有限公司 一种利用低频射频电浆制备ild绝缘层的晶圆制造工艺

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