CN114664651A - 半导体表面缺陷的处理方法和半导体器件的制备方法 - Google Patents

半导体表面缺陷的处理方法和半导体器件的制备方法 Download PDF

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CN114664651A
CN114664651A CN202011541065.9A CN202011541065A CN114664651A CN 114664651 A CN114664651 A CN 114664651A CN 202011541065 A CN202011541065 A CN 202011541065A CN 114664651 A CN114664651 A CN 114664651A
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layer
deposition
deposition layer
silicon
semiconductor device
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江向红
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to PCT/CN2021/097458 priority patent/WO2022134474A1/zh
Priority to US17/599,473 priority patent/US12033857B2/en
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Abstract

该发明公开了一种半导体表面缺陷的处理方法和半导体器件的制备方法，所述半导体表面缺陷的处理方法包括：将半导体器件置于等离子体处理设备内，所述半导体器件包括衬底和形成在所述衬底表面的沉积层，所述沉积层形成有气泡；对所述沉积层表面进行等离子体轰击以将所述气泡击破，使得所述沉积层表面平整。根据本发明实施例的半导体表面缺陷的处理方法，能够使得半导体表面更加平整且能够提高半导体器件的良率。

Description

半导体表面缺陷的处理方法和半导体器件的制备方法
技术领域
本发明涉及半导体技术领域，具体涉及一种半导体表面缺陷的处理方法和半导体器件的制备方法。
背景技术
现有半导体器件工艺中，在沉积形成薄膜层时，由于表面残留气体的影响，导致气体被包在膜层下，在膜层表面形成凸出的气泡导致膜层表面不平整，尤其是在硬掩模层工艺过程中，在工艺末期对膜层进行刻蚀时，凸出气泡顶部刻蚀容易形成尖端凸出，尖端凸出容易发生剥落掉入刻蚀凹槽内，导致半导体器件刻蚀后形成颗粒遮挡，而且在刻蚀过程中，由于气泡形成，刻蚀气体或溶液进入气泡内，刻蚀宽度发生变化，容易出现侧蚀问题，导致刻蚀宽度变大而影响后续良率异常。
发明内容
本发明的目的在于提供一种半导体表面缺陷的处理方法，能够使得半导体表面更加平整且能够提高半导体器件的良率。
根据本发明实施例的半导体表面缺陷的处理方法，包括：将半导体器件置于等离子体处理设备内，所述半导体器件包括衬底和形成在所述衬底表面的沉积层，所述沉积层形成有气泡；对所述沉积层表面进行等离子体轰击以将所述气泡击破，使得所述沉积层表面平整。
根据本发明的一些实施例，所述沉积层形成为含有硅氢键的含硅化合物层，在对所述沉积层表面进行等离子体轰击时采用硼烷气体进行等离子体轰击，所述硅氢键断裂并形成键能稳定的硼氢键。
可选地，在对所述沉积层表面进行等离子体轰击后，于所述沉积层表面形成覆盖所述沉积层的含硼氢键的氮化硅层。
可选地，所述硼烷气体的流速为2000～5000sccm，所述制程温度为400～480℃，工艺压力在2～5Tor。
可选地，所述射频功率为300～800W。
可选地，在于所述衬底表面形成沉积层的步骤中，采用硅烷气体与氨气为形成所述沉积层的原料气体，所述气泡内具有形成所述沉积层后的残余生成气体，在将所述气泡击破后还包括以下步骤：将所述气泡击破后释放的气体抽除。
可选地，所述沉积层为氮化硅层、氧化硅层、氮氧化硅层或非晶硅(a-Si)层。
可选地，在对所述沉积层表面进行等离子体轰击时，采用惰性气体为载气。
进一步地，所述惰性气体的流速为1000～3000sccm。
本发明还提出了一种半导体器件的制备方法。
根据本发明实施例的半导体器件的制备方法包括：提供半导体衬底；采用等离子体增强化学气相沉积法于所述半导体表面形成层叠设置的多层沉积层，所述沉积层形成有气泡；在形成多层所述沉积层时，至少对位于最底层的所述沉积层进行等离子体轰击以击破所述气泡后，于所述最底层的沉积层表面形成其它沉积层；图形化所述多层沉积层。
根据本发明的一些实施例，所述最底层的沉积层形成为含硅氢键的硅化合物层，在对所述最底层的沉积层进行等离子轰击时，采用硼烷气体进行等离子体轰击，所述硅氢键断裂以形成键能稳定的硼氢键。
可选地，在对所述最底层的沉积层进行等离子体轰击后，所述最底层的沉积层的表面形成含硼氢键的硅化合物层，在于所述最底层的沉积层表面形成其它沉积层的步骤中，所述其它沉积层形成在所述硼氢键的硅化合物层的表面。
根据本发明的一些实施例，所述沉积层形成为掩膜层。
可选地，所述多层沉积层包括第一掩膜层和第二掩膜层，在形成所述多层沉积层的步骤中包括：于所述半导体衬底表面形成所述第一掩膜层，对所述第一掩膜层表面进行等离子体轰击以击破所述第一掩膜层的气泡；于通过等离子体轰击后的所述第一掩膜层表面形成所述第二掩膜层，对所述第二掩膜层表面进行等离子体轰击以击破所述第二掩膜层的气泡。
根据本发明的一些实施例，所述形成多层沉积层和对所述沉积层进行等离子体轰击在同一反应腔室进行。
根据本发明实施例的半导体表面缺陷的处理方法，通过半导体等离子体工艺对沉积层的表面进行等离子体轰击以将半导体器件表面形成的气泡击破，使得气泡中的残余气体溢出，从而能够消除半导体器件表面形成的气泡，使得沉积层表面平整，这样在后续半导体制备工艺中，例如在半导体器件表面进行沉积和刻蚀时，不仅能够避免形成凸出部，使得沉积后形成的半导体器件表面更加平整，也能够避免刻蚀后造成颗粒遮挡和侧蚀的问题，以提高后续产品良率。
附图说明
图1-图6为相关技术中半导体器件的制备的各步骤的工艺流程图；
图7-图9为本发明实施例的半导体表面缺陷处理方法和半导体器件的制备方法的各步骤的工艺流程剖视图；
图10-图11为本发明实施例的半导体表面处理方法的原理示意图；
图12为根据本发明实施例的半导体表面缺陷的处理方法的流程示意图
图13为根据本发明实施例的半导体器件的制备方法的流程示意图。
附图标记：
1：半导体衬底；
11：沉积层，12：含硼氢键的沉积层，13：气泡。
具体实施方式
以下结合附图和具体实施方式对本发明提出的一种半导体表面缺陷的处理方法作进一步详细说明。
如图1-图6所示，相关技术的半导体器件在制备过程中，例如在硬掩模层工艺过程中，尤其是工艺末期，由于薄膜层11’形成速率较快，而工艺中形成的气体无法快速排出，使得形成的薄膜层11’的表面会有气体残留，导致气体被包裹在薄膜层11’下而在薄膜层的表面形成凸出的气泡13’，这样在后续沉积其它薄膜层15’过程中，在气泡13’的位置处的其它薄膜层15’形成凸出表面的凸出部12’，不仅导致了形成的半导体器件表面不平整，而且在后续进行刻蚀时，当刻蚀位置形成在气泡13’位置处时，由于气泡13’内形成有一定的空间，刻蚀气体或刻蚀液体进入气泡13’内，由于气泡13’的大小与刻蚀位置的差异，导致刻蚀出现偏差，例如如图6所示的出现侧蚀现象，影响刻蚀凹槽的宽度，导致后续良率异常。而且如图6所示，由于位于气泡上方的凸出部12’，在进行刻蚀时导致刻蚀凹槽的顶部形成向上倾斜的尖端而与半导体器件的表面不平整，在刻蚀时从而容易形成颗粒14’脱落进入刻蚀凹槽内，造成在刻蚀凹槽内形成颗粒遮挡而产生半导体器件良率异常的问题。
下面参考附图描述根据本发明实施例的半导体表面缺陷的处理方法。
如图12所示，根据本发明实施例的半导体表面缺陷的处理方法的步骤包括：将半导体器件置于等离子体处理设备内，所述半导体器件包括衬底1和形成在所述衬底1表面的沉积层11，所述沉积层11形成有气泡13；对所述沉积层11表面进行等离子体轰击以将所述气泡13击破，使得所述沉积层11表面平整。
本发明实施例的半导体表面缺陷的处理方法用于对半导体制程工艺中表面沉积沉积层11的半导体器件表面缺陷进行处理，尤其是在硬掩模工艺中形成的半导体器件。将半导体器件置于等离子体设备内，通过等离子体设备可对半导体器件的表面进行等离子体处理。
具体地，如图7和图8所示，半导体器件包括衬底1和形成在衬底1表面的沉积层11，沉积层11中形成有气泡13；衬底1材料可以为硅(Si)、锗(Ge)、硅锗(GeSi)、或碳化硅(SiC)；也可以是绝缘体上硅(SOI)、绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。
在半导体器件的制备工艺中，通过在衬底1表面沉积形成沉积层11，并通过刻蚀等工艺形成需要的半导体器件，正如背景技术所述，在形成沉积层11的过程中，由于沉积反应速率与反应生成气体排出速率的不对等，造成沉积层11表面气体的残留，使得在沉积层11的表面形成凸出沉积层11表面的气泡13。
将半导体器件置于等离子体处理设备中，如图8所示，通过半导体等离子体工艺对沉积层11的表面进行等离子体轰击以将半导体器件表面形成的气泡13击破，使得气泡13中的残余气体溢出，从而能够消除半导体器件表面形成的气泡13，使得沉积层11表面平整，这样在后续半导体制备工艺中，例如在半导体器件表面进行沉积和刻蚀时，不仅能够避免形成凸出部，使得沉积后形成的半导体器件表面更加平整，也能够避免刻蚀后造成颗粒遮挡和侧蚀的问题，以提高后续产品良率。
在本发明的一些实施例中，沉积层11可形成为含有硅氢键的含硅化合物层，例如沉积层11可以为氮化硅层、氧化硅层、氮氧化硅层或非晶硅(a-Si)层等。在形成沉积层11的工艺中可采用等离子体增强化学气相沉积法在半导体衬底1表面形成沉积层11，在工艺设备中通入原料气体，通过原料气体反应后在衬底1表面形成含有硅氢键的含硅化合物层，例如沉积层11可形成为氮化硅层，具体在沉积时可采用硅烷气体与氨气作为原料以形成具有硅氢键的氮化硅层。
这样如图9所示，在对沉积层11表面进行等离子体轰击时可采用硼烷气体进行等离子体轰击，硅氢键断裂并形成键能稳定的硼氢键。即通过硼烷气体对含有硅氢键的含硅化合物层表面进行等离子体轰击，如图10-图11所示，硼烷中的硼离子解离成等离子体，轰击沉积层11表面，促进沉积层11表面的硅氢键的断裂解离，并取代硅氢键中的硅，形成具有短键长高健能的硼氢键，不仅使得沉积层11表面气泡13中残留气体逸出，沉积层11表面更加平整，而且能够在沉积层11表面形成含硼氢键的硅化合物层12，从而能够使得沉积层11表面更加致密，沉积层11表面的缺陷得到改善，稳定性更好，也能够改善沉积层11的介电常数和光学性能。
可选地，在对沉积层11表面进行等离子体轰击时，硼烷气体的流速为2000～5000sccm，制程温度为400～480℃，工艺压力在2～5Tor，射频功率为300～800W。由此通过在等离子体轰击处理过程中，通过调整硼烷气体的流速、等离子体的工艺压力、制程温度以及射频功率和时间等可以进一步地改善形成的沉积层11表面的介电常数和光学性能，以使得形成的沉积层11表面更加稳定。
进一步地，在于衬底1表面形成沉积层11的步骤中，可采用硅烷气体与氨气为形成沉积层11的原料气体，气泡13内具有形成沉积层11后的残余生成气体，在将气泡13击破后还包括以下步骤：将气泡13击破后释放的气体抽除。
可选地，在对沉积层11表面进行等离子体轰击时，可采用惰性气体为载气以避免与沉积层11发生反应，惰性气体的流速为1000～3000sccm。
下面以硬掩模层工艺中形成的沉积层11为氮化硅层为例进行具体地描述。
在形成氮化硅层工艺过程中，采用硅烷气体和氨气作为原料气体，其中，硅烷气体和氨气的比例可以为：SIH4/NH3≈1.5，制程温度400℃-480℃,工艺压力在2-7Tor，射频频率设定在70-100W，适当降低工艺压力,加速残留气体的抽离。
在主沉积结束时，引入硼烷气体作为后续处理气体，硼烷气体的流速为2000～5000sccm，制程温度为400～480℃，工艺压力在2～5Tor，射频功率为300～800W。在惰性气体如氩气作用下，氩气流速为1000～3000sccm，硼离子解离成等离子体，轰击半导体器件的沉积层11表面，使得硅氢键受到轰击断裂，硼离子与断裂的氢结合，形成更加稳定的短键长高键能的硼氢键，解离的硅被氮化进而形成大量的硅氮键，具体反应如下：
反应方程式：
SiH4+NH3+e-→Si-H+N-H+H2↑+e-
B2 H6+e-→B+H+e-
N-H+Si-H+B→SixNy+B-H+H2↑
由此不仅使得沉积层11表面的气泡13中的残留气体逸出，而且能够使得沉积层11表面更加致密平整，改善了沉积层11表面的性能。
下面参考附图描述根据本发明实施例的半导体器件的制备方法。
如图13所示，根据本发明实施例的半导体器件的制备方法可以包括：提供半导体衬底1；采用等离子体增强化学气相沉积法于半导体表面形成层叠设置的多层沉积层11，沉积层11形成有气泡13；在形成多层沉积层11时，至少对位于最底层的沉积层11进行等离子体轰击以击破气泡13后，于最底层的沉积层11表面形成其它沉积层；图形化多层沉积层11。
具体地，半导体衬底1材料可以为硅(Si)、锗(Ge)、硅锗(GeSi)、或碳化硅(SiC)；也可以是绝缘体上硅(SOI)、绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。
采用等离子体增强化学气相沉积法于半导体表面形成层叠设置的多层沉积层11，例如在采用等离子体增强化学气相沉积法形成的硬掩模层工艺过程中；沉积层11表面会形成有气泡13。
沉积层11可以形成为一层，也可以为多层，例如在半导体衬底1表面形成多层沉积层11时，多层沉积层11层叠设置且多层沉积层11的材料是不同的，为了避免在最终形成的半导体器件的表面形成较大的凸出部，使得半导体器件的表面更加平整，可至少对最底层的沉积层11进行等离子体轰击，即对位于半导体衬底1表面且与半导体衬底1表面接触的沉积层11进行等离子体进行轰击以击破其表面形成的气泡，使得最底层的沉积层11的表面更加致密平整。然后于最底层的沉积层11的表面沉积其它沉积层，所述其它沉积层形成在最低层沉积层11的上方且形成材料与最低层的沉积层11的材料不同，例如最低层的沉积层11可以为氮化硅层，位于所述氮化层上的其它沉积层可以为无定型碳层、氧化硅层等。由此不仅能够使得半导体器件表面更加平整，而且由于最底层的沉积层11形成在半导体衬底1的表面，也能够避免由于最底层的沉积层11形成气泡13而在刻蚀时产生侧蚀的问题。
当然可以理解的是，为了进一步地提高半导体器件的表面的平整度和致密性，在形成每层沉积层11后均可以采用等离子体轰击去除每层沉积层11表面形成的气泡13，等离子体轰击的次数可以等于小于多层沉积层11的层数。
最后图形化多层沉积层11，这样，在图形化沉积层11的过程中，形成的半导体器件表面更加平整，从而避免了图形化过程中由于表面凸出部造成的颗粒脱落在刻蚀凹槽内，也能够避免刻蚀凹槽时由于侧蚀造成的刻蚀凹槽宽度异常的问题，能够提高产品良率。
可选地，形成多层沉积层11和对沉积层11进行等离子体轰击在同一反应腔室进行。从而能够简化半导体器件制备的工艺，也能够减少对半导体器件的污染。例如，在形成多层沉积层11时将半导体衬底1置于等离子体设备中采用等离子体增强化学气相沉积法形成，在最底层的沉积层11主沉积结束后，引入等离子体轰击气体，控制其流速，并调整等离子体的制程温度、工艺压力以及射频频率等参数对形成的沉积层11进行等离子体轰击，从而不需要将半导体器件取出放置在其它设备中，减少污染。
本发明的一些具体示例中，沉积层11形成为掩膜层，例如沉积层11可以为氮化硅层、氧化硅层、氮氧化硅层或非晶硅(a-Si)层，在形成掩膜层过程中由于后续刻蚀工艺，从而更需要掩膜层表面更加平整以提高掩膜层形成掩膜的效果和后续刻蚀效果。
具体地，多层沉积层11可以包括第一掩膜层和第二掩膜层，在形成多层沉积层11的步骤中包括：于半导体衬底1表面形成第一掩膜层，对第一掩膜层表面进行等离子体轰击以击破第一掩膜层的气泡13；于通过等离子体轰击后的第一掩膜层表面形成第二掩膜层，对第二掩膜层表面进行等离子体轰击以击破第二掩膜层的气泡13。这样通过对第一掩膜层和第二掩膜层分别进行等离子体轰击，从而能够使得具有掩膜层的半导体器件的表面更加致密平整，有利于提高半导体器件表面的光学性能和后续刻蚀效果。
可选地，最底层的沉积层11可形成为含硅氢键的硅化合物层，在对最底层的沉积层11进行等离子轰击时，采用硼烷气体进行等离子体轰击，硅氢键断裂以形成键能稳定的硼氢键。具体地通过硼烷气体对含有硅氢键的含硅化合物层进行等离子体轰击，硼烷中的硼离子解离成等离子体，轰击沉积层11表面，促进沉积层11表面的硅氢键的断裂解离，并取代硅氢键中的硅，形成具有短键长高健能的硼氢键，不仅使得沉积层11表面更加致密平整，而且由于形成相比硅氢键更加稳定的硼氢键，能够使得沉积层11表面性能更好。
可选地，在对最底层的沉积层11进行等离子体轰击后，最底层的沉积层11的表面形成含硼氢键的硅化合物层，在于最底层的沉积层11表面形成其它沉积层的步骤中，其它沉积层形成在硼氢键的硅化合物层的表面，从而使得形成在硼氢键的硅化合物层的表面的其它沉积层也能够更加平整，以进一步地提高半导体器件的性能。
下面以硬掩模层工艺中形成的沉积层11为氮化硅层为例对本发明实施例的半导体器件的制备方法进行具体地描述。
采用等离子体增强化学气相沉积法在半导体衬底1的表面形成最底层沉积层11即氮化硅层，具体可采用硅烷气体和氨气作为原料气体，硅烷气体和氨气的比例可以为：SIH4/NH3≈1.5，制程温度400℃-480℃,工艺压力在2-7Tor，射频频率设定在70-100W，适当降低工艺压力,加速残留气体的抽离。
在主沉积结束时，引入硼烷气体作为后续处理气体，硼烷气体的流速为2000～5000sccm，制程温度为400～480℃，工艺压力在2～5Tor，射频功率为300～800W。在惰性气体如氩气作用下，氩气流速为1000～3000sccm，硼离子解离成等离子体，轰击半导体器件的沉积层11表面，使得硅氢键受到轰击断裂，硼离子与断裂的氢结合，形成更加稳定的短键长高键能的硼氢键，解离的硅被氮化进而形成大量的硅氮键，由此在沉积层11的表面可形成更加致密的含硼氢键的氮化硅层12，不仅使得沉积层11表面的气泡13中的残留气体逸出，而且使得沉积层11表面更加致密平整，改善了沉积层11表面的性能。
然后在含有硼氢键的氮化硅层12的表面后续形成其它沉积层11，并图形化多层沉积层11和硼氢键的氮化硅层12以在多层沉积层11和半导体衬底1内形成刻蚀凹槽，从而能够避免后续刻蚀形成侧蚀和颗粒遮挡刻蚀凹槽的问题。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (15)

1.一种半导体表面缺陷的处理方法，其特征在于，包括：
将半导体器件置于等离子体处理设备内，所述半导体器件包括衬底和形成在所述衬底表面的沉积层，所述沉积层形成有气泡；
对所述沉积层表面进行等离子体轰击以将所述气泡击破，使得所述沉积层表面平整。
2.根据权利要求1所述的半导体表面缺陷的处理方法，其特征在于，所述沉积层形成为含有硅氢键的含硅化合物层，在对所述沉积层表面进行等离子体轰击时采用硼烷气体进行等离子体轰击，所述硅氢键断裂并形成键能稳定的硼氢键。
3.根据权利要求2所述的半导体表面缺陷的处理方法，其特征在于，在对所述沉积层表面进行等离子体轰击后，于所述沉积层表面形成覆盖所述沉积层的含硼氢键的氮化硅层。
4.根据权利要求2所述的半导体表面缺陷的处理方法，其特征在于，所述硼烷气体的流速为2000～5000sccm，所述制程温度为400～480℃，工艺压力在2～5Tor。
5.根据权利要求2所述的半导体表面缺陷的处理方法，其特征在于，所述射频功率为300～800W。
6.根据权利要求2所述的半导体表面缺陷的处理方法，其特征在于，在于所述衬底表面形成沉积层的步骤中，采用硅烷气体与氨气为形成所述沉积层的原料气体，所述气泡内具有形成所述沉积层后的残余生成气体，在将所述气泡击破后还包括以下步骤：将所述气泡击破后释放的气体抽除。
7.根据权利要求2所述的半导体表面缺陷的处理方法，其特征在于，所述沉积层为氮化硅层、氧化硅层、氮氧化硅层或非晶硅(a-Si)层。
8.根据权利要求2所述的半导体表面缺陷的处理方法，其特征在于，在对所述沉积层表面进行等离子体轰击时，采用惰性气体为载气。
9.根据权利要求8所述的半导体表面缺陷的处理方法，其特征在于，所述惰性气体的流速为1000～3000sccm。
10.一种半导体器件的制备方法，其特征在于，包括：
提供半导体衬底；
采用等离子体增强化学气相沉积法于所述半导体表面形成层叠设置的多层沉积层，所述沉积层形成有气泡；
在形成多层所述沉积层时，至少对位于最底层的所述沉积层进行等离子体轰击以击破所述气泡后，于所述最底层的沉积层表面形成其它沉积层；
图形化所述多层沉积层。
11.根据权利要求10所述的半导体器件的制备方法，其特征在于，所述最底层的沉积层形成为含硅氢键的硅化合物层，在对所述最底层的沉积层进行等离子轰击时，采用硼烷气体进行等离子体轰击，所述硅氢键断裂以形成键能稳定的硼氢键。
12.根据权利要求11所述的半导体器件的制备方法，其特征在于，在对所述最底层的沉积层进行等离子体轰击后，所述最底层的沉积层的表面形成含硼氢键的硅化合物层，在于所述最底层的沉积层表面形成其它沉积层的步骤中，所述其它沉积层形成在所述硼氢键的硅化合物层的表面。
13.根据权利要求10所述的半导体器件的制备方法，其特征在于，所述沉积层形成为掩膜层。
14.根据权利要求13所述的半导体器件的制备方法，其特征在于，所述多层沉积层包括第一掩膜层和第二掩膜层，在形成所述多层沉积层的步骤中包括：于所述半导体衬底表面形成所述第一掩膜层，对所述第一掩膜层表面进行等离子体轰击以击破所述第一掩膜层的气泡；于通过等离子体轰击后的所述第一掩膜层表面形成所述第二掩膜层，对所述第二掩膜层表面进行等离子体轰击以击破所述第二掩膜层的气泡。
15.根据权利要求10所述的半导体器件的制备方法，其特征在于，所述形成多层沉积层和对所述沉积层进行等离子体轰击在同一反应腔室进行。
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