TWI289329B - Method and apparatus for controlling spacer width - Google Patents

Abstract

The present invention provides a method and an apparatus for controlling spacer width. The method includes the following steps: forming an oxidation layer, a nitride layer and a second oxidation layer on a semiconductor substrate having the gate structure to cover the upper portion and side walls of the gate structure; using the nitride layer as an etching stop layer to perform anisotropic etching on the second oxidation layer so as to form a residual second oxidation layer on a side wall of the gate structure, wherein the width between the side wall of the gate and the edge of the residual second oxidation layer is t, which is smaller than the width of the target spacer; using the first oxidation layer as an etching stop layer to perform anisotropic etching on the nitride layer so as to form a residual nitride layer on the side wall of the gate; removing the first oxidation layer and the second oxidation layer to leave only a first spacer, formed by the residual first oxidation layer and the residual nitride layer, on the side wall of the gate structure; and finally forming a second spacer having the width of T-t on the semiconductor substrate of the side wall of the first spacer. Since the present invention first forms the first spacer having a width smaller than a predetermined target spacer width (T) before forming the rest of the spacer to make up the target spacer width, the spacer width can be controlled effectively for not only fabricating an element of good electric stability but also preventing any bridging generated between the gate and the source/drain or any electric leakage after a subsequent metallic silicide process.

Description

1289329 ----ΜΜί_5_年-...月日条正五、发明说明(1) 少 [Field of the Invention] The present invention relates to a method and apparatus for forming a spacer, and more particularly to a method for seeding a spacer The device can effectively control the width of the spacer, so that an electrically stable component can be obtained. BACKGROUND OF THE INVENTION With the shrinking of semiconductor integrated circuits, the minimum line width (CD) of components has been reduced from 〇· 25 /ζιη to 〇· i 8 , even 〇· 13 /zm. As the minimum line width of the component decreases, the ratio of the CD of the spacer on the gate side to the (3) layer of the gate of the gate increases. That is to say, the minimum line width of the components decreases, and the proportion of the spacers becomes larger and larger. Therefore, the influence of the spacer on the electrical properties of the component is also increasing. Traditionally, spacers of 0 · 2 5 // m components have been deposited with only one layer of tantalum nitride having a thickness of up to 2,500 Å, and then dry etched to form a 'gap wall. However, the deposition of such a thick tantalum nitride requires a high temperature, and if it is for a 〇. 1 8 # m or 0 · 1 3 // m element, the method of forming a spacer by using a high-temperature deposition thick gas enthalpy is also used. Damage to components ^ Therefore, for 〇·1 8 //in or 〇·. 1 3 /zm components, the composite spacer method is generally used, and the lower temperature is used. A thinner insulating layer. Figures la to 1d show a conventional method of manufacturing a composite spacer. First, referring to the first drawing, a semiconductor substrate 1 has a gate structure 6 〇 ' which includes a gate emulsification layer 62 and a polycrystalline chop layer 64. A first oxide layer 2, a nitride layer 24, and a second oxide layer 2 6 are sequentially formed on the semiconductor substrate 10 to cover the gate structure 6 〇.

0503-6921 twfl (n) ; tsmc2001-08^8; JamnGwo.pt c 1289329 Amendment -------- Case No. 91106715 5th, 5th, invention description (2) Jin then 'Please refer to Figure lb, with nitrogen The layer 24 is an etch stop screen, and the second oxide layer 26 is removed by dry etching, and the nitride layer 24 is turned on. At this time, the singularity on the sidewall is a splicer. Referring to the lc diagram, the first oxide layer 22 is used as an etch stop layer and the spacers 6 6 a are used as a hard mask for dry etching. Nitriding sound 24 ^ while forming a residual nitriding layer on the sidewall of the first oxide layer 22 =. At the same time, the spacers 26a are also etched away to form the spacers 26b. Next, referring to the figure Id, performing hydrofluoric acid (HF) etching to remove the first oxide layer 22 and the spacers 26b leaving the residual first oxide layer 22a remaining underneath, In the above-described conventional method of forming a composite spacer, the width A of the composite spacer C on the sidewall of the gate 6 is determined by the width of the spacer 26a (see b)). That is, the width A of the composite spacer c is a technique determined by the dry etching process for removing the second oxide layer, and the shape of the spacer 26a (pr〇fUe) is difficult to control. 'The width is very unstable. This makes the width A of the composite gap often unable to reach the width of the target spacer. Therefore, the electrical properties of the components are also difficult to control and are very unstable. Moreover, due to the gap on the sidewall of the gate, the wall = width is unstable, so that after the metal germanide process is performed, bridging phenomenon between the gate and the source/drain is easily caused, resulting in leakage. [Invention and Summary] In view of the above, it is an object of the present invention to provide a spacer for forming 0503-6921 twfl(n); tsnic2001 -0848; JamnGwo.pt c page 6 !289329

Correction Λ η : Method 2 This can control the width of the spacer to achieve stable components while avoiding bridging. Another object of the present invention is to provide a device for forming a spacer. In order to achieve the above object of the present invention, the spacer formed by the present invention is sequentially formed on a semiconductor substrate having a gate structure thereon - a layer, a nitride layer, and a second oxide layer to cover the gate. Pole structure: and side walls. Then, the nitride layer is used as a stop layer, and the second layer is anisotropic etching, and a residual layer is formed on the sidewall of the gate structure: an emulsion layer, and (1) a sidewall to a residual second oxide. At the edge of the layer: = flute, the value of t is smaller than the target gap width (τ). Then see = the oxide layer is the memory stop layer, the nitride layer is anisotropic, and the residual nitride layer is formed on the sidewall of the gate. Removing the second layer of dioxide, 'so that the sidewall of the interpole structure: left; the sum, leaving the first spacer formed by the nitride layer from the second; on the side of the semiconductor substrate, forming a width (τ- t) ~ only brother -= wall: then make up the gap that forms insufficient width, the size is small, the width is J, and the width of the gap is 芩: 芩 ! ! 具体 具体 具体 ! ! 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体a gap forming device, using the width of the two gaps (Τ) as a small first door, the visibility of the first door, the target, the Ning, the wilderness, the younger brother, a gap wall; a measuring device for measuring I the second: t width Ο); a second spacer forming device, forming a second spacer on the sidewall of the wall of the f = town, and according to the width of the -亍C _ gap t) determining the formation of the second spacer wall - w _ and - the data transmission device for adding the measurement, ~. two -------------

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_.Uwf 1(8); tsmc2〇〇^^^T 1289329 ΜΜ 9ΐιηβ7ΐς V. Description of the invention (4) The width of the first gap wall of the meniscus correction is transmitted to the second gap wall shape. According to another preferred embodiment of the present invention The device of the wall width includes: a first spacer wall forming device: a gap is formed on the sidewall of the gate structure on the body substrate, and a width two in-half is formed to determine the first spacer Width (1):: 襄 forming device: it includes a deposition device and a smear, = two walls dare to conformally form an insulating layer on the semiconductor substrate, the b-type structure and the first-gap Determining the thickness (w) of the insulating layer according to the measured yoke wall:::pole (t), so that w = , see the wide device for non-directional (four) the insulating layer to make the etch ^ The second spacer having a width of (T_t) remains on the wall; and the width of the first spacer (1) is transmitted by the 曰 and the two-pass ' =. ', ', main μ, providing a one-foot (10) integrated circuit comprising a plurality of electro-crystals:, medium-to-one transistor comprising: a semiconductor substrate; a gate structure on the substrate; One of the first two §^(target) falFV# visibility (T) is small on the sidewall of the gate structure, and the first spacer is formed by an oxide layer on the sidewall of the gate structure and a nitride layer on the sidewall of the north layer of oxygen forms a second spacer wall standing on the sidewall of the first spacer wall, the width of which is described above, and the present invention first forms a specific gap of the target spacer (τ ) is small = first spacer S1, and then the width (t) actually formed by the first spacer S1 is measured, and then the gap 不足 503-692ltwfl(n) which is insufficiently formed according to the width difference (T-1) ;tsmc2001-〇848;JamnGwo.ptc i 1289329 Amendment number 91106715 V. Invention description (5) Wall part. In this way, the stable component of the bucket can be effectively approved, and the width can be obtained, so that the electrical property can be obtained. [Example] ' ¥ 2 a to 2 f shows the basis according to Taisu s p> ^ ^ .X , , , A preferred embodiment of the present invention forms a ^ a month, and the semiconductor substrate 100 has a gate lion 0, which includes a gate oxide layer 62D and a polycrystalline stone layer 640. The f-conductor substrate 1GG± is sequentially compliantly formed with a first oxide layer 20, a nitride layer 240, and a second oxide layer 260 for covering the upper and sidewalls of the gate structure 600. The first oxide layer 22 may be TEOS-Si 2 deposited by a CVD method and may have a thickness of 100 A to 200 A, for example, ι 50 Å. The nitride layer 24 〇 may be tantalum nitride deposited by CVD method, and may have a thickness of 2 〇〇 A to 4 〇〇 A, for example, 3 〇〇 A . The second oxide layer 260 may be te 〇 S-Si 〇 2 deposited by a CVD method and may have a thickness of 800 Å to 1 2 0 0 A, for example, 1 〇 〇 〇 a. Next, referring to FIG. 2b, the nitride layer 240 is used as an etch stop layer, and the second oxide layer 260 is anisotropically etched, and a spacer 2 60a is formed on the sidewall of the gate structure 6? . If it is assumed that the width of the target gap is (T), the width (t) of the edge of the gate to the edge of the spacer 26 〇a should be controlled to be smaller than the target gap width (τ). . Then, please refer to Fig. 2c, the first oxide layer 22 is used as the stop layer, and the spacers 26 0a are used as the hard mask, and the nitride layer 24 is subjected to non-& A residual nitride layer 2 4 ^ is formed on the sidewall of the electrode. At the same time, the gap wall 210 will also be etched away to form the spacers 2 6 〇 b. Next, please refer to the 2d figure, with an isotropic etching method (for example, to grab 0503-69211wf1 (η); t smc2001-0848; JamnGwo.pt c page 9 1289329 i No. 91106715_^5, invention description ( 6) wet etching) removing the first oxide layer 220 and the spacers 260b such that the remaining first oxide layer 22a and the residual nitrogen sigma layer 240a remain on the sidewalls of the gate structure 600 The first spacer S1 is formed. The width (7) of the first spacer S1 is the wide sound of the edge of the gate 600 to the edge of the spacer 2600 a (Fig. 2b). Moreover, it is difficult to directly make the width of the first gap 31 reach the target gap wall. Therefore, the main concept of the present invention is to form a ratio of the target & gap width (T) to j, first. a gap wall si, and then measuring the width (t) of the first spacer wall si actually formed, and then forming a gap portion of insufficient width according to the width difference (T-q. y see Figures 2e and 2f, To illustrate the method of filling the gap portion of the insufficient width. Please refer to Figure 2e first, and conformally form an insulating layer 3 厚度 on the semiconductor substrate 1〇〇 to cover the gate structure. 6 G 〇 and the first spacer S1. The thickness of the insulating layer 300 ((1) is determined by the target clearance (τ) and the width (ΐ) of the first spacer S1, that is, two τ- The insulating layer 300 can be a nitride, for example, the thickness of the 沉积' deposited by the cyD method can be between 150 A and 45 0 λ. The larger the next buckwheat is the 2 f map, with anisotropy. Etching or removing the insulating layer 300 by engraving, so that the insulating layer 3 残留 remains on the first gap wall The gap wall is made by the anisotropy = the width of the portion of the second spacer S2 remaining in the insulating layer 300, that is, the thickness w formed by the original insulating layer. The finally obtained spacer second and second spacer Si And the second gap is formed, the total width (t ^ : the gap width (T) is the same." S ' 2f shows a part of the CM0S complex y of the current day and month, the figure t display 0503-6921 t'vfl (n); tsmc200i-0848; JaninGwo (20060809) .ptc p. 1289329 Case 91106715 V. Description of the invention (7) The electric body shown includes a semiconductor substrate 1〇〇 on the substrate 1 a gate structure 600, a first spacer s 1 ' located on the sidewall of the gate structure 6 and a second spacer s 2 on the sidewall of the first spacer S1. The width of the spacer S1 is t, the value of t is smaller than the target gap width (T), and the first spacer S1 is composed of a residual first oxide layer located on the sidewall of the gate structure 6 22 0a and a nitride layer 240 a on the sidewall of the remaining first oxide layer 20 20 a. The width of the second spacer S 2 is ¥, that is, (T-1) The invention also provides a device for controlling the width of a spacer. The following is a process for forming a composite spacer on a sidewall of a gate structure on a semiconductor substrate to illustrate a device for controlling wall width in accordance with a preferred embodiment of the present invention. Please refer to FIG. 3. According to a preferred embodiment of the present invention, the apparatus for controlling the width of the spacer includes: a first spacer forming device 52, a measuring device 54, and a second spacer forming device. 7〇, and the two-package transmission device, please read the process of 2d to 2f and the device of Figure 3. First, a semiconductor substrate 1 having a gate structure 600 is fed into a spacer forming device 52 to form a width-to-target spacer width on the sidewall of the gate structure 6? T) is the first small gap S1, ^ is shown in the figure. The measuring device 54 can be used to determine the width of the first spacer 51. The measured width (t) is entered into the data transfer device 56, and the data transfer device 56 can then transmit the width (t) data to the second spacer step 70. Evening windbreaker

1289329 _mm, 91106715_年月日 Yongzheng V. Inventive Note (8) Set 74. The semiconductor substrate is fed into a deposition device 72 to conformally form an insulating layer 300 on the semiconductor substrate to cover the gate structure 60 〇 and the first spacer S1. The deposition thickness (w) of the insulating layer 30 0 is determined in accordance with the measured width (t) of the first spacer from the data transfer device 56 such that w = T-t. Next, the rich conductor substrate is fed into the etching device 74, and the insulating layer is anisotropically etched so that the insulating layer remains on the sidewall of the first spacer S1. Due to the anisotropic etching method, the width of the portion of the second spacer S2 remaining in the insulating layer 3 is equal to the thickness w originally formed. The resulting spacer is formed by the first spacer si and the second spacer, the total width (t + w ) being the same as the target spacer width (τ). In summary, the present invention first forms a first spacer S1 that is smaller than the target spacer width (τ), and then determines that the first spacer S1 actually forms a 'white, degree (ΐ)', and then The difference (T - ΐ) complements the door that forms less than the width: the wall portion. In this way, the width of the spacer can be effectively controlled, so that a stable component can be obtained, and bridging between the gate and the gate after the subsequent metal telluride process can be avoided to prevent leakage. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and the present invention may be modified and retouched without departing from the spirit and scope of the present invention. Protection Fan = The one defined in the scope of the patent application attached is subject to change. 'dry circumference

。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 : Figures 1 to 1 d show the manufacturing method of the conventional composite spacer. Figures 2a through 2f show a method of forming a gap wall in accordance with a preferred embodiment of the present invention. Figure 3 shows a device for forming a spacer wall in accordance with a preferred embodiment of the present invention. [Description of symbols] Conventional technology is poem 10 0~ semiconductor substrate; 6 0~ gate structure; 62~ gate oxide layer; 64~ polysilicon layer; 22~ first oxide layer; 22a~ residual first oxidation Layer; 2 4~ nitride layer; 24a~ residual nitride layer; 26~ second oxide layer;

Ma ~ spacer; 2 6b ~ spacer; C ~ composite spacer; A ~ composite spacer width. The invention is a '10 0~ semiconductor substrate;

0503-69211wf1(η);ΐ smc2001-0848;J amnGwo.ptc Page 13 1289329 __ Case No. 91106715_年月曰修 is a simple illustration of the structure 6 0 0~ gate structure; 6 2 0~ gate oxide layer 64 0~polycrystalline germanium layer; 2 2 0~first oxide layer; 22 0a~ residual first oxide layer; 2 4 0~nitriding layer; 2 4 0 a~ residual nitride layer; 26 0~ Second oxide layer; 26 0a~gap; 26 0b~gap; S1~first spacer; S2~second spacer; T~target spacer width; t~first spacer S1 width; 3 0 0~insulating layer; w~insulating layer thickness; 52~first spacer forming device; ~measuring device; 70~second spacer forming device; '56~data transfer device; 2~deposition device; 74~etching Device.

0503-69211wf1(η);t smc2001-0848;J amnGwo.p t c第14页

Claims (1)

1289329 Case No. 91106715 VI. Scope of Application for Patent Revision A method of controlling a width of a spacer, comprising: a nitride layer::t conductor substrate having a gate structure thereon, a first oxide layer sequentially formed on the + germanium substrate, and a dioxide layer to cover the upper and side of the gate structure, the nitride layer is used as a stop layer for the engraving, the second oxide layer is directional, and the gate is in the gate of the gentleman 槿f / 仃非寺, the second portion of the sidewall of the mouth structure is formed, and the edge layer of the second oxide layer remaining to the residual gate layer is smaller than the target gap width (τ); and is t , t = the first oxide layer is stopped, I's the nitride layer, and the second nitride layer is formed on the sidewall of the gate; the first oxide layer and the second oxide layer are removed. The remaining part of the remaining oxide layer and the residual nitride layer; the wall spacer; and the composition of the brother's formation width is the first oxygen of the first oxygen, wherein the second gas - a second spacer on the semiconductor substrate (T - ΐ) of the first spacer sidewall. 2 · as claimed The method described in the first aspect: the chemical layer is TE〇s-Si% deposited by the CVD method. 3. The method according to the method of claim 1 is characterized in that the thickness of the layer is 1 in 2 to 2 〇 4. The method according to claim 1, wherein the layer is iTE 〇 s - μ% deposited by the CVD method. 5. The method according to the first aspect of the patent application, the thickness of the layer is 8Into 12〇〇a. / 6· The method described in claim 1 of the scope of the patent, wherein the 0503-69211wf1(η);t smc2001-0848;J amnGwo.p tc Page 15 Ϊ289329 Λ_日 Correction 丄 9iinfi7iR y, the patent application scope is tantalum nitride deposited by CVD method. The method of claim 1, wherein the method of the nitride layer-gas range according to item 1 wherein the removal of the first wall of the oxide layer is on the gate structure side The step of forming the first interstitial soil on the wall is carried out by an isotropic method. The method of claim 1, wherein the step of the first spacer wall and the step of providing the spear includes forming a width of (7沁) on the bottom. a second gap wall thickness, the thickness of the body substrate is compliantly formed (b), one of the insulating layers k is retanning the gate structure and the first spacer; and the anode layer is removed to make the insulating layer A second gap wall having a width of (τ-t) is left on the waste side of the first gap. And a slave, wherein the barrier layer ‘where the insulation ‘where the insulation is removed ’, wherein the removal, 1 0. The method of claim 9 is a nitride. 11. The method described in the first paragraph of the patent application is a tantalum nitride deposited by a CVD method. 12. The method described in claim 10 of the patent application layer has a degree of difference between 1 500 and 4 5 () A. 1 3. The method of claim 9, wherein the step of the edge layer is an anisotropic etching method. 14. The method of claim 13, wherein the step of insulating the layer is performed by dry etching. 1 5 · A CMO S integrated circuit comprising a plurality of transistors, wherein Page 16 0503 - 69211wf 1 (η); t smc2001 -0848; J amnGwo. ptc 1289329 A correction ~ _ case number gil0671Pi Year 6th, the patent application range at least one transistor includes: a semiconductor substrate; located on the substrate One of the upper gate structures; one of the first spacers on the sidewall of the gate structure, the twist is t, and the t value is greater than the target gap width (and the first spacer is located at the One of the sidewalls of the gate structure is formed by a nitride layer on the sidewall of the oxide layer; the second vaporization layer is located on the sidewall of the first spacer wall (d~t) The visibility is 1 6 · The CMOS product % as described in claim 15 of the patent application. The oxide layer is TEOS-SiO 2 deposited by the CVD method. ' 17 · As claimed in item 15 In the CMOS integrated body %, the thickness of the oxide layer is loo A to 200 A. "Land, 18. The CMOS integrated body according to claim 15 of the patent application is in the CVD layer. The nitriding stone deposited by the law. ΐΐ4 - 士斗\9. If applied, the CMOS integrated lightning path mentioned in the 15th patent range The thickness of the nitride layer is from 2 〇0 A to 4 〇〇A. '; 20. The second spacer is an insulating layer in the integrated body of (3) (10) according to claim 15 of the patent application. The CMOS integrated circuit according to claim 20, wherein the insulating layer is a nitride in the case of d. ^ 22. The integrated circuit of the &CM〇s integrated circuit according to the second item of claim 2, wherein the insulating layer is The tantalum nitride deposited by the CVD method. 23· (3) (9) as described in the second paragraph of the patent application, "j" Page 17 1289329 0503-6921twfl(n); tsmc2001-0848;JamnGwo.ptc 苐18 pages