CN108321204B - 开关元件及开关元件的制造方法 - Google Patents

开关元件及开关元件的制造方法 Download PDF

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CN108321204B
CN108321204B CN201711384307.6A CN201711384307A CN108321204B CN 108321204 B CN108321204 B CN 108321204B CN 201711384307 A CN201711384307 A CN 201711384307A CN 108321204 B CN108321204 B CN 108321204B
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layer
type semiconductor
semiconductor substrate
semiconductor layer
insulating film
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CN108321204A (zh
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山田哲也
大川峰司
森朋彦
上田博之
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Denso Corp
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Denso Corp
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Abstract

本发明提供开关元件及开关元件的制造方法，开关元件具备：半导体基板，具有第一n型半导体层、由外延层构成的p型的体层、通过体层而与第一n型半导体层分离的第二n型半导体层；栅极绝缘膜，覆盖跨及第一n型半导体层的表面、体层的表面及第二n型半导体层的表面的范围；及栅电极，隔着栅极绝缘膜而与体层相向。第一n型半导体层与体层的界面具有倾斜面。倾斜面以随着沿横向远离体层的端部而体层的深度变深的方式倾斜。倾斜面配置在栅电极的下部。

Description

开关元件及开关元件的制造方法
技术领域
本公开涉及开关元件及开关元件的制造方法。
背景技术
日本特开2009-147381号公报公开了具有第一n型半导体层(漂移区)、p型的体层、第二n型半导体层(源区)的开关元件。第二n型半导体层通过体层而与第一n型半导体层分离。栅电极隔着栅极绝缘膜而与将第一n型半导体层和第二n型半导体层分离的范围的体层相向。在所述开关元件中，第一n型半导体层与体层的界面具有以随着远离体层的端部而体层的深度变深的方式倾斜的倾斜面。倾斜面配置在栅电极的下部。
通过本申请发明者们的研究可知，通过在栅电极的下部的体层与第一n型半导体层的界面设置倾斜面，能够缓和向栅极绝缘膜施加的电场。
在日本特开2009-147381号公报的开关元件中，在栅电极的下部的体层与第一n型半导体层的界面设置倾斜面。但是，在日本特开2009-147381号公报中，体层由扩散层构成。在通过扩散层构成体层的情况下，从体层侧向第一n型半导体层侧产生杂质的扩散，因此倾斜面成为以向第一n型半导体层侧凸出的方式弯曲的形状。当这样倾斜面弯曲时，倾斜面相对地变窄，对向栅极绝缘膜施加的电场进行缓和的效果相对变小。因此，在本说明书中，提供一种能够更有效地缓和向栅极绝缘膜施加的电场的开关元件。
发明内容
本公开的第一形态的开关元件具备：半导体基板，具有第一n型半导体层、p型的体层及第二n型半导体层，该第一n型半导体层露出于所述半导体基板的表面，该p型的体层由露出于所述半导体基板的所述表面的外延层构成，该第二n型半导体层露出于所述半导体基板的所述表面、且通过所述体层而与所述第一n型半导体层分离；栅极绝缘膜，覆盖跨及所述第一n型半导体层的表面、所述第一n型半导体层与所述第二n型半导体层之间的所述体层的表面及所述第二n型半导体层的表面的范围；及栅电极，隔着所述栅极绝缘膜而与位于所述第一n型半导体层和所述第二n型半导体层之间的所述体层相向。所述第一n型半导体层与所述体层的界面具有倾斜面。所述倾斜面以随着沿横向远离所述体层的端部而所述体层的深度变深的方式倾斜。所述倾斜面配置在所述栅电极的下部。
在本公开的第一形态的开关元件中，在栅电极的下部的体层与第一n型半导体层的界面设置倾斜面。而且，在所述开关元件中，体层由外延层构成，几乎不会产生杂质从体层侧向第一n型半导体层侧的扩散。因此，根据所述开关元件的构造，能够在体层与第一n型半导体层的界面设置几乎不弯曲的倾斜面，能够得到相对宽的倾斜面。因此，根据所述构造，能够有效地缓和向栅极绝缘膜施加的电场。
在本公开的第一形态的开关元件中，可以是，所述倾斜面相对于所述半导体基板的所述表面的角度小于60°。
在本公开的第一形态的开关元件中，可以是，所述界面具有表层部界面，该表层部界面在所述栅电极的下部从所述半导体基板的所述表面向下方延伸、且相对于所述半导体基板的所述表面的角度为80°以上且90°以下，所述倾斜面位于所述表层部界面的下侧，所述倾斜面相对于所述半导体基板的所述表面的角度小于60°。
在本公开的第一形态的开关元件中，可以是，所述半导体基板包括至少两个所述体层和至少两个所述第二n型半导体层，所述栅极绝缘膜覆盖跨及所述第二n型半导体层的表面的一部分、所述第一n型半导体层中的位于两个所述体层之间的部分即间隔部的表面及所述体层的位于所述间隔部与所述第二n型半导体层之间的部分的表面的范围。
本公开的第二形态的开关元件的制造方法中，所述开关元件具备：半导体基板，具有第一n型半导体层、p型的体层及第二n型半导体层，该第一n型半导体层露出于所述半导体基板的表面，该第二n型半导体层露出于所述半导体基板的所述表面、且通过所述体层而与所述第一n型半导体层分离；栅极绝缘膜；及栅电极，隔着所述栅极绝缘膜而与位于所述第一n型半导体层和所述第二n型半导体层之间的所述体层相向，所述开关元件的制造方法包括以下步骤：在所述半导体基板的上表面形成具有开口的掩模；对所述开口内的所述半导体基板的上表面进行蚀刻而形成凹部；通过所述蚀刻将所述凹部形成为，所述凹部的侧面相对于所述半导体基板的上表面成为倾斜面，该倾斜面以随着沿横向远离所述凹部的端部而所述凹部的深度变深的方式倾斜；去除所述掩模；通过外延生长，使所述体层外延生长到所述半导体基板的上表面和所述凹部内；对所述半导体基板的上表面进行研磨；向所述体层的一部分选择性地注入n型杂质离子，形成所述第二n型半导体层；以覆盖跨及所述第一n型半导体层的表面、所述第一n型半导体层与所述第二n型半导体层之间的所述体层的表面及所述第二n型半导体层的表面的范围的方式形成所述栅极绝缘膜；以覆盖所述栅极绝缘膜的整个上表面的方式形成所述栅电极；以覆盖所述半导体基板的表面及所述栅电极的表面的方式形成层间绝缘膜；在设于所述层间绝缘膜的接触孔内形成接触插塞；在所述层间绝缘膜的上表面配置上部电极；及在所述半导体基板中的与形成所述层间绝缘膜的面相反的面配置下部电极。
附图说明
前述及后述的本发明的特征及优点通过下面的具体实施方式的说明并参照附图而明确，其中，相同的附图标记表示相同的部件。
图1是实施例1的MOSFET的纵向剖视图。
图2是表示具有相对宽的倾斜面的MOSFET的电场分布的图。
图3是表示比较例1的MOSFET的电场分布的图。
图4是表示比较例2的MOSFET的电场分布的图。
图5是对接通电阻进行比较的坐标图。
图6是对向栅极绝缘膜施加的电场进行比较的坐标图。
图7是实施例1的MOSFET的制造工序的说明图。
图8是实施例1的MOSFET的制造工序的说明图。
图9是实施例1的MOSFET的制造工序的说明图。
图10是实施例1的MOSFET的制造工序的说明图。
图11是实施例1的MOSFET的制造工序的说明图。
图12是实施例2的MOSFET的纵向剖视图。
图13是实施例2的MOSFET的制造工序的说明图。
具体实施方式
图1所示的MOSFET10具有GaN半导体基板12。GaN半导体基板12是以GaN(氮化镓)为主成分的半导体基板。
GaN半导体基板12具有多个源层40、多个体层42及漂移层44。
各源层40是n型区域，露出于GaN半导体基板12的上表面12a。
各体层42是p型区域，配置在对应的源层40的周围。各体层42覆盖对应的源层40的侧面和下表面。各体层42在与源层40相邻的范围，露出于GaN半导体基板12的上表面12a。
漂移层44是n型区域，配置于各体层42的下侧。而且，在一对体层42之间也配置漂移层44。以下，将漂移层44中的位于一对体层42之间的部分称为间隔部44a。间隔部44a有时被称为JFET区域。间隔部44a露出于GaN半导体基板12的上表面12a。而且，漂移层44露出于GaN半导体基板12的下表面12b的大致整个区域。漂移层44通过各体层42而与各源层40分离。
体层42与漂移层44之间的界面50是pn结面。在体层42与间隔部44a之间的部分的界面50设有倾斜面52。倾斜面52从GaN半导体基板12的上表面12a向斜下方延伸。倾斜面52延伸至体层42的底面。倾斜面52以随着沿横向(与上表面12a平行的方向)远离体层42的端部42a而体层42的深度(即，上表面12a与体层42的下端之间的距离)变深的方式相对于上表面12a倾斜。倾斜面52与上表面12a之间的角度θ(在体层42内测定的角度)小于60°。在体层42的底部，界面50与上表面12a大致平行地延伸。
在GaN半导体基板12的上表面12a配置有栅极绝缘膜28、栅电极26、层间绝缘膜24、接触插塞22及上部电极20。
栅极绝缘膜28覆盖GaN半导体基板12的上表面12a的一部分。栅极绝缘膜28覆盖跨及体层42附近的源层40的表面、源层40与间隔部44a之间的体层42的表面及间隔部44a的表面的范围。各体层42中的与栅极绝缘膜28相接的部分(即，源层40与间隔部44a之间的体层42的表层部)是形成沟道的沟道区42b。栅极绝缘膜28由例如氧化硅等绝缘体构成。
栅电极26配置在栅极绝缘膜28上。栅电极26隔着栅极绝缘膜28而与源层40、体层42(即，沟道区42b)及漂移层44(即，间隔部44a)相向。栅电极26通过栅极绝缘膜28而与GaN半导体基板12绝缘。
层间绝缘膜24将未被栅极绝缘膜28覆盖的范围的上表面12a覆盖。而且，层间绝缘膜24覆盖栅电极26的表面。层间绝缘膜24由例如氧化硅等绝缘体构成。
在层间绝缘膜24设有多个接触孔，在所述多个接触孔内设有接触插塞22。一部分接触插塞22在其下端与源层40连接，其他接触插塞22在其下端与体层42连接。
上部电极20配置在层间绝缘膜24上。上部电极20与各接触插塞22的上表面相接。上部电极20经由接触插塞22而与源层40及体层42连接。
在GaN半导体基板12的下表面12b配置有下部电极30。下部电极30与漂移层44连接。
当栅电极26的电位升高至栅极阈值(使MOSFET10接通所需的最小的栅极电位)以上时，电子被拉向体层42的沟道区42b，由此在沟道区42b形成沟道。通过沟道，将源层40与漂移层44连接，由此电子从源层40向漂移层44流动。在MOSFET10中，沟道区42b(即，体层42)是外延层，因此存在于沟道区42b的晶体缺陷少。因此，所述MOSFET10的接通电阻相对小。
另外，在MOSFET10中，位于沟道区42b的下侧的部分的界面50是倾斜面52。因此，通过了沟道区42b的电子如图1的箭头100所示，一边分散一边向下方流动。由此，也能进一步降低MOSFET10的接通电阻。
当栅电极26的电位下降为小于栅极阈值时，沟道消失，电子的流动停止。即，MOSFET10断开。当MOSFET10断开时，向界面50的pn结施加反向电压(即，漂移层44相比体层42成为高电位的电压)。因此，耗尽层从体层42向漂移层44扩展，漂移层44发生耗尽化。当漂移层44发生耗尽化时，在漂移层44的内部产生电位分布。电位分布跨及漂移层44及栅极绝缘膜28地产生。因此，跨及漂移层44和栅极绝缘膜28地施加电场。
图2～图4示出通过模拟而算出了MOSFET断开时的电位分布的结果。在图2～图4中，虚线表示等电位线。需要说明的是，图2示出模拟了实施例1的具有相对宽的倾斜面52的MOSFET的电位分布，图3、图4示出比较例1、2的MOSFET的电位分布。在图3所示的比较例1的MOSFET中，界面50不具有倾斜面52，体层42与间隔部44a之间的界面50相对于上表面12a而大致垂直地延伸。在图4所示的比较例2的MOSFET中，界面50具有倾斜面52，但是倾斜面52以向漂移层44侧凸出的方式弯曲，倾斜面52相对窄。在体层42由扩散层构成的情况下，即使在注入杂质的阶段设置相对宽的倾斜面52，在杂质活性化时p型杂质也会从体层42向漂移层44侧扩散，因此倾斜面52向漂移层44侧弯曲。其结果是，如图4那样，倾斜面52相对地变窄。在图3、图4中，与图2相比，在间隔部44a的上部的栅极绝缘膜28的附近，等电位线的间隔变密。根据图2～图4可知，如图2那样倾斜面52相对宽时，能缓和向栅极绝缘膜28施加的电场。
另外，图5、图6中，对图2的MOSFET与比较例1、2(图3、图4)的MOSFET的特性进行比较来表示。图5示出漏极‐源极间电压BV与接通电阻的关系。图6表示漏极‐源极间电压BV与向氧化膜施加的电场的关系。从图5可知，图2的MOSFET能得到与比较例1、2的MOSFET相等的接通电阻。而且，从图6可知，在漏极‐源极间电压相等的情况下，在图2的MOSFET中，与比较例1、2的MOSFET相比向栅极绝缘膜28施加的电场低。根据以上的结果，根据具有相对宽的倾斜面52的实施例1的MOSFET10，能够得到与比较例1、2的MOSFET相等的接通电阻，并且与比较例1、2的MOSFET相比能够抑制向栅极绝缘膜28施加的电场。
接下来，说明实施例1的MOSFET10的制造方法。首先，如图7所示，在GaN半导体基板12的上表面12a形成具有开口60的掩模58。接下来，对开口60内的GaN半导体基板12的上表面进行蚀刻，由此形成凹部62。此时，调整蚀刻条件，以使凹部62的侧面成为相对于GaN半导体基板12的上表面倾斜的(更详细而言，以随着远离凹部62的端部62a而凹部62的深度变深的方式倾斜的)倾斜面63的方式形成凹部62。例如，使掩模58的厚度在越接近开口60的位置处越薄，调整气体种类、压力、RF功率等条件而进一步减小掩模58与GaN半导体基板12的蚀刻率之差，由此能够形成倾斜面63。在此，以使倾斜面63与GaN半导体基板12的上表面之间的角度θ小于60°的方式形成凹部62。
接下来，去除掩模58，如图8所示，通过外延生长，使p型的GaN半导体层即体层42外延生长到GaN半导体基板12的上表面和凹部62内。以下，将包含漂移层44和体层42的整个GaN半导体层称为GaN半导体基板12。
接下来，通过CMP(ChemicalMechanicalPolishing：化学机械研磨)对GaN半导体基板12的上表面(即，体层42的表面)进行研磨。在此，如图9所示，使漂移层44的间隔部44a露出于GaN半导体基板12的上表面。而且，使体层42残存在凹部62内。
接下来，如图10所示，通过向体层42的一部分选择性地注入n型杂质离子而形成源层40。
接下来，如图11所示，形成栅极绝缘膜28。栅极绝缘膜28形成为覆盖跨及体层42附近的源层40的表面、源层40与间隔部44a之间的体层42的表面及间隔部44a的表面的范围。接下来，如图11所示，以覆盖栅极绝缘膜28的整个上表面的方式形成栅电极26。然后，通过形成层间绝缘膜24、接触插塞22、上部电极20及下部电极30而图1的MOSFET10完成。
如以上说明所述，在实施例1的MOSFET10中，体层42是外延层。因此，在形成体层42时，p型杂质从体层42向漂移层44几乎不扩散。因此，能够将界面50形成为与凹部62大致相同的形状。因此，通过将体层42形成为外延层，能够使倾斜面52成为所希望的形状。即，通过将体层42形成为外延层，能够抑制倾斜面52的弯曲，并使倾斜面52相对地变宽。因此，本实施例1的MOSFET10能够有效地缓和向栅极绝缘膜28施加的电场。
图12所示的实施例2的MOSFET在体层42与间隔部44a(即，漂移层44)之间的界面50具有表层部界面53和倾斜面52的点上与实施例1的MOSFET10不同。实施例2的MOSFET的其他结构与实施例1的MOSFET10相等。表层部界面53是界面50中的位于上表面12a附近的部分。表层部界面53与上表面12a之间的角度θ1为80°以上且90°以下。即，表层部界面53从上表面12a向下方大致垂直地延伸。倾斜面52配置在表层部界面53的下侧。倾斜面52的上端与表层部界面53的下端连接。倾斜面52以随着沿横向远离体层42的端部42a而体层42的深度变深的方式相对于上表面12a倾斜。倾斜面52与上表面12a之间的角度θ2小于60°。
在实施例2的MOSFET中，体层42是外延层，因此倾斜面52相对宽。因此，在实施例2的MOSFET中，能缓和向栅极绝缘膜28施加的电场。
另外，在实施例2的MOSFET中，在倾斜面52的上部设有表层部界面53。因此，在实施例1和实施例2中使间隔部44a的宽度相同的情况下，实施例2的从倾斜面52至源层40的距离比实施例1的从倾斜面52至源层40的距离长。在MOSFET接通的状态下，在包含倾斜面52的界面50的周边局部性地产生耗尽层。在实施例2的MOSFET中，在接通状态下，在倾斜面52的周边产生的耗尽层与源层40之间的距离比实施例1的MOSFET10宽。因此，在实施例2的MOSFET中，短沟道效果难以产生。因此，根据实施例2的构造，能够进一步抑制由短沟道效果引起的栅极阈值的变动。
另外，如实施例2那样如果设置相对于上表面12a大致垂直地延伸的表层部界面53，则在量产时在MOSFET之间，间隔部44a的上表面12a的宽度(即，在实施例2中，位于间隔部44a的两侧的表层部界面53之间的宽度)难以产生变动。当间隔部44a的宽度相对宽时，更容易向间隔部44a的上部的栅极绝缘膜28施加高电场。根据实施例2的MOSFET的构造，能抑制间隔部44a的宽度的变动，因此能够稳定地抑制向栅极绝缘膜28施加的电场。
实施例2的MOSFET形成图13所示的形状的凹部62，然后，能够通过实施与实施例1同样的工序来制造。首先与实施例1同样地如图7那样形成凹部62，然后均匀地沿着GaN半导体基板12的厚度方向以蚀刻进展的条件进一步对凹部62进行蚀刻，从而能够得到图13所示的形状的凹部62。
需要说明的是，在上述的实施例1、2中，关于MOSFET进行了说明，但是也可以在IGBT适用本说明书公开的技术。通过向下部电极30与漂移层44之间追加p型层，能够得到IGBT的构造。
另外，在上述的实施例1、2中，使用了GaN半导体基板作为半导体基板。然而，也可以在具有以SiC、Si为主成分的半导体基板的开关元件中适用本说明书公开的技术。其中，本说明书公开的技术在使用难以控制GaN、SiC等杂质的扩散的半导体基板的情况下特别有效。
对于实施例的结构要素与技术方案的结构要素的关系进行说明。实施例的漂移层44是第一n型半导体层的一例。实施例的源层40是第二n型半导体层的一例。
关于本公开的技术要素，以下进行说明。
在本公开的一例的开关元件中，第一n型半导体层与体层的界面具有在栅电极的下部从半导体基板的表面向下方向延伸、且相对于半导体基板的表面的角度为80°以上且90°以下的表层部界面。倾斜面位于表层部界面的下侧。倾斜面相对于半导体基板的表面的角度小于60°。
需要说明的是，在本说明书中，界面(即，表层部界面或倾斜面)相对于半导体基板的表面的角度是指在体层内计测的角度。
以上，详细地说明了实施方式，但是它们只不过是例示，没有对权利要求书进行限定。权利要求书记载的技术包括对以上例示的具体例进行了各种变形、变更的情况。本说明书或附图说明的技术要素是单独或者通过各种组合来发挥技术有用性的要素，没有限定为申请时权利要求记载的组合。而且，本说明书或附图例示的技术是同时实现多个目的的技术，实现其中的1个目的自身就具有技术有用性。

Claims (3)

1.一种开关元件，其特征在于，包括：
半导体基板，具有第一n型半导体层、p型的体层及第二n型半导体层，所述第一n型半导体层露出于所述半导体基板的表面，所述p型的体层由露出于所述半导体基板的所述表面的外延层构成，所述第二n型半导体层露出于所述半导体基板的所述表面、且通过所述体层而与所述第一n型半导体层分离；
栅极绝缘膜，覆盖跨及所述第一n型半导体层的表面、所述第一n型半导体层与所述第二n型半导体层之间的所述体层的表面及所述第二n型半导体层的表面的范围；及
栅电极，隔着所述栅极绝缘膜而与位于所述第一n型半导体层和所述第二n型半导体层之间的所述体层相向，
所述第一n型半导体层与所述体层的界面具有倾斜面，所述倾斜面以所述体层的深度随着沿横向远离所述体层的端部而变深的方式倾斜，所述倾斜面配置在所述栅电极的下部，
所述界面具有表层部界面，所述表层部界面在所述栅电极的下部从所述半导体基板的所述表面向下方延伸、且相对于所述半导体基板的所述表面的角度为80°以上且90°以下，
所述倾斜面位于所述表层部界面的下侧，
所述倾斜面相对于所述半导体基板的所述表面的角度小于60°。
2.根据权利要求1所述的开关元件，其特征在于，
所述半导体基板包括至少两个所述体层和至少两个所述第二n型半导体层，
所述栅极绝缘膜覆盖跨及所述第二n型半导体层的表面的一部分、所述第一n型半导体层中的位于两个所述体层之间的部分即间隔部的表面及所述体层的位于所述间隔部与所述第二n型半导体层之间的部分的表面的范围。
3.一种开关元件的制造方法，所述开关元件具备：
半导体基板，具有第一n型半导体层、p型的体层及第二n型半导体层，所述第一n型半导体层露出于所述半导体基板的表面，所述第二n型半导体层露出于所述半导体基板的所述表面、且通过所述体层而与所述第一n型半导体层分离；
栅极绝缘膜；及
栅电极，隔着所述栅极绝缘膜而与位于所述第一n型半导体层和所述第二n型半导体层之间的所述体层相向，
所述开关元件的制造方法的特征在于，包括以下步骤：
在所述半导体基板的上表面形成具有开口的掩模；
对所述开口内的所述半导体基板的上表面进行蚀刻而形成凹部，通过所述蚀刻将所述凹部形成为，所述凹部的侧面相对于所述半导体基板的上表面成为倾斜面，所述倾斜面以所述凹部的深度随着沿横向远离所述凹部的端部而变深的方式倾斜；
去除所述掩模；
通过外延生长，使所述体层外延生长到所述半导体基板的上表面和所述凹部内；
对所述半导体基板的上表面进行研磨；
向所述体层的一部分选择性地注入n型杂质离子，形成所述第二n型半导体层；
以覆盖跨及所述第一n型半导体层的表面、所述第一n型半导体层与所述第二n型半导体层之间的所述体层的表面及所述第二n型半导体层的表面的范围的方式形成所述栅极绝缘膜；
以覆盖所述栅极绝缘膜的整个上表面的方式形成所述栅电极；
以覆盖所述半导体基板的表面及所述栅电极的表面的方式形成层间绝缘膜；
在设于所述层间绝缘膜的接触孔内形成接触插塞；
在所述层间绝缘膜的上表面配置上部电极；及
在所述半导体基板中的与形成所述层间绝缘膜的面相反的面配置下部电极，
所述第一n型半导体层与所述体层的界面具有表层部界面，所述表层部界面在所述栅电极的下部从所述半导体基板的所述表面向下方延伸、且相对于所述半导体基板的所述表面的角度为80°以上且90°以下，
所述倾斜面位于所述表层部界面的下侧，
所述倾斜面相对于所述半导体基板的所述表面的角度小于60°。
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