TWI664729B - 切換元件及製造切換元件的方法 - Google Patents

切換元件及製造切換元件的方法 Download PDF

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TWI664729B
TWI664729B TW106143067A TW106143067A TWI664729B TW I664729 B TWI664729 B TW I664729B TW 106143067 A TW106143067 A TW 106143067A TW 106143067 A TW106143067 A TW 106143067A TW I664729 B TWI664729 B TW I664729B
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layer
type semiconductor
semiconductor substrate
semiconductor layer
insulating film
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TW106143067A
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TW201826539A (zh
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山田哲也
大川峰司
森朋彥
上田博之
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日商豐田自動車股份有限公司
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  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Thyristors (AREA)

Abstract

一種切換元件包括一半導體基材，其包括一第一n-型半導體層、一由晶膜層所構成的p-型主體層、及一第二n-型半導體層，其與該第一n-型半導體層被該主體層分隔開、一閘極絕緣膜，其覆蓋一橫跨該第一n-型半導體層的表面、該主體層的表面、及該第二n-型半導體層的表面的區域、及一閘極電極，其透過該閘極絕緣膜面向該主體層。一介於該第一n-型半導體層的表面和該主體層之間的界面包括一斜的表面。該斜的表面被傾斜致使該主體層的深度隨著從該主體層的一端算起之在水平方向上的距離的增加而增加。該斜的表面被設置在該閘極電極下方。

Description

切換元件及製造切換元件的方法
[0001] 本發明係有關於一種切換元件及製造切換元件的方法。
[0002] 日本未審查的專利公開案第2009-147381號 (JP 2009-147381 A)揭露一種切換元件，其包括一第一n-型半導體層(漂移區)、一p-型主體層、及一第二n-型半導體層(源極區)。該第二n-型半導體層與該第一n-型半導體層被該主體層分隔開。一經由一閘極絕緣膜面向該主體層的閘極電極，它是在一將該第一n-型半導體層與該第二n-型半導體層分開的區域內。在該切換元件中，一介於該第一n-型半導體層和該主體層之間的界面具有一斜的表面，該斜的表面被傾斜致使該主體層的深度隨著從該主體層的一端算起的距離的增加而增加。該斜的表面被設置在該閘極電極下方。
[0003] 研究的結果顯示，本案發明人已發現一將被施加至該閘極絕緣膜的電場可藉由將該傾斜的表面提供至位於該閘極電極下方的該主體層和該第一n-型半導體層之間的界面上來將其衰減。 　　[0004] 在JP 2009-147381 A中，該斜的表面被提供在位於該閘極電極下方的該主體層和該第一n-型半導體層之間的界面上。然而，在JP 2009-147381 A中，該主體層是由擴散層所構成。在該主體層是由擴散層所構成的情形中，雜質從該主體層側朝向該第一n-型半導體層側擴散，因此該斜的表面具有彎曲的形狀，用以朝向第一n-型半導體層側突伸。以此方式，當該斜的表面被彎曲、該斜的表面變得相當窄、且對於將被施加至該閘極絕緣膜的電場的衰減效果被相對地降低。因此，在此說明書中，一種可更有效地衰減該將被施加至該閘極絕緣膜的電場的切換元件被提供。 　　[0005] 本發明的第一態樣係關於一種切換元件，其包括一半導體基材、一閘極絕緣膜、及一閘極電極。該半導體基材包括一第一n-型半導體層，其被曝露於該半導體基材的一表面、一p-型主體層，其由晶膜層構成且被曝露於該半導體基材的該表面、及一第二n-型半導體層，其被曝露於該半導體基材的該表面且被該主體層將其與該第一n-型半導體層分隔開。該閘極絕緣膜被建構來覆蓋一橫跨該第一n-型半導體層的表面、該主體層的一介於該第一n-型半導體層和該第二n-型半導體層之間的表面、及該第二n-型半導體層的表面的區域。該閘極電極被建構成透過該閘極絕緣膜面向介於該第一n-型半導體層和該第二n-型半導體層之間的該主體層。一介於該第一n-型半導體層的表面和該主體層之間的界面包括一斜的表面，該斜的表面被傾斜致使該主體層的深度隨著從該主體層的一端算起之在水平方向上的距離的增加而增加，且該斜的表面被設置在該閘極電極下方。 　　[0006] 在依據本發明的第一態樣的該切換元件中，一介於位在該閘極電極下方的該主體層和該第一n-型半導體層之間的界面被設置有一斜的表面。此外，在該切換元件中，該主體層是由晶膜層所構成，且不會發生雜質從該主體層側朝向該第一n-型半導體層側擴散。因此，可藉由此切換元件的結構來提供一不會在該主體層和該第一n-型半導體層之間的界面上彎曲的斜的表面以及獲得一相對寬的斜的表面。因此，可藉此結構來有效地衰減一將被施加至該閘極絕緣膜的電場。 　　[0007] 在依據本發明的該第一態樣的切換元件中，該斜的表面相對於該半導體基材的該表面的角度可小於60度。 　　[0008] 在依據本發明的該第一態樣的切換元件中，該界面可包括一表面層部分界面，其由該閘極電極下方的該半導體基材的該表面向下延伸且具有一等於或大於80度且等於或小於90度之相對於該半導體基材的該表面的角度，該斜的表面可被設置在該表面層部分界面的下側，且該斜的表面相對於該半導體基材的該表面的角度可小於60度。 　　[0009] 在依據本發明的該第一態樣的切換元件中，該半導體基材可包括至少兩個主體層及兩個第二n-型半導體層，且該閘極絕緣膜可覆蓋一區域，該區域橫跨一間隔部分的表面(其為一在該第一n-型半導體層內位在該兩個主體層之間的部分)、該主體層的表面(其為一位於該間隔部分和該第二n-型半導體層之間的部分)、及該第二n-型半導體層的該表面的一部分。 　　[0010] 本發明的第二態樣係關於一種製造切換元件的方法，該切換元件包括一半導體基材，該半導體基材包括一第一n-型半導體層，其被曝露於該半導體基材的一表面、一p-型主體層、及一第二n-型半導體層，其被曝露於該半導體基材的該表面且被該主體層將其與該第一n-型半導體層分隔開、一閘極絕緣膜、及一閘極電極，其透過該閘極絕緣膜面向介於該第一n-型半導體層和該第二n-型半導體層之間的該主體層。該方法包括形成一其內設有一開口的遮罩於該半導體基材的一上表面內；蝕刻該開口的該半導體基材的該上表面以形成一下凹部分、及形成下凹部分致使該下凹部分的一側表面成為一被傾斜的斜的表面，使得在蝕刻時該下凹部分的一相對於該半導體基材的該上表面的深度隨著一從該下凹部分的一端算起的一沿著水平方向的距離的增加而增加；移除該遮罩；藉由晶膜生長(epitaxial growth)來將該主體層晶膜地生長於該半導體基材的該上表面上及該下凹部分內；研磨該半導體基材的該上表面；選擇性地將n-型雜質離子注入該主體層的一部分以形成該第二n-型半導體層；形成該閘極絕緣膜以覆蓋一區域，該區域橫跨該第一n-型半導體層內的一表面、該主體層的一介於該第一n-型半導體層和該第二n-型半導體層之間的表面、及該第二n-型半導體層的一表面；形成該閘極電極以覆蓋該閘極絕緣膜的整個上表面；形成一層間絕緣膜，用以覆蓋該半導體基材的該上表面以及該閘極電極的一表面；形成接觸塞(contact plug)於一設置在該層間絕緣膜內的接觸孔中；將一上電極設置在該層間絕緣膜的一上表面上；及將一下電極設置在該半導體基材內的一表面上，該表面和一其上形成有該層間絕緣膜的表面相反。
[0012] 例示於圖1中的MOSFET 10包括一GaN半導體基材12。該GaN半導體基材12是一包含氮化鎵(GaN)作為主要成分的半導體基材。 　　[0013] 該GaN半導體基材12包括多個源極層40、多個主體層42、及一漂移層44。 　　[0014] 該等源極層40的每一者都是一n-型區域，且被曝露於該GaN半導體基材12的一上表面12a。 　　[0015] 該等主體層42的每一者都是一p-型區域且被設置在相應的源極層40的附近。該等主體層42的每一者覆蓋相應的源極層40的該側表面和下表面。該等主體層42的每一者被曝露於該GaN半導體基材12的該上表面12a的一和該源極層40相鄰的區域內。 　　[0016] 該漂移層44是一n-型區域，且被設置在該等主體層42底下。此外，該漂移層44亦被設置在一對主體層42之間。在下文中，該漂移層44的一位在該等主體層42之間的部分被稱為間隔部分44a。該間隔部分44a可被稱為JFET區域。該間隔部分44a被曝露於該GaN半導體基材12的該上表面12a。此外，該漂移層44被曝露該GaN半導體基材12的下表面12b的實質整個區域。該漂移層44被每一主體層42將它和每一源極層40分隔開。 　　[0017] 一介於該主體層42和該漂移層44之間的界面50是一pn接面表面。該斜的表面52被設置在該界面50內，它是一介於該主體層42和該間隔部分44a之間的部分。該斜的表面52從該GaN半導體基材12的該上表面12a斜斜地向下延伸。該斜的表面52延伸至主體層42的下表面。該斜的表面52被相對於該上表面12a傾斜，致使該主體層42的深度(亦即，一介於該上表面12a和該主體層42的下端之間的距離)隨著一從該主體層42的一端42a算起之沿著水平方向(平行於該上表面12a的方向)的距離的增加而增加。一介於該斜的表面52和該上表面12a之間的角度θ(在該主體層42內被測量的角度)小於60度。在該主體層42的底部內，該界面50實質平行於該上表面12a延伸。 　　[0018] 一閘極絕緣膜28、一閘極電極26、一層間絕緣膜24、一接觸塞22、和一上電極20被設置在該GaN半導體基材12的該上表面12a上。 　　[0019] 該閘極絕緣膜28覆蓋該GaN半導體基材12的該上表面12a的一部分。該閘極絕緣膜28覆蓋一區域，該區域橫跨該源極層40在該主體層42附近的表面、該主體層42介於該源極層40和該間隔部分44a之間的表面、和該間隔部分44a的表面。一和每一主體層42內的該閘極絕緣膜28接觸的部分(即，該主體層42介於該源極層40和該間隔部分44a之間的表面層部分)是一通道區域42b，一通道被形成在該區域內。該閘極絕緣膜28是由絕緣體(譬如，氧化物矽)組成。 　　[0020] 該閘極電極26被設置在該閘極絕緣膜28上。該閘極電極26透過該閘極絕緣膜28面向該源極層40、該主體層42(即，該通道區域42b)及該漂移層44(即，該間隔部分44a)。該閘極電極26被該閘極絕緣膜28將它和該GaN半導體基材12絕緣。 　　[0021] 該層間絕緣膜24在一沒有被該閘極絕緣膜28覆蓋的區域內覆蓋該上表面12a。此外，該層間絕緣膜24覆蓋該閘極電極26的該表面。該層間絕緣膜24是由絕緣體(譬如，氧化物矽)組成。 　　[0022] 該層間絕緣膜24被設置有多個接觸孔，且該接觸塞22被設置在每一接觸孔內。該等接觸塞22的一些接觸塞在其下端被連接至該源極層40，且其它接觸塞22則在其下端被連接至該主體層42。 　　[0023] 該上電極20被設置在該層間絕緣膜24上。該上電極20和每一接觸塞22的上表面接觸。該上電極20經由該接觸塞22被連接至該源極層40和該主體層42。 　　[0024] 一下電極30被設置在該GaN半導體基材12的該下表面12b上。該下電極30被連接至該漂移層44。 　　[0025] 當該閘極電極26的電位提高至等於或大於一閘極門檻值(將該MOSFET 10啟動所需之最小閘極電位)時，電子即被吸引至該主體層42的該通道區域42b，一通道因而被形成在該通道區域42b內。該源極層40和該漂移層44經由該通道而彼此連接，電子因而從該源極層40流至該漂移層44。在該MOSFET 10中，該通道區域42b(亦即，該主體層42)是一晶膜層，因此在該通道區域42b內的結晶缺陷很少。因此，該MOSFET 10具有相對低的on-電阻。 　　[0026] 此外，在該MOSFET 10中，位在該通道區域42b底下的部分內的該界面50係作為該斜的表面52。因此之故，在電子被散布的同時，已經通過該通道區域42b的電子向下流，如圖1中的箭頭100所標示。因此，該MOSFET 10的on-電阻被進一步降低。 　　[0027] 當該閘極電極26的電位被降低至小於該閘極門檻值時，該通道即消失，且電子的流動即被停止。亦即，該MOSFET 10被關閉。當該MOSFET 10被關閉時，一反向電壓(亦即，一讓該漂移層44具有的電位高於該主體層42的電位的電壓)被施加至該界面50的pn接面。因此之故，一耗乏層(depletion layer)從該主體層42擴張至該漂移層44，因此該漂移層44被耗盡。當該漂移層44被耗盡時，一電位分布被產生在該漂移層44內。該電位分布被產生橫跨該漂移層44和該閘極絕緣膜28。因此之故，一電場被施加橫跨該漂移層44和該閘極絕緣膜28。 　　[0028] 圖2至4例示透過模擬來計算一MOSFET在off狀態的電位分布的結果。在圖2至4中，虛線表示等電位線。同時，圖2例示在具有相對寬的斜的表面52的MOSFET中藉由模仿實例1所獲得之電位分布，及圖3和圖4分別例示在依據對照例1和2的MOSFET中的電位分布。在依據圖3中所示的對照例1的MOSFET中，界面50並沒有該斜的表面52，且介於該主體層42和該間隔部分44a之間的該界面50延伸成實質垂直於該上表面12a。在依據圖4中所示的對照例2的MOSFET中，雖然界面50具有該斜的表面52，但該斜的表面52被彎曲而朝向該漂移層44側突出，且該斜的表面52相對窄。在該主體層42是由一擴散層構成的實例中，即使是該相對寬的斜的表面52在注入雜質的階段即被提供，p-型雜質仍在活化雜質的時間點即被從該主體層42朝向該漂移層44散布，該斜的表面52因而被朝向該漂移層44彎曲。因此，如圖4所示，該斜的表面52變得相對窄。在圖3及4中，一介於該間隔部分44a上的該閘極絕緣膜28內的等電位線之間的間距變得比圖2的間距小。從圖2至圖4可瞭解到的是，當該斜的表面52是如圖2所示地相對寬時，該被施加至該閘極絕緣膜28的電場會被衰減。 　　[0029] 此外，圖5及6例示圖2的MOSFET和依據對照例1及2(圖3及4)的MOSFET之間特性的比較。圖5例示源極電壓BV和on-電阻之間的關係。圖6例示例示源極電壓BV和將被施加至氧化物膜的電場之間的關係。從圖5可瞭解到的是，圖2中的MOSFET可獲得和依據對照例1及2的MOSFET的on-電阻相等的on-電阻。此外，從圖6可瞭解到的是，在汲極和源極電壓彼此相等的情形下，一將被施加至圖2中的MOSFET內的該閘極絕緣膜28的電場低於依據對照例1及2的MOSFET中的電場。從上述的結果可知，在獲得和依據對照例1及2的MOSFET的on-電阻相等的on-電阻的同時，依據實例1中具有相對寬的斜的表面52的MOSFET 10可以比依據對照例1及2的MOSFET更有效地抑制將被施加至該閘極絕緣膜28的電場。 　　[0030] 接下來，一種製造實例1的MOSFET 10的方法將被描述。首先，如圖7所示，一其內設有一開口60的遮罩58被形成在該GaN半導體基材12的該上表面12a內。接下來，在該開口60內的該GaN半導體基材12的該上表面被蝕刻以形成一下凹部分62。在此時，該下凹部分62被形成，使得該下凹部分62的側表面作為一斜的表面63，其藉由調整蝕刻條件而相對於該GaN半導體基材12的該上表面傾斜(更詳細地，它被傾斜使得該下凹部分62的深度隨著一從該下凹部分62的一端62a算起的距離的增加而增加)。例如，可藉由隨著一離該開口60的距離的減小而減小該遮罩58的厚度以及藉由調整諸如氣體種類、壓力及RF功率等條件以進一步縮小該遮罩58和該GaN半導體基材12之間的蝕刻率的差異來形成該斜的表面63。在此處，該下凹部分62被形成，使得一介於該斜的表面63和該GaN半導體基材12的該上表面之間的角度θ被設定為小於60度。 　　[0031] 接下來，該遮罩58被移除，且該主體層42(它是一p-型GaN半導體層)藉由晶膜生長而被晶膜地生長在該GaN半導體基材12的該上表面上及該下凹部分62內，如圖8所示。在下文中，包括該漂移層44和該主體層42在內的整個GaN半導體層被稱為該GaN半導體基材12。 　　[0032] 接下來，該GaN半導體基材12的該上表面(亦即，該主體層42的該表面)以化學機械研磨(CMP)加以研磨。在此處，如圖9所示，該漂移層44的該間隔部分44a被曝露至該GaN半導體基材12的該上表面。此外，該主體層42被留在該下凹部分62內。 　　[0033] 接下來，如圖10所示，n-型雜質離子被選擇性地注入該主體層42的一部分內以形成該源極層40。 　　[0034] 接下來，如圖11所示，該閘極絕緣膜28被形成。該閘極絕緣膜28被形成，用以覆蓋一區域，該區域橫跨該源極層40在該主體層42附近的表面、該主體層42介於該源極層40和該間隔部分44a之間的表面、及該間隔部分44a的表面。接下來，如圖11所示，該閘極電極26被形成，用以覆蓋該閘極絕緣膜28的整個上表面。之後，該層間絕緣膜24、該接觸塞22、該上電極20、及該下電極30被形成，藉以完成圖1中所示的MOSFET 10。 　　[0035] 如上文所述，在依據實例1的MOSFET 10中，該主體層42是一晶膜層。因此之故，當該主體層42被形成時，p-型雜質很難從該主體層42被散布至該漂移層44。因此，可讓該界面50具有和該下凹部分62實質相同的形狀。因此之故，該主體層42被建構成晶膜層，且因而可讓該斜的表面52具有一所想要的形狀。亦即，該主體層42被建構成一晶膜層，因此可藉由抑制該斜的表面52的曲率來讓該斜的表面52變得相對寬。因此，依據實例1的該MOSFET 10可有效地衰減一將被施加至該閘極絕緣膜28的電場。 　　[0036] 依據圖12所示的實例2的MOSFET不同於依據實例1的MOSFET 10的地方在於一介於該主體層42和該間隔部分44a(即，該漂移層44)之間的界面50具有一表面層部分界面53和一斜的表面52。依據實例2的該MOSFET的其它構造和依據實例1的MOSFET 10的構造相同。該表面層部分界面53是該界面50的一被設置在該上表面12a的附近的部分。一介於該表面層部分界面53和該上表面12a之間的角度θ1等於或大於80度且等於或小於90度。亦即，該表面層部分界面53係實質垂直地從該上表面12a向下延伸。該斜的表面52被設置在該表面層部分界面53下方。該斜的表面52的上端被連接至該表面層部分界面53的下端。該斜的表面52被傾斜至該上表面12a，使得該主體層42的深度隨著一從該主體層42的一端42a算起之沿著該水平方向的距離的增加而增加。一介於該斜的表面52和該上面12a之間的角度θ2係小於60度。 　　[0037] 在依據實例2的該MOSFET中，該主體層42是一晶膜層，因此該斜的表面52相對寬。因此，在依據實例2的該MOSFET中，一將被施加至該閘極絕緣膜28的電場被衰減。 　　[0038] 此外，在依據實例2的該MOSFET中，該表面層部分界面53被設置在該斜的表面52的上部內。因此之故，在依據實例1和實例2的該間隔部分44a的寬度被設定為彼此相同的情形下，該實例2中的一介於該斜的表面52和該源極層40之間的距離變成大於實例1中的該距離。在該MOSFET被啟動的狀態中，一耗乏層被局部地產生在包含該斜的表面52的該界面50的附近。在依據實例2的MOSFET中，一介於在on-狀態時被產生在該斜的表面52的附近的該耗乏層和該源極層40之間的距離大於依據實例1的MOSFET 10中的該距離。因此之故，在依據實例2的該MOSFET中，一短通道效應不會被獲得。因此，一據實例2的結構可更加抑制起因於短通道效應的閘極門檻值變動。 　　[0039] 此外，當實質垂直於該上表面12a延伸的該表面層部分界面53如實例2般地被提供時，在大量製造期間不容易造成MOSFET間之該間隔部分44a的上表面12a內的寬度(亦即，一介於位在實例2中的該間隔部分44a的兩側上的該表面層部分界面53之間的寬度)的變化。當該間隔部分44a的寬度相對寬時，一高的電場被輕易地施加至該間隔部分44a上的該閘極絕緣膜28。根據實例2的MOSFET的結構，該間隔部分44a的寬度的變化被抑制，因此可文定地抑制將被施加至該閘極絕緣膜28的電場。 　　[0040] 依據實例2的該MOSFET可藉由形成具有圖13所示的形狀的下凹部分62然後實施和實例1相同的處理來製造。具有圖13所示的形狀的該下凹部分62可藉由首先和實例1類似地形成圖7中所示的該下凹部分62，然後在蝕刻沿著該GaN半導體基材12的厚度方向均勻地進行的條件下進一步蝕刻該下凹部分62來獲得。 　　[0041] 雖然該MOSFET已在上文的實例1及實例2中被描述，但揭露於此說明書中的技術可被應用至IGBT。該IGBT的結構可藉由添加p-型層於該下電極30和該漂移層44之間來獲得。 　　[0042] 此外，在上文描述的實例1和實例2中，該GaN半導體基材被用作為半導體基材。然而，揭露於此說明書中的技術可被應用至一切換元件，其包括以SiC或Si作為主要成分的半導體基材。在此處，揭露於此說明書中的技術在一使用幾乎不控制雜質擴散的半導體基材(譬如，GaN或SiC)的實例中是特別有效的。 　　[0043] 該等實例的組成元件和請求項的組成元件間的關係將被描述。該漂移層44在該實例中是第一n-型半導體層的一個例子。該源極層40在該實例中是第二n-型半導體層的一個例子。 　　[0044] 本發明的技術元件將於下文中描述。 　　[0045] 在該切換元件(其為本發明的一個例子)中，介於該第一n-型半導體層和該主體層之間的界面從該半導體基材的表面向下延伸於該閘極電極下方，且該表面層部分界面具有一相對於該半導體基材的表面的角度，其等於或大於80度且等於或小於90度。一斜的表面被設置在該表面層部分界面的下側上。該斜的表面相對於該半導體基材的表面的角度小於60度。 　　[0046] 同時，在此說明書中，一界面(亦即，該表面層部分界面或該斜的表面)相對於該半導體基材的表面的角度係指一在該主體層內被測量的角度。 　　[0047] 如上文所述，雖然實施例已被詳細地描述，但這些實施例只是實例且並不侷限請求項的區域。描述於請求項中的技術包括描述於上文中的該等特定的實例的修改及變化。描述於此說明書或圖式中的技術元件顯示獨立的技術實用性或其各種組合，且並限於在此申請案申請時描述於請求項中的組合。此外，描述於此說明書或圖式中的技術同時達成多個目的，且即使在它達成該等目的中的一個目的時仍具有技術實用性。
[0048]
12‧‧‧GaN半導體基材
12a‧‧‧上表面
40‧‧‧源極層
42‧‧‧主體層
44‧‧‧漂移層
44a‧‧‧間隔部分
12b‧‧‧下表面
50‧‧‧界面
52‧‧‧斜的表面
20‧‧‧上電極
22‧‧‧接觸塞
24‧‧‧層間絕緣膜
26‧‧‧閘極電極
28‧‧‧閘極絕緣膜
42b‧‧‧通道區域
30‧‧‧下電極
10‧‧‧MOSFET
100‧‧‧箭頭
58‧‧‧遮罩
60‧‧‧開口
62‧‧‧下凹部分
63‧‧‧斜的表面
62a‧‧‧一端
53‧‧‧表面層部分界面
42a‧‧‧一端
[0011] 本發明的示性實施例的特徵、好處、及技術和產業重要性將參考附圖在下文中描述，其中相同的標號標示相同的元件，及其中： 　　圖1是依據實例1的MOSFET的剖面圖； 　　圖2是例示一具有相對寬的斜的表面的MOSFET的電場分布的圖式； 　　圖3是一例示依據對照例1的MOSFET的電場分布的圖式； 　　圖4是一例示依據對照例2的MOSFET的電場分布的圖式； 　　圖5是一例示有關on-電阻的比較的圖表； 　　圖6是一例示一將被施加至閘極絕緣膜的電場的比較的圖表； 　　圖7是一例示依據實例1的MOSFET製程的圖式； 　　圖8是一例示依據實例1的MOSFET製程的圖式； 　　圖9是一例示依據實例1的MOSFET製程的圖式； 　　圖10是一例示依據實例1的MOSFET製程的圖式； 　　圖11是一例示依據實例1的MOSFET製程的圖式； 　　圖12是依據實例2的MOSFET的剖面圖；及 　　圖13是一例示依據實例2的MOSFET製程的圖式。

Claims (3)

  1. 一種切換元件，包含：一半導體基材，其包括一第一n-型半導體層，其被曝露於該半導體基材的一表面，一p-型主體層，其由晶膜層構成且被曝露於該半導體基材的該表面，及一第二n-型半導體層，其被曝露於該半導體基材的該表面且被該主體層將其與該第一n-型半導體層分隔開；一閘極絕緣膜，其被建構來覆蓋一橫跨該第一n-型半導體層的表面、該主體層的一介於該第一n-型半導體層和該第二n-型半導體層之間的表面、及該第二n-型半導體層的表面的區域；一閘極電極，其被建構成透過該閘極絕緣膜面向介於該第一n-型半導體層和該第二n-型半導體層之間的該主體層，其中一介於該第一n-型半導體層和該主體層之間的界面包括一非彎曲的斜的表面，該斜的表面被傾斜致使該主體層的深度隨著一從該主體層的一端算起之在水平方向上的距離的增加而增加，且該斜的表面被設置在該閘極電極下方；其中該界面包括一表面層部分界面，其由在該閘極電極下方的該半導體基材的該表面向下延伸；該斜的表面被設置在該表面層部分界面的下側；且該斜的表面相對於該半導體基材的該表面的角度小於60度。
  2. 如申請專利範圍第1項之切換元件，其中：該半導體基材包括至少兩個主體層及兩個第二n-型半導體層；且該閘極絕緣膜覆蓋一區域，該區域橫跨一間隔部分的表面(其為一在該第一n-型半導體層內位在該兩個主體層之間的部分)、該主體層的表面(其為一位於該間隔部分和該第二n-型半導體層之間的部分)、及該第二n-型半導體層的該表面的一部分。
  3. 一種製造切換元件的方法，該切換元件包括一半導體基材，其包括一被曝露於該半導體基材的一表面的第一n-型半導體層，一p-型主體層，及一第二n-型半導體層，其被曝露於該半導體基材的該表面且被該主體層將其與該第一n-型半導體層分隔開、一閘極絕緣膜、及一閘極電極，其透過該閘極絕緣膜面向介於該第一n-型半導體層和該第二n-型半導體層之間的該主體層，該方法包含：形成一其內設有一開口的遮罩於該半導體基材的一上表面內；蝕刻該開口的該半導體基材的該上表面以形成一下凹部分、並形成下凹部分致使該下凹部分的一側表面成為一被傾斜的斜的表面，使得在蝕刻時該下凹部分的一相對於該半導體基材的該上表面的深度隨著一從該下凹部分的一端算起的一沿著水平方向的距離的增加而增加；移除該遮罩；藉由晶膜生長來將該主體層晶膜地生長於該半導體基材的該上表面上及該下凹部分內；研磨該半導體基材的該上表面；選擇性地將n-型雜質離子注入該主體層的一部分以形成該第二n-型半導體層；形成該閘極絕緣膜以覆蓋一區域，該區域橫跨該第一n-型半導體層內的一表面、該主體層的一介於該第一n-型半導體層和該第二n-型半導體層之間的表面、及該第二n-型半導體層的一表面；形成該閘極電極，用以覆蓋整個該閘極絕緣膜的上表面；形成一層間絕緣膜，用以覆蓋該半導體基材的該表面以及該閘極電極的一表面；形成接觸塞(contact plug)於一設置在該層間絕緣膜內的接觸孔中；將一上電極設置在該層間絕緣膜的一上表面上；及將一下電極設置在該半導體基材內的一表面上，該表面和一其上形成有該層間絕緣膜的表面相反。
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