CN106158781A - 微凸块接合装置 - Google Patents

微凸块接合装置 Download PDF

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Publication number
CN106158781A
CN106158781A CN201610769934.0A CN201610769934A CN106158781A CN 106158781 A CN106158781 A CN 106158781A CN 201610769934 A CN201610769934 A CN 201610769934A CN 106158781 A CN106158781 A CN 106158781A
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Prior art keywords
metal
dielectric layer
treatment
micro
workpiece
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CN201610769934.0A
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CN106158781B (zh
Inventor
沈文维
陈承先
郭正铮
陈明发
王荣德
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种微凸块接合装置，包括一工件，其包括一金属凸块；以及一介电层，其具有位于上述金属凸块正上方的一部分。上述金属凸块和上述介电层的上述部分的一表面形成一介面。一金属表面处理物形成于上述金属凸块的上方且接触上述金属凸块。上述金属表面处理物从上述介电层的上方延伸上述介面的下方。通过本发明实施例的接合结构，可强化现有技术的弱点，且可改善接合结构的可靠度。

Description

微凸块接合装置
本申请是申请号为201010546155.7、申请日为2010年11月10日、发明名称为“微凸块接合装置”的发明专利申请的分案申请。
技术领域
本发明涉及一种集成电路，特别是涉及一种强度提升的微凸块接合结构及其形成方法。
背景技术
在芯片制造工艺中，首先在半导体基板的表面上形成例如晶体管的集成电路元件。然后，在上述集成电路元件的上方形成内连线结构。在半导体晶片的表面上形成金属凸块，且电性耦接至上述集成电路元件。切割上述半导体晶片成为半导体芯片，上述半导体芯片也可视为常见的裸片。
在封装半导体芯片工艺中，通常利用倒装芯片接合工艺(flip-chip bonding)将上述半导体芯片与其他芯片接合。使用焊锡以接合上述半导体芯片中的金属凸块(bump)，或将上述半导体芯片中的金属凸块接合至封装基板中的接合焊盘。当接合两个半导体芯片(或一个半导体芯片和一个封装基板)时，可在一个导电凸块或接合焊盘上预先形成一焊锡凸块(solder bump)。然后进行一回焊工艺(re-flow)，以使上述焊锡凸块与半导体芯片接合。现有技术的导电凸块通常具有大尺寸，且因而发展出微凸块(micro-bump)。微凸块倒装芯片内连线结构(Micro-bump flip-chip interconnections)允许高接合密度。
图1显示现有技术范例中位于芯片200上的微凸块(micro-bump)，其中微凸块210形成于芯片200的一表面。上述微凸块210包括镍层212，以及镍层212上的铜焊盘214。氮化硅层216覆盖微凸块210的边缘部分，且并未覆盖铜焊盘214顶面的中间部分。无电镀镍/无电镀钯/浸金表面处理物(ENEPIG finish)220形成覆盖从氮化硅层216中的开口暴露出来的铜焊盘214。利用回焊焊锡覆盖物234，将如图1所示的微凸块210与芯片232上的金属凸块230接合，以使芯片200和232接合在一起。
因此，在此技术领域中，有需要一种微凸块接合结构及其形成方法，以提升接合强度。
发明内容
有鉴于此，本发明一实施例提供一种微凸块接合装置，包括第一工件，包括：基板；金属凸块，位于该基板上方，其中该金属凸块包括上表面及侧壁；介电层，位于该基板上方，其中该介电层包括第一部分及侧壁部分，该第一部分局部覆盖该金属凸块的该上表面，该侧壁部分顺应地覆盖该金属凸块的该侧壁；以及金属表面处理物，从该介电层的该第一部分的上表面连续地延伸至该金属凸块内，且更连续地延伸至该介电层的该第一部分的下表面下方。
本发明一实施例提供一种微凸块接合装置的形成方法，包括：提供第一工件，其中该第一工件包括基板和位于该基板上方的金属凸块，且该金属凸块包括上表面及侧壁；在该基板上方毯覆形成介电层，其中该介电层包括第一部分及侧壁部分，该第一部分局部覆盖该金属凸块的该上表面，且该侧壁部分顺应地覆盖该金属凸块的该侧壁；在形成该介电层之后，在该金属凸块内形成凹陷，其中该凹陷延伸至该介电层的该第一部分下方且露出该第一部分的下表面；以及在露出该第一部分的该下表面之后形成金属表面处理物，其中该金属表面处理物从该介电层的该第一部分的上表面连续地延伸至该凹陷内，且更连续地延伸至该介电层的该第一部分露出的该下表面下方。
本发明其他实施例公开如下。
通过本发明实施例的接合结构，可强化现有技术的弱点，且可改善接合结构的可靠度。
附图说明
图1为现有微凸块结构的剖面示意图。
图2至图6为依据本发明不同实施例的接合结构的形成方法的工艺剖面图。
图7至图9为依据本发明其他不同实施例的接合结构的形成方法的工艺剖面图。
【主要附图标记说明】
2～工件；
10～基板；
12～内连线结构；
14～半导体元件；
28～金属焊盘；
30～保护层；
32～焊球下金属层；
34～铜凸块；
36～金属表面处理物；
38～金属凸块；
40～焊锡覆盖物；
100～工件；
108～集成电路元件；
110～金属凸块；
110A～中间部分；
110B～边缘部分；
112～金属层；
112A～镍层；
112B～铜种晶层；
114～金属层；
118～介电层；
118A～第一部分；
118B～侧壁部分；
118C～第三部分；
120～开口；
124～凹陷；
126～底部；
128～角落；
124’～底切；
132～金属表面处理物；
132A、132B、132C、132D～部分；
140～掩模；
200、232～芯片；
210～微凸块；
212～镍层；
214～铜焊盘；
216～氮化硅层；
220～无电镀镍/无电镀钯/浸金表面处理物；
230～金属凸块；
234～焊锡覆盖物；
T～厚度；
W1～水平尺寸；
W2～宽度；
D1、D2～深度。
具体实施方式
以下以各实施例详细说明并伴随着附图说明的范例，做为本发明的参考依据。在附图或说明书描述中，相似或相同的部分皆使用相同的图号。且在附图中，实施例的形状或是厚度可扩大，并以简化或是方便标示。再者，附图中各元件的部分将以分别描述说明之，值得注意的是，图中未示出或描述的元件，为本领域普通技术人员所知的形式，另外，特定的实施例仅为公开本发明使用的特定方式，其并非用以限定本发明。
本发明实施例是提供一种新颖的接合结构。以下以各实施例详细说明并伴随着附图说明的范例，做为本发明的参考依据。在附图或说明书描述中，相似或相同的部分皆使用相同的图号。
请参考图2，提供一工件2，其包括一基板10。工件2可为一元件裸片(device die)，其内部包括例如晶体管的有源元件(active device)，然而，工件2也可为其内部没有有源元件的一封装基板或一中介物(interposer)。在本发明一实施例中，工件2可为一元件裸片(device die)，而基板10可为例如硅基板的一半导体基板，然而基板10也可包括其他半导体材料。例如晶体管的半导体元件14可形成于基板10的一表面。内连线结构12，其包括形成于其中且连接至半导体元件14的金属线和介层孔插塞(图未显示)，形成于基板10的上方。上述金属线和介层孔插塞可由铜或铜合金形成，且可利用常用的镶嵌工艺形成上述金属线和介层孔插塞。内连线结构12可包括常用的层间介电质(ILD)和金属层间介电质(IMD)。
金属焊盘28形成于内连线结构12的上方。金属焊盘28可包括铝(Al)、铜(Cu)、银(Ag)、金(Au)、镍(Ni)、钨(W)、上述合金及/或上述多层结构。金属焊盘28可电性耦接至半导体元件14，举例来说，保护层30可通过其下的内连线结构12电性耦接至半导体元件14。可形成保护层30以覆盖金属焊盘28的边缘部分。在本发明一实施例中，可由聚酰亚胺(polyimide)或其他常用的介电材料形成保护层30。
焊球下金属层(Under Bump Metallurgy,UBM)32形成于金属焊盘28上且电性连接至金属焊盘28。焊球下金属层32可包括一铜层和一钛层(图未显示)。铜凸块34形成于焊球下金属层32上。在本发明一实施例中，可利用电镀工艺形成铜凸块34。本发明一实施例的电镀工艺可包括形成一毯覆焊球下金属层(图未显示，其中焊球下金属层32为上述毯覆焊球下金属层的一部分)，在上述毯覆焊球下金属层上形成一掩模(图未显示)，图案化上述掩模以形成一开口，在上述开口中电镀铜凸块34，以及移除上述掩模和先前被上述掩模覆盖的部分上述毯覆焊球下金属层。铜凸块34可大体上由纯铜或纯铜合金形成。
可利用电镀工艺在铜凸块34上形成金属表面处理物36。金属表面处理物36可包括不同的材料和层且可用以防止铜凸块34的氧化和铜凸块34扩散至焊锡覆盖物40/焊锡覆盖物40扩散至铜凸块34。在本发明一实施例中，可由镍(Ni)形成金属表面处理物36，然而也可添加其他的金属。在本发明其他实施例中，金属表面处理物36可由无电镀镍/无电镀钯/浸金(ENEPIG)形成，上述无电镀镍/无电镀钯/浸金(ENEPIG)包括一镍层、位于镍层上的一钯层和位于钯层上的一金层。金属表面处理物36可被限制于铜凸块34正上方的区域。在本发明其他实施例中，金属表面处理物36也可形成于铜凸块34的侧壁上。在后续的讨论中，焊球下金属层32、铜凸块34和金属表面处理物36的组合可视为金属凸块38。焊锡覆盖物40可形成于金属凸块38上且可包括包含例如SnAg、SnAgCu或类似材料的一无铅焊锡材料(lead-free solder material)，然而焊锡覆盖物40也可由包含例如铅(Pb)和锡(Sn)的一共镕焊锡材料(eutectic solder material)形成。
图3显示工件100，其可为一半导体芯片，然而工件100也可为一封装基板。另外，如图3所示的结构可为一硅芯片/裸片/晶片的一背侧或一前侧。工件100可包括金属凸块110。可在工件100中形成导通孔(TSV)以形成立体集成电路(3DICs)。可在工件100中形成例如重布线路(图未显示)的电性连接物。通过上述电性连接物，金属凸块110可电性耦接至工件100中的集成电路元件108及/或其中的导通孔(TSV)。
金属凸块110可包括金属层112，金属层112可包括镍层112A和铜种晶层112B，举例来说，金属层112可做为用以形成金属层114的一焊球下金属层(UBM)和一阻挡层。在本发明一实施例中，上述镍层112A的厚度可约介于至之间，且上述铜种晶层112B的厚度可约介于至之间。然而，本领域普通技术人员可知实施例所提及的尺寸仅做为例子，且如果使用不同的工艺可改变上述尺寸。可利用例如电镀或无电镀工艺，在金属层112的上方形成金属层114。上述金属层112可由铜(Cu)(举例来说，纯铜或大体上为纯铜)、铝(Al)、银(Ag)或上述合金形成。上述金属层114的厚度T可约介于1μm至10μm之间。在说明书描述中，上述金属层112和金属层114的组合可视为一微凸块(金属凸块)110。在俯视图中，微凸块(金属凸块)110似乎可为一长方形、一正方形或一圆形。水平尺寸W1(其可为一长度、一宽度或一尺寸，依据微凸块(金属凸块)110的形状而定)的厚度可约介于5μm至30μm之间，然而也可使用不同的尺寸。
形成微凸块(金属凸块)110之后，可毯覆形成一介电层118以覆盖工件100的表面。上述介电层118的形成方式可包括化学气相沉积(CVD)法、等离子体增强型化学气相沉积(PECVD)法或其他适合的方式。上述介电层118的厚度可约介于0.1μm至1μm之间。上述介电层118可为一顺应层(conformal layer)，其中位于微凸块(金属凸块)110侧壁上的侧壁部分的厚度接近于水平部分的厚度。另外，上述介电层118可包括位于微凸块(金属凸块)110正上方的一第一部分118A、一侧壁部分118B和不位于微凸块(金属凸块)110正上方的一第三部分118C，其中第一部分118A和第三部分118C是连接至侧壁部分118B的相对末端。然后，进行一图案化工艺，以在上述介电层118中形成开口120，且微凸块(金属凸块)110从开口120暴露出来。上述介电层118可由氮化硅形成，然而也可使用例如氧化硅、氮氧化硅或类似的材料形成上述介电层118。形成开口120之后，微凸块(金属凸块)110的顶面包括两个部分，穿过开口120而暴露出来的中间部分110A，和被介电层118覆盖的边缘部分110B，其中中间部分110A大体上与边缘部分110B对齐。微凸块(金属凸块)110的顶面的边缘部分110B也可为介电层118的底面和微凸块(金属凸块)110的顶面之间的一介面。因此，上述介面也可标示为110B。
请参考图4，可使用攻击微凸块(金属凸块)110/金属层114的一蚀刻剂来进行一蚀刻工艺。上述蚀刻工艺可为等向性蚀刻，然而可结合非等向性蚀刻作用和等向性蚀刻作用。因此，可使用一湿蚀刻工艺，举例来说，使用H2SO4做为蚀刻剂。因此凹陷金属层114，且形成凹陷124。在本发明一实施例中，凹陷124的深度D1可约大于1μm或甚至约大于2μm。深度D1也可约介于至2μm之间。由于等向性蚀刻的性质，凹陷124可包括一大体上平坦的底部126，且底部126也为金属层114的凹陷部分的顶面。另外，凹陷124的角落128可为圆角。凹陷124可延伸至的介电层118的正下方以形成底切124’，其中底切124’的宽度W2可大于0.5μm或甚至约大于2μm。
接着，如图5所示，形成金属表面处理物(metal finish)132。在本发明一实施例中，可由镍形成金属表面处理物132，然而也可添加其他金属。在本发明其他实施例中，可由无电镀镍/无电镀钯/浸金(ENEPIG)形成金属表面处理物132，上述无电镀镍/无电镀钯/浸金(ENEPIG)包括一镍层、位于镍层上的一钯层和位于钯层上的一金层。可利用浸镀法(immersion plating)形成上述金层。在本发明其他实施例中，可利用包括但不限制于无电镀镍浸金(ENIG)、直接浸金(DIG)或类似方法的其他常用的表面处理材料和方法形成金属表面处理物132。可依据金属表面处理物132的类型，使用包括无电电镀法、浸润法或类似方法的方式，以从金属层114的暴露部分选择性形成金属表面处理物132。因此，填满包括底切124’的凹陷124。最终形成的金属表面处理物132可包括位于介电层118的第一部分118A上方的部分132A、与介电层118的第一部分118A对齐的部分132B，以及低于介电层118的第一部分118A且延伸至金属层114内部的部分132C。此外，部分132D，其为部分132C的一部分，位于底切124’中，且位于介电层118的正下方。金属表面处理物132的顶面可高于介电层118的顶面。金属表面处理物132可延伸至部分介电层118的正上方。另外，金属表面处理物132的顶面可为圆角形。
如图6所示，工件2可通过倒装芯片接合(flip-chip bonding)方式与工件100接合。进行一回焊工艺以熔化焊锡覆盖物40(图2)。因此，焊锡覆盖物40可与工件2和工件100接合。在最终结构中，金属表面处理物132和金属(铜)层114之间的介面低于介面110B，上述介面110B为现有技术的易于破裂和断裂的弱点(weak point)。反之，金属表面处理物132的内部接合部分位于与介面110B相同的高度，且上述金属表面处理物132的内部接合部分远较于金属表面处理物132和金属(铜)层114之间的介面坚固。另外，金属表面处理物132与金属层114不仅会形成一个大的介面区域，而且金属表面处理物132会延伸至介电层118的下方。因此，金属表面处理物132和金属(铜)层114之间的接合力强。可改善整体接合结构的可靠度。
如图2至图6所示的实施例中，是使用介电层118为一自对准掩模。在本发明其他实施例中，可使用一额外的掩模，在金属层114中形成凹陷。图7至图9是显示不同的实施例。除了特定元件之外，这些实施例的元件符号是显示类似于如图2至图6所示的实施例的元件符号。本实施例的起始步骤实质上与图2和图3所示相同。接着，如图7所示，在工件100的表面上形成一掩模140，其中掩模140可为一光致抗蚀剂。图案化上述掩模140，以使部分金属层114的中间部分(顶面)110A暴露出来，且其中一些部分被覆盖。然后，如图8A至图8C所示，进行一蚀刻工艺以蚀刻暴露出部分金属层114，以形成凹陷124。上述蚀刻工艺可为等向性蚀刻工艺、非等向性蚀刻或上述组合。在最终结构中，凹陷124的深度D2可约大于1μm或甚至约大于2μm。深度D2也可约介于至3μm之间。
进行上述蚀刻工艺之后，移除掩模140。图8A至图8C是显示最终结构，其中图8A为剖面图，且图8B至图8C为依据本发明不同实施例的俯视图。在俯视图中，可注意到的是，凹陷124可具有多种不同的图案。举例来说，如图8B所示，凹陷124可为排列成为例如一阵列的一周期性图案的隔绝的孔洞。在图8C中，凹陷124可为平行的沟槽，长条状的金属表面处理物132形成于其中。此外，如图8C使用的虚线所示，凹陷124可延伸至介电层118的正下方。
请参考图9，形成金属表面处理物132，然后将最终形成的工件100接合至工件2。金属表面处理物132材料和形成方法可与图5所示实施例实质上相同，且在此不做重复说明。在最终结构中，可注意到的是，金属表面处理物132可形成为延伸至金属层114内的介层孔插塞。结果，可增加金属层114和金属表面处理物132之间的介面面积，会提升最终接合结构的强度。另外，金属表面处理物132也会延伸至介电层118的正下方，以更提升最终接合结构的强度。
在本发明实施例中，通过延伸金属表面处理物132至介电层118和微凸块(金属凸块)110(金属层114)之间的介面的下方，会明显提升最终接合结构的强度。进行实验以研究现有接合结构，其金属表面处理物和微凸块之间的介面与介电层和微凸块之间的介面对齐。在实验结果中，通过现有微凸块接合的两个芯片被彼此拉开。上述实验结果显示出百分之八十的接合破裂处位于金属表面处理物和微凸块之间的介面。因此，通过本发明实施例的接合结构，可强化现有技术的弱点，且可改善接合结构的可靠度。
虽然本发明已以实施例公开如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视所附的权利要求所界的范围为准。

Claims (10)

1.一种微凸块接合装置，包括：
第一工件，包括：
基板；
金属凸块，位于该基板上方，其中该金属凸块包括上表面及侧壁；
介电层，位于该基板上方，其中该介电层包括第一部分及侧壁部分，该第一部分局部覆盖该金属凸块的该上表面，该侧壁部分顺应地覆盖该金属凸块的该侧壁；以及
金属表面处理物，从该介电层的该第一部分的上表面连续地延伸至该金属凸块内，且更连续地延伸至该介电层的该第一部分的下表面下方。
2.根据权利要求1所述的微凸块接合装置，其中该金属表面处理物接触该金属凸块和该介电层，且该介电层的该第一部分延伸至该金属表面处理物内。
3.根据权利要求1所述的微凸块接合装置，其中该金属表面处理物接触该第一部分的该上表面、该下表面、与该上表面和该下表面连接的侧表面。
4.根据权利要求1所述的微凸块接合装置，其中该金属表面处理物包括延伸至该金属凸块内的多个介层孔插塞，且该些介层孔插塞通过该金属凸块的部分水平隔开。
5.根据权利要求1所述的微凸块接合装置，还包括一焊锡凸块，该焊锡凸块位于该金属表面处理物上方，且接触该金属表面处理物和该介电层的该第一部分。
6.根据权利要求5所述的微凸块接合装置，还包括一第二工件，该第二工件包括一额外金属凸块，其中该第一工件的该金属表面处理物与该第二工件的该额外金属凸块通过该焊锡凸块接合，且其中该第一工件及/或该第二工件为包括集成电路的一组件裸片。
7.一种微凸块接合装置的形成方法，包括：
提供第一工件，其中该第一工件包括基板和位于该基板上方的金属凸块，且该金属凸块包括上表面及侧壁；
在该基板上方毯覆形成介电层，其中该介电层包括第一部分及侧壁部分，该第一部分局部覆盖该金属凸块的该上表面，且该侧壁部分顺应地覆盖该金属凸块的该侧壁；
在形成该介电层之后，在该金属凸块内形成凹陷，其中该凹陷延伸至该介电层的该第一部分下方且露出该第一部分的下表面；以及
在露出该第一部分的该下表面之后形成金属表面处理物，其中该金属表面处理物从该介电层的该第一部分的上表面连续地延伸至该凹陷内，且更连续地延伸至该介电层的该第一部分露出的该下表面下方。
8.根据权利要求7所述的微凸块接合装置的形成方法，其中该凹陷包括通过该金属凸块的部分水平隔开的多个沟槽。
9.根据权利要求7所述的微凸块接合装置的形成方法，其中通过蚀刻工艺在该金属凸块内形成该凹陷，且使用该介电层作为掩模进行该蚀刻工艺。
10.根据权利要求7所述的微凸块接合装置的形成方法，其中通过无电电镀法或浸润法在该金属凸块上形成该金属表面处理物，且填满该凹陷。
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US8901736B2 (en) 2014-12-02
US9768138B2 (en) 2017-09-19
US20110291262A1 (en) 2011-12-01
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CN102263067A (zh) 2011-11-30
TW201143003A (en) 2011-12-01

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