CN105487718A - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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Publication number
CN105487718A
CN105487718A CN201610066613.4A CN201610066613A CN105487718A CN 105487718 A CN105487718 A CN 105487718A CN 201610066613 A CN201610066613 A CN 201610066613A CN 105487718 A CN105487718 A CN 105487718A
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China
Prior art keywords
layer
metal level
touch control
control electrode
tft
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CN201610066613.4A
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CN105487718B (zh
Inventor
陈归
龚强
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to CN201610066613.4A priority Critical patent/CN105487718B/zh
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Priority to US15/201,439 priority patent/US10043912B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
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Abstract

本发明公开了一种阵列基板及其制作方法。阵列基板包括：玻璃基板，玻璃基板上依次设置遮光金属层和缓冲层；薄膜晶体管层，设置在缓冲层上，薄膜晶体管层包括栅绝缘层和薄膜晶体管，其中薄膜晶体管位于遮光金属层上方；绝缘层、有机透明层，依次设置在薄膜晶体管层上；像素电极层，像素电极层通过第一通孔与薄膜晶体管的源/漏极连接；触控电极层，触控电极层通过第二通孔与遮光金属层连接；钝化层，设置在像素电极层与触控电极层之间。通过以上方式，本发明能够简化制作，并有效降低触控电极与信号线之间的耦合电容。

Description

阵列基板及其制作方法
技术领域
本发明涉及液晶显示技术领域，特别是涉及一种阵列基板及其制作方法。
背景技术
现在开发的自容内嵌式(IncellTouch)触控技术是将有效显示(AtiveArea，AA)区的公共(Com)电极分成小区块作为触控电极。每个触控电极都有连接至触控芯片(IC)的Rx信号线以接收触控信号。目前低温多晶硅技术(LowTemperaturePoly-silicon，LTPS)常用的是顶栅的薄膜晶体管(ThinFilmTransistor，TFT)，为了防止AA区中TFT器件漏电过大，一般会在沟道下方用金属层遮光，即我们常说遮光金属(LSM)层。
在现有的自容Incell设计中，如图1所示，在玻璃基板(图未示)上依次生长遮金属层11和缓冲层12，在缓冲层12上生长多晶硅层132，在多晶硅层132的两侧进行掺杂形成掺杂区132，进一步在掺杂区132的远离多晶硅层12的一侧生成重掺杂区133。在多晶硅层132上依次生长栅绝缘层131和第一金属层134，形成栅极。在第二金属层135上生长第一绝缘层14，在重掺杂区133上生长第二金属层135，形成源/漏(S/D)极。其中第二金属层135穿过第一绝缘层14。进一步地，在第一绝缘层14上依次生长有机透明层15和第二绝缘层141。然后在第二绝缘层141上生长第三金属层19以作为Rx信号线，在第三金属层19上依次生长第三绝缘层142、触控电极16、钝化层18以及像素电极层17。其中像素电极17通过第一过孔与第二金属层135连接，触控电极16通过第二通孔与第三金属层19连接。
由此可见，为了制作Rx信号线，在制作阵列基板时，新增了一道金属制程，即第三金属层19。并且为了将Rx信号线与触控电极16导通，新增了一道过孔制程。新加的两道制程不仅使原本12道光罩的CMOSLTPS制程变为了14道光罩，同时由于不使触控电极与Rx信号线的耦合电容Cst过小，第三金属层19与触控电极16之间的绝缘层的厚度不能做的太薄，因此触控电极16与其它电极Rx信号线的耦合电容就难以做小。
发明内容
本发明实施例提供了一种阵列基板及其制作方法，能够简化制作，并有效降低触控电极与信号线之间的耦合电容。
本发明提供一种阵列基板，包括：玻璃基板，玻璃基板上依次设置遮光金属层和缓冲层；薄膜晶体管层，设置在缓冲层上，薄膜晶体管层包括栅绝缘层和薄膜晶体管，其中薄膜晶体管位于遮光金属层上方；绝缘层、有机透明层，依次设置在薄膜晶体管层上；像素电极层，像素电极层通过第一通孔与薄膜晶体管的源/漏极连接；触控电极层，触控电极层通过第二通孔与遮光金属层连接；钝化层，设置在像素电极层与触控电极层之间。
其中，薄膜晶体管包括多晶硅层、第一金属层以及第二金属层，其中多晶硅层设置在缓冲层上，多晶硅层的两侧为重掺杂区，栅绝缘层和第一金属层依次设置在多晶硅层上，且第一金属层经图案化形成栅极，第二金属层穿过绝缘层设置在重掺杂区上，形成源/漏极。
其中，第一金属层穿过栅绝缘层和缓冲层，与遮光金属层连接。
其中，第二金属层穿过栅绝缘层和缓冲层，与遮光金属层连接，触控电极层通过第二通孔与第二金属层连接。
其中，触控电极层设置在有机透明层上，并在触控电极层上依次设置钝化层和像素电极层，第一通孔依次穿过钝化层、触控电极层以及有机透明层，第二通孔依次穿过有机透明层和绝缘层。
其中，像素电极层设置在有机透明层上，并在像素电极层上依次设置钝化层和触控电极层，第一通孔穿过有机透明层，第二通孔依次穿过钝化层、有机透明层以及绝缘层。
本发明还提供一种阵列基板的制作方法，包括：在玻璃基板上依次生长遮光金属层和缓冲层；在缓冲层上生长薄膜晶体管层，薄膜晶体管层包括栅绝缘层和薄膜晶体管，其中薄膜晶体管位于遮光金属层上方；依次在薄膜晶体管层上生长绝缘层和有机透明层；通过第一通孔将像素电极层与薄膜晶体管的源/漏极连接，通过第二通孔将触控电极层与遮光金属层连接。
其中，薄膜晶体管包括多晶硅层、第一金属层以及第二金属层，在缓冲层上生长薄膜晶体管层的步骤包括：在缓冲层上生长多晶硅层；对多晶硅层两侧进行重掺杂，形成重掺杂区；在多晶硅层上依次生长栅绝缘层和第一金属层，形成栅极；在重掺杂区上生长第二金属层，形成源/漏极。
其中，在重掺杂区上生长第二金属层的步骤还包括：第二金属层穿过栅绝缘层和缓冲层，与遮光金属层连接，触控电极层通过第二通孔与第二金属层连接。
其中，在多晶硅层上依次生长栅绝缘层和第一金属层的步骤还包括：第一金属层穿过栅绝缘层和缓冲层，与遮光金属层连接。
通过上述方案，本发明的有益效果是：本发明通过在玻璃基板上依次生长遮光金属层和缓冲层，在缓冲层上生长薄膜晶体管层，薄膜晶体管位于遮光金属层上方，在薄膜晶体管层上依次生长绝缘层、有机透明层，并且像素电极层通过第一通孔与薄膜晶体管的源/漏极连接，触控电极层通过第二通孔与遮光金属层连接，钝化层设置在像素电极层与触控电极层之间，能够简化制作，并有效降低触控电极与信号线之间的耦合电容。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是现有技术的阵列基板的结构示意图；
图2是本发明实施例的自容IncellTouch的架构图；
图3是本发明第一实施例的阵列基板的结构示意图；
图4是本发明第二实施例的阵列基板的结构示意图；
图5是本发明第一实施例的阵列基板的版图布局示意图；
图6是本发明第三实施例的阵列基板的结构示意图；
图7是本发明第四实施例的阵列基板的结构示意图；
图8是本发明第二实施例的阵列基板的版图布局示意图；
图9是本发明第一实施例的阵列基板的制作方法的流程示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图2是本发明实施例的自容IncellTouch的架构图。如图2所示，将AA区中的公共导电薄膜(COMITO)区分成一个小方块作为触控电极，触控电极和触控芯片(IC)输出管脚(Pin)之间用Rx信号线连接。图2中，100表示一个触控电极，200表示Rx信号线与IC输出Pin相连的输出端(fanout)走线；300表示与触控电极相连的Rx信号线以及走线与触控电极之间的过孔；400表示与其它触控电极相连接的Rx信号线，其会与非短接的触控电极相连。
图3是本发明第一实施例的阵列基板的结构示意图。如图3所示，阵列基板20包括：玻璃基板(图未示)、遮光金属层21、缓冲层22、薄膜晶体管层23、绝缘层24、有机透明层25、像素电极层27、触控电极层26以及钝化层28。在玻璃基板上依次设置遮光金属层21和缓冲层22。薄膜晶体管层23设置在缓冲层22上，薄膜晶体管层23包括栅绝缘层230和薄膜晶体管231。其中薄膜晶体管230位于遮光金属层21上方。绝缘层24、有机透明层25依次设置在薄膜晶体管层23上。像素电极层27通过第一通孔与薄膜晶体管230的源/漏极连接。触控电极层6通过第二通孔与遮光金属层21连接。钝化层28设置在像素电极层27与触控电极层26之间。
在本发明实施例中，薄膜晶体管231包括多晶硅层232、第一金属层234以及第二金属层235。其中多晶硅层232设置在缓冲层22上，多晶硅层232的两侧为重掺杂区233。优选地，在多晶硅层两侧设置掺杂区236，进而在掺杂区236的远离多晶硅层232的一侧进行重掺杂形成重掺杂区233。栅绝缘层230和第一金属层234依次设置在多晶硅层232上，且第一金属层234经图案化形成栅极。第二金属层235设置在重掺杂区233上，形成源/漏极，具体地，第二金属层235穿过绝缘层24并与多晶硅层232两侧的重掺杂区233接触。
在本发明实施例中，参见图3，触控电极层26设置在有机透明层25上，并在触控电极层26上依次设置钝化层28和像素电极层27。第一通孔依次穿过钝化层28、触控电极层26以及有机透明层25，形成像素电极27的导电薄膜依次穿过钝化层28、触控电极层26以及有机透明层25与穿过绝缘层24的第二金属层235在绝缘层24的上方相接触。第二通孔202可以依次穿过有机透明层25、绝缘层24、栅绝缘层230以及缓冲层22。形成触控电极层26的导电薄膜依次穿过有机透明层25、绝缘层24、栅绝缘层230以及缓冲层22直接与遮光金属层21接触。第二通孔202也可以只依次穿过有机透明层25和绝缘层24，第二金属层235通过第三通孔203与遮光金属层21连接，形成触控电极层26的导电薄膜则依次穿过有机透明层25和绝缘层24在栅绝缘层230上方与第二金属层235接触进而与遮光金属层21连接。其中第三通孔203依次穿过栅绝缘层230和缓冲层22。
在本发明实施例中，与触控电极层26连接的遮光金属层21可以与薄膜晶体管231正下方的遮光金属层21连接，此时位于薄膜晶体管231正下方的遮光金属层21向外延伸一部分，以方便与触控电极层26连接。与触控电极层26连接的遮光金属层21也可以是与薄膜晶体管231正下方的遮光金属层21分离的。与触控电极层26连接的遮光金属层21作为Rx信号线使用，而位于薄膜晶体管231的正下方的遮光金属层21用于进行遮光，以防止薄膜晶体管漏电过大。其中，形成触控电极层26的导电薄膜和形成像素电极27的导电薄膜都采用氧化铟锡导电薄膜。
在本发明实施例中，第二金属层235与遮光金属层21之间的通孔可以采用绝缘层24的掩模版(Mask)，在将绝缘层24和栅绝缘层230刻蚀完成后换用氮化硅(SiNx)与P型硅(P-Si)选择比较大的气体刻蚀缓冲(Buffer)层22，以保证在将第二金属层235与遮光金属层21导通的同时不会讲其它地方的P-Si刻蚀掉。
本实施例的阵列基板20直接采用遮光金属层21作为连接触控电极和触控芯片的Rx信号线，不需要增加额外的光罩制程来制作第三金属层以用作Rx信号线，进而也就不需要增加一通孔制程以将触控电极与Rx信号连接，即节省了两道光罩制程，简化了制作。另外，直接采用遮光金属层21作为连接触控电极和触控芯片的Rx信号线后，触控电极层26与Rx信号线之间的距离比较大，如图3中的触控电极层26与Rx信号线之间包括有机透明层25、绝缘层24、栅绝缘层230以及缓冲层22。如此使得触控电极与Rx信号线的电容可以做到很小，能够有效降低触控电极与Rx信号线之间的耦合电容。
参见图4中的阵列基板30，其中薄膜晶体管331包括多晶硅层332、重掺杂区333、第一金属层334以及第二金属层335，具体结构与图3中的薄膜晶体管231的结构类似，在此不再赘述。像素电极层37设置在有机透明层35上，并在像素电极层37上依次设置钝化层38和触控电极层36。如此第一通孔301穿过有机透明层35，形成像素电极37的导电薄膜穿过有机透明层35与穿过绝缘层34的第二金属层335在绝缘层34的上方相接触。第二通孔302可以依次穿过钝化层38、有机透明层35、绝缘层34、栅绝缘层330以及缓冲层32。形成触控电极层36的导电薄膜依次穿过钝化层38、有机透明层35、绝缘层34、栅绝缘层230以及缓冲层32直接与遮光金属层31接触。第二通孔302也可以依次穿过钝化层38、有机透明层35以及绝缘层34，第二金属层335则还通过第三通孔303与遮光金属层31连接，形成触控电极层36的导电薄膜依次穿过钝化层38、有机透明层35以及绝缘层34在栅绝缘层230上方与第二金属层335接触进而与遮光金属层31连接。其中第三通孔303依次穿过栅绝缘层330和缓冲层32。
在本发明实施例中，与触控电极层36连接的遮光金属层31可以与薄膜晶体管331正下方的遮光金属层31连接，此时位于薄膜晶体管331正下方的遮光金属层31向外延伸一部分，以方便与触控电极层36连接。与触控电极层36连接的遮光金属层31也可以是与薄膜晶体管331正下方的遮光金属层31分离的。与触控电极层36连接的遮光金属层31作为Rx信号线使用，而位于薄膜晶体管331的正下方的遮光金属层31用于进行遮光，以防止薄膜晶体管漏电过大。阵列基板30的其他部分的结构与图3中的阵列基板20类似，在此不再赘述。
本实施例的触控电极层36与Rx信号线之间包括钝化层38、有机透明层35、绝缘层34、栅绝缘层330以及缓冲层32。如此进一步增加了触控电极层36与Rx信号线之间的距离，使得触控电极与Rx信号线的电容可以做到很小，能够进一步降低触控电极与Rx信号线之间的耦合电容。
图5是本发明实施例的阵列基板的版图布局示意图。如图5所示，用遮光金属层作为Rx信号线，通过绝缘层过孔将第二金属层与遮光金属层导通，通过钝化层过孔和有机透明层过孔将触控电极的导电薄膜与第二金属层导通，如此通过现在已有的制程将触控电极的导电薄膜与遮光金属层导通，这样就可以节省两道光罩，同时因为拉大了Rx信号线与触控电极的距离，有效降低触控电极与Rx信号线之间的耦合电容。具体地，在像素电极制作中应用现有工艺增加遮光金属层与触控电极的导电薄膜之间的通孔。
图6是本发明第三实施例的阵列基板的结构示意图。如图6所示，阵列基板40与图3中的阵列基板20的区别在于，在有机透明层45上依次设置绝缘层441和绝缘层442。触控电极层46设置在绝缘层442上。其中via1表示触控电极层46至遮光金属层41的通孔。通孔via1可以包括第二通孔402和第三通孔403。其中，第二通孔202依次穿过绝缘层441、绝缘层442、有机透明层25以及绝缘层24，第三通孔203依次穿过栅绝缘层230和缓冲层22。第二金属层435通过第三通孔403与遮光金属层21连接，形成触控电极层46的导电薄膜则依次穿过绝缘层441、绝缘层442、有机透明层45以及绝缘层44在栅绝缘层430上方与第二金属层435接触进而与遮光金属层41连接。通孔via1也可以只包括第二通孔，其中，第二通孔依次穿过绝缘层441、绝缘层442、有机透明层25、绝缘层24、栅绝缘层230以及缓冲层22，形成触控电极层46的导电薄膜则依次穿过绝缘层441、绝缘层442、有机透明层45、绝缘层44、栅绝缘层230以及缓冲层22直接与遮光金属层连接。
本发明实施例通过在有机透明层45和触控电极层46之间增加绝缘层441和绝缘层442，可以进一步增加触控电极层36与Rx信号线之间的距离，使得触控电极与Rx信号线的电容可以做到很小，能够进一步降低触控电极与Rx信号线之间的耦合电容。
本发明实施例的阵列基板也可以是在图4中的阵列基板30的基础上增加两个绝缘层，增加方法与图6中的阵列基板40相同，在此不再赘述。
参见图7，第一金属层434也可以穿过栅绝缘层430和缓冲层42，与遮光金属层41连接。via2即为穿过栅绝缘层430和缓冲层42的通孔。遮光金属层41作为Rx信号线，连接触控电极和触控芯片输出管脚。而与遮光金属层41连接的第一金属层434的设置能够减少Rx信号线的电阻。本发明实施例的通孔via2的制作可以通过增加一道光罩制程实现，而第一金属层434的沉积可以与栅极的制作同步进行，不需额外增加光罩。
阵列基板40的版图布局参见图8，用遮光金属层作为Rx信号线，触控电极层通过通孔via1与遮光金属层连接。第一金属层通过通孔via2与遮光金属层连接。其中，通孔via1的结构参见图6中的通孔via1，通孔via2的结构参见图7中的通孔via2。通孔via1将触控电极的导电薄膜与遮光金属层导通，而通孔via1可以通过现有的制程实现，不需额外增加光罩，这样就可以节省两道光罩，同时因为拉大了Rx信号线与触控电极的距离，有效降低触控电极与Rx信号线之间的耦合电容。具体地，在像素电极制作中应用现有工艺增加遮光金属层与触控电极的导电薄膜之间的通孔。通孔via2的制作可以通过增加一道光罩制程实现，而第一金属层的沉积可以与栅极的制作同步进行，不需额外增加光罩。在通孔via2沉积第一金属层能够减少Rx信号线的电阻。
以上各实施例可以任意组合形成阵列基板。
图9是本发明第一实施例的阵列基板的制作方法的流程示意图。如图9所示，阵列基板的制作方法包括：
步骤S10：在玻璃基板上依次生长遮光金属层和缓冲层。
步骤S11：在缓冲层上生长薄膜晶体管层，薄膜晶体管层包括栅绝缘层和薄膜晶体管，其中薄膜晶体管位于遮光金属层上方。
步骤S12：依次在薄膜晶体管层上生长绝缘层和有机透明层。
步骤S13：通过第一通孔将像素电极层与薄膜晶体管的源/漏极连接，通过第二通孔将触控电极层与遮光金属层连接。
在本发明实施例中，薄膜晶体管包括多晶硅层、第一金属层以及第二金属层。在步骤S11中，在缓冲层上生长多晶硅层；对多晶硅层两侧进行重掺杂，形成重掺杂区。优选地，在多晶硅层两侧设置掺杂区，进而在掺杂区的远离多晶硅层的一侧进行重掺杂形成重掺杂区。然后在多晶硅层上依次生长栅绝缘层和第一金属层，形成栅极；在重掺杂区上生长第二金属层，形成源/漏极。其中第二金属层还穿过绝缘层。
在本发明实施例中，在步骤S13中，可以在有机透明层上生长触控电极层，然后依次在触控电极层上生长钝化层和像素电极层。第一通孔依次穿过钝化层、触控电极层以及有机透明层，形成像素电极的导电薄膜依次穿过钝化层、触控电极层以及有机透明层与穿过绝缘层24的第二金属层在绝缘层的上方相接触。第二通孔可以依次穿过有机透明层、绝缘层、栅绝缘层以及缓冲层。形成触控电极层的导电薄膜依次穿过有机透明层、绝缘层、栅绝缘层以及缓冲层直接与遮光金属层接触。第二通孔也可以只依次穿过有机透明层和绝缘层，第二金属层通过第三通孔与遮光金属层连接，形成触控电极层的导电薄膜则依次穿过有机透明层和绝缘层在栅绝缘层上方与第二金属层接触进而与遮光金属层连接。其中第三通孔依次穿过栅绝缘层和缓冲层。
在本发明实施例中，与触控电极层连接的遮光金属层可以与薄膜晶体管正下方的遮光金属层连接，此时位于薄膜晶体管正下方的遮光金属层向外延伸一部分，以方便与触控电极层连接。与触控电极层连接的遮光金属层也可以是与薄膜晶体管正下方的遮光金属层分离的。与触控电极层连接的遮光金属层作为Rx信号线使用，而位于薄膜晶体管的正下方的遮光金属层用于进行遮光，以防止薄膜晶体管漏电过大。其中，形成触控电极层的导电薄膜和形成像素电极的导电薄膜都采用氧化铟锡导电薄膜。
在本发明实施例中，第二金属层与遮光金属层之间的通孔可以采用绝缘层的掩模版(Mask)，在将绝缘层和栅绝缘层刻蚀完成后换用氮化硅(SiNx)与P型硅(P-Si)选择比较大的气体刻蚀缓冲(Buffer)层，以保证在将第二金属层与遮光金属层导通的同时不会讲其它地方的P-Si刻蚀掉。直接采用遮光金属层作为连接触控电极和触控芯片的Rx信号线，不需要增加额外的光罩制程来制作第三金属层以用作Rx信号线，进而也就不需要增加一通孔制程以将触控电极与Rx信号连接，即节省了两道光罩制程，简化了制作。另外，直接采用遮光金属层作为连接触控电极和触控芯片的Rx信号线后，触控电极层与Rx信号线之间的距离比较大，如触控电极层与Rx信号线之间包括有机透明层、绝缘层、栅绝缘层以及缓冲层。使得触控电极与Rx信号线的电容可以做到很小，能够有效降低触控电极与Rx信号线之间的耦合电容。
在步骤S13中，也可以在有机透明层上生长像素电极层，然后在像素电极层上依次生长钝化层和触控电极层。如此第一通孔穿过有机透明层，形成像素电极的导电薄膜穿过有机透明层与穿过绝缘层的第二金属层在绝缘层的上方相接触。第二通孔可以依次穿过钝化层、有机透明层、绝缘层、栅绝缘层以及缓冲层。形成触控电极层的导电薄膜依次穿过钝化层、有机透明层、绝缘层、栅绝缘层以及缓冲层直接与遮光金属层接触。第二通孔也可以依次穿过钝化层、有机透明层以及绝缘层，第二金属层还通过第三通孔与遮光金属层连接，形成触控电极层的导电薄膜依次穿过钝化层、有机透明层以及绝缘层在栅绝缘层上方与第二金属层接触进而与遮光金属层连接。其中第三通孔依次穿过栅绝缘层和缓冲层。
本实施例的触控电极层与Rx信号线之间包括钝化层、有机透明层、绝缘层、栅绝缘层以及缓冲层。如此进一步增加了触控电极层与Rx信号线之间的距离，使得触控电极与Rx信号线的电容可以做到很小，能够进一步降低触控电极与Rx信号线之间的耦合电容。
在本发明实施例中，可以在步骤S12之后依次生长两层绝缘层，以进一步增加触控电极层与遮光金属层之间的距离，使得触控电极与Rx信号线的电容可以做到更小，能够进一步降低触控电极与Rx信号线之间的耦合电容。
另外，在步骤S11中，在多晶硅层上依次生长栅绝缘层和第一金属层时，可以将第一金属层穿过栅绝缘层和缓冲层，与遮光金属层连接。在制作过程中，可以通过增加一道光罩制作穿过栅绝缘层和缓冲层的通孔，而在该通孔中沉积第一金属层则可以与栅极的制作同步进行，不需额外增加光罩。与遮光金属层连接的第一金属层的设置能够减少Rx信号线的电阻。
综上所述，本发明通过在玻璃基板上依次生长遮光金属层和缓冲层，在缓冲层上生长薄膜晶体管层，薄膜晶体管位于遮光金属层上方，在薄膜晶体管层上依次生长绝缘层、有机透明层，并且像素电极层通过第一通孔与薄膜晶体管的源/漏极连接，触控电极层通过第二通孔与遮光金属层连接，钝化层设置在像素电极层与触控电极层之间，能够简化制作，并有效降低触控电极与信号线之间的耦合电容。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

1.一种阵列基板，其特征在于，所述阵列基板包括：
玻璃基板，所述玻璃基板上依次设置遮光金属层和缓冲层；
薄膜晶体管层，设置在所述缓冲层上，所述薄膜晶体管层包括栅绝缘层和薄膜晶体管，其中所述薄膜晶体管位于所述遮光金属层上方；
绝缘层、有机透明层，依次设置在所述薄膜晶体管层上；
像素电极层，所述像素电极层通过第一通孔与所述薄膜晶体管的源/漏极连接；
触控电极层，所述触控电极层通过第二通孔与所述遮光金属层连接；
钝化层，设置在所述像素电极层与所述触控电极层之间。
2.根据权利要求1所述的阵列基板，其特征在于，所述薄膜晶体管包括多晶硅层、第一金属层以及第二金属层，其中所述多晶硅层设置在所述缓冲层上，所述多晶硅层的两侧为重掺杂区，所述栅绝缘层和所述第一金属层依次设置在所述多晶硅层上，且第一金属层经图案化形成栅极，所述第二金属层穿过所述绝缘层沉积在所述重掺杂区上，形成源/漏极。
3.根据权利要求2所述的阵列基板，其特征在于，所述第一金属层穿过所述栅绝缘层和所述缓冲层，与所述遮光金属层连接。
4.根据权利要求2所述的阵列基板，其特征在于，所述第二金属层穿过所述栅绝缘层和所述缓冲层，与所述遮光金属层连接，所述触控电极层通过第二通孔与所述第二金属层连接。
5.根据权利要求1所述的阵列基板，其特征在于，所述触控电极层设置在所述有机透明层上，并在所述触控电极层上依次设置所述钝化层和所述像素电极层，所述第一通孔依次穿过所述钝化层、所述触控电极层以及所述有机透明层，所述第二通孔依次穿过所述有机透明层和所述绝缘层。
6.根据权利要求1所述的阵列基板，其特征在于，所述像素电极层设置在所述有机透明层上，并在所述像素电极层上依次设置所述钝化层和所述触控电极层，所述第一通孔穿过所述有机透明层，所述第二通孔依次穿过所述钝化层、所述有机透明层以及所述绝缘层。
7.一种阵列基板的制作方法，其特征在于，所述方法包括：
在玻璃基板上依次生长遮光金属层和缓冲层；
在所述缓冲层上生长薄膜晶体管层，所述薄膜晶体管层包括栅绝缘层和薄膜晶体管，其中所述薄膜晶体管位于所述遮光金属层上方；
依次在所述薄膜晶体管层上生长绝缘层和有机透明层；
通过第一通孔将像素电极层与所述薄膜晶体管的源/漏极连接，通过第二通孔将触控电极层与所述遮光金属层连接。
8.根据权利要求7所述的制作方法，其特征在于，所述薄膜晶体管包括多晶硅层、第一金属层以及第二金属层，所述在所述缓冲层上生长薄膜晶体管层的步骤包括：
在所述缓冲层上生长所述多晶硅层；
对所述多晶硅层两侧进行重掺杂，形成重掺杂区；
在所述多晶硅层上依次生长栅绝缘层和第一金属层，形成栅极；
在所述重掺杂区上生长第二金属层，形成源/漏极。
9.根据权利要求7所述的制作方法，其特征在于，所述在所述重掺杂区上生长第二金属层的步骤还包括：
所述第二金属层穿过所述栅绝缘层和所述缓冲层，与所述遮光金属层连接，所述触控电极层通过第二通孔与所述第二金属层连接。
10.根据权利要求7所述的制作方法，其特征在于，所述在所述多晶硅层上依次生长栅绝缘层和第一金属层的步骤还包括：
所述第一金属层穿过所述栅绝缘层和所述缓冲层，与所述遮光金属层连接。
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