WO2019184318A1 - 一种触摸显示面板及其制造方法 - Google Patents

一种触摸显示面板及其制造方法 Download PDF

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Publication number
WO2019184318A1
WO2019184318A1 PCT/CN2018/111409 CN2018111409W WO2019184318A1 WO 2019184318 A1 WO2019184318 A1 WO 2019184318A1 CN 2018111409 W CN2018111409 W CN 2018111409W WO 2019184318 A1 WO2019184318 A1 WO 2019184318A1
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WIPO (PCT)
Prior art keywords
layer
disposed
metal layer
touch
touch line
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PCT/CN2018/111409
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English (en)
French (fr)
Inventor
聂晓辉
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武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/192,766 priority Critical patent/US10802627B2/en
Publication of WO2019184318A1 publication Critical patent/WO2019184318A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Definitions

  • the present invention relates to the field of display panels, and in particular to a touch display panel and a method of fabricating the same.
  • the touch type of the display panel is often self-inductive, and the ITP (In Cell Touch) is realized by integrating the sensor pad on the array substrate. Panel, in-line touch screen) improves the quality and value of the product.
  • the structure of the Sensor pad generally contains Common ITO and touch line routing.
  • the production of the touch line trace can be separately designed, that is, the touch line is separately set; or the mask of the data line can be formed in the same layer or the same process as the data line, and the same metal is used for synchronous production. The way, but both options have problems with increased costs and process risks.
  • the technical problem to be solved by the present invention is to provide a touch display panel and a manufacturing method thereof, which can reduce the manufacturing cost, reduce the process risk, and improve the process reliability.
  • a technical solution adopted by the present invention is to provide a touch display panel, comprising: a substrate; a first metal layer, wherein the first metal layer includes a touch disposed on the substrate a wire and a light blocking block, the touch wire and a portion of the light shielding block are integrally formed; a TFT functional layer, the TFT functional layer is located above the first metal layer, and the TFT functional layer is provided with a first pass a hole, the first via is located in a vertical projection of the portion of the light blocking block; a common electrode layer is located on the TFT functional layer of the first metal layer, and passes the first through the touch line Hole connection.
  • a technical solution adopted by the present invention is to provide a touch display panel, including: a substrate; a first metal layer, the first metal layer includes a touch line disposed on the substrate; a light shielding block; a TFT functional layer, the TFT functional layer is located above the first metal layer, the TFT functional layer is provided with a first via hole; and a common electrode layer is located above the TFT functional layer, and The touch wires are connected by a first via.
  • another technical solution adopted by the present invention is to provide a method for manufacturing a touch display panel, comprising: providing a first metal layer on one side of a substrate, the first metal layer including a touch line and a light blocking block on the substrate; a TFT functional layer disposed on the first metal layer, a first via hole disposed on the TFT functional layer; and a common layer disposed on the TFT functional layer An electrode layer, the common electrode layer and the touch line being connected through the first via.
  • the first metal layer has the beneficial effects that the present invention is formed by the same layer or the same process as the light shielding block for shielding the illumination of the semiconductor layer by the backlight, so that the common electrode is formed by the same process.
  • the layer can be connected to the touch line through the first via hole to realize the touch function of the touch display panel, which can effectively reduce the cost when manufacturing the touch line, and the first opening is below the common electrode layer, and the process risk is small.
  • FIG. 1 is a schematic cross-sectional view showing an embodiment of a touch display panel provided by the present invention
  • FIG. 2 is a top plan view of a first metal layer of an embodiment of a touch display panel provided by the present invention
  • FIG. 3 is a top plan view of a first metal layer and a semiconductor layer according to an embodiment of the touch display panel provided by the present invention
  • FIG. 4 is a schematic flow chart of an embodiment of a method of manufacturing a touch display panel provided by the present invention.
  • FIG. 1 is a schematic cross-sectional view showing a second embodiment of a touch display panel provided by the present invention.
  • the touch display panel includes a substrate 10, a first metal layer 20, a buffer layer 30, a gate insulating layer 50, an interlayer insulating layer 60 and a planarization layer 70, a common electrode layer 80, a passivation layer 90, a pixel electrode layer 100, and a drain. Electrode 41 and source electrode 42.
  • the buffer layer 30, the gate insulating layer 50, the interlayer insulating layer 60, and the planarization layer 70 belong to a TFT functional layer.
  • the first metal layer 20 is formed on the substrate 10 by physical vapor deposition using metal molybdenum (Mo) as a material.
  • Mo metal molybdenum
  • the substrate 10 is provided with one side of the first metal layer 20, and the side of the first metal layer 20 away from the substrate 10 is covered with a buffer layer 30 having a material composition of SiNx/SiOx.
  • a semiconductor layer 40 is disposed on a side of the buffer layer 30 away from the substrate 10.
  • the semiconductor layer 40 and the first metal layer 20 at least partially overlap in a vertical projection direction, and the material of the semiconductor layer 40 is annealed by excimer laser Polycrystalline silicon transformed from amorphous silicon.
  • a gate insulating layer 50 is provided, the material composition of which is SiOx.
  • An interlayer insulating layer 60 is provided on a side of the gate insulating layer 50 away from the substrate 10.
  • a drain electrode 41 and a source electrode 42 are provided on the interlayer insulating layer 60, and the drain electrode 41 and the source electrode 42 are electrically connected to the semiconductor layer 40 through the second via 91 on the interlayer insulating layer 60.
  • a planarization layer 70 is provided on a side of the interlayer insulating layer 60 away from the substrate 10. The passivation layer 90 and the pixel electrode layer 100 are sequentially disposed on the side of the planarization layer 70 away from the substrate 10.
  • the common electrode layer 80 is disposed on a side of the planarization layer 70 away from the substrate 10 .
  • the buffer layer 30, the gate insulating layer 50, the interlayer insulating layer 60, and the planarization layer 70 are provided with the first via holes 81 at the same position, so that the common electrode layer 80 is connected to the first metal layer 20 through the first via holes 81. , realize the touch function of the touch display panel.
  • the semiconductor layer 40 and the drain electrode 41 and the source electrode 42 disposed on the semiconductor layer 40 are staggered from the position of the first opening. .
  • the second via 91 is further disposed on the interlayer insulating layer 60 for allowing the pixel electrode layer 100 to be connected to the drain electrode 41 through the second via 91 to realize the display function of the touch display panel. Since the positions of the semiconductor layer 40 and the source electrode 42 and the drain electrode 41 are all shifted from the first via 81, the second via 91 connecting the drain electrode 41 and the pixel electrode layer 100 is necessarily offset from the first via 81. position.
  • FIG. 2 is a schematic top view of the first metal layer 20 of the second embodiment of the touch display panel provided by the present invention.
  • the first metal layer 20 includes a touch line 22 for implementing a touch function of the panel in combination with the common electrode layer 80 and an illumination for shielding the semiconductor layer 40 from the backlight.
  • the touch line 22 partially overlaps the at least one light blocking block 21.
  • the main material of the first metal layer 20 is metal molybdenum (Mo).
  • the touch line 22 and the light shielding block 21 are made of the same material, and are formed in the first metal layer 20 of the layer by the same process. to make.
  • the first metal layer 20 including the touch line 22 and the light shielding block 21 as shown in FIG. 3 is formed on the surface of the substrate 10 at a time using metal molybdenum (Mo).
  • Mo metal molybdenum
  • the touch line 22 can be fabricated in the first metal layer 20 together with the light blocking block 21 using other materials and/or other processes.
  • a plurality of light-shielding blocks 21 made of metal molybdenum (Mo) may be deposited on the substrate 10 using a process (for example, physical vapor deposition), and then the material is placed on the substrate 10 using another process.
  • the material of the light shielding block 21 and the touch line 22 may be identical (for example, metal molybdenum (Mo)), but may be sequentially produced in different processes.
  • the first via 81 is located in the vertical projection of the light shielding block 21, because in the embodiment, the light shielding block 21 and the touch control line 22 in the first metal layer 20 are integrally formed of the same material. Therefore, the light shielding block 21 and the touch line 22 are electrically connected to each other, so that when the first via 81 is located in the vertical projection of the light shielding block 21, the common electrode layer 80 is connected to the light shielding block 21, and because the light shielding block 21 is touched.
  • the control lines 22 are electrically connected to each other, and thus the common electrode layer 80 is equivalent to the connection of the touch lines 22. In other implementation scenarios, even if the light shielding block 21 and the touch control line 22 are not integrally formed, it is only necessary to partially overlap each other and to conduct each other to achieve the object of the present invention.
  • FIG. 3 is a top plan view of the first metal layer 20 and the semiconductor layer 40 of the touch display panel according to the second embodiment of the present invention.
  • the first via 81 is used for the common electrode layer 80 to be connected to the first metal layer 20 for touch.
  • the touch function of the display panel, the second via 91 is a display function for connecting the pixel electrode layer 100 and the drain electrode 41 to realize a touch display screen.
  • the positions of the first via 81 and the second via 91 can be referred to FIG. 3. As shown in FIG.
  • the positions of the first via 81 and the second via 91 are staggered from each other and are not close together, and The first via 81 is disposed farther from the vertical projection of the light blocking block 21 than the second via 91 disposed on the touch line 22 .
  • the interval between the first via 81 and the second via 91 can effectively avoid the process risk as long as it is not zero, and the further the first via 81 is separated from the second via 91, the less the process risk is.
  • the touch line and the light shielding block are disposed in the same layer in the first metal layer, and are connected to the common electrode layer through the first via hole to realize the touch function of the touch display panel, which can be simplified.
  • the steps of the touch line save production costs.
  • the touch line is connected to the partial light blocking block in the embodiment, the first via hole is disposed in the vertical projection area of the partial light blocking block to widen the first via hole and the second pass for connecting the drain electrode and the pixel electrode. The spacing between the holes improves process reliability.
  • FIG. 4 is a schematic flow chart of an embodiment of a method for manufacturing a touch display panel according to the present invention.
  • the method for manufacturing a touch display panel provided by the present invention includes the following steps:
  • a first metal layer is disposed on one side of the substrate, and the first metal layer includes a touch line and a light shielding block disposed on the substrate.
  • a first metal layer is disposed on one side of the substrate, and the first metal layer is formed on the substrate by using a metal molybdenum (Mo) material by physical vapor deposition, including shielding the backlight from the semiconductor.
  • Mo metal molybdenum
  • the touch line and the light blocking block in the first metal layer are integrally formed.
  • the touch line and the light blocking block in the first metal layer may be different materials and sequentially passed through different Process making.
  • a TFT functional layer is disposed on the first metal layer, and a first via hole is disposed on the TFT functional layer.
  • a TFT functional layer is disposed on the first metal layer, and the TFT functional layer includes: a buffer layer, a gate insulating layer, an interlayer insulating layer, and a planarization layer, and is in a buffer layer, a gate insulating layer, and a layer a first via hole is disposed at the same position of the interlayer insulating layer and the planarization layer,
  • the method for manufacturing the other layers except the first metal layer by the touch display panel is as follows: the buffer layer material is SiNx/SiOx, covering the first metal layer, and after being formed into a film, in a preset manner The position of the first via hole is punched. A layer of amorphous silicon is formed by chemical vapor deposition on the buffer layer and is converted into a semiconductor layer by excimer laser annealing. A gate insulating layer is deposited on the semiconductor layer by chemical vapor deposition, and the material composition thereof is SiOx. Similarly, the gate insulating layer is formed into a film and is opened at the position of the first via hole.
  • An interlayer insulating layer is deposited on the gate insulating layer by chemical vapor deposition, and the hole is opened at the position of the first via hole after the film is formed.
  • an additional via is required on the gate insulating layer, and the via is located above the semiconductor layer for providing the drain electrode and the source electrode.
  • the drain electrode and the source electrode are made by physical vapor deposition.
  • a common electrode layer is disposed on the TFT functional layer, and the common electrode layer and the touch control line are connected through the first via.
  • a common electrode layer is disposed on a side of the first metal layer away from the substrate, and the common electrode layer is connected to the first metal layer through the first via. Furthermore, a semiconductor layer is provided on the buffer layer, the position of the semiconductor layer being offset from the first via location. A source electrode and a drain electrode are disposed on the semiconductor layer, and positions of the source electrode and the drain electrode are shifted from the position of the first via hole.
  • the common electrode layer is formed by physical vapor deposition and is connected to the first metal layer through the first via. Since the positions of the semiconductor layer and the source and drain electrodes are all shifted from the first via, the second via connecting the drain electrode and the pixel electrode layer necessarily shifts the position of the first via.
  • the first via is located in a vertical projection area of a portion of the light blocking block.
  • the light shielding block and the touch line in the first metal layer are integrally formed of the same material, so that the light shielding block and the touch line are electrically connected to each other, so when the first via hole is located in the light shielding block
  • the common electrode layer is connected to the light shielding block in the vertical projection, and the common electrode layer is equivalent to the connection of the touch line because the light shielding block and the touch line are electrically connected to each other.
  • the first via is disposed in the vertical projection of the light blocking block farther than the second via hole disposed on the touch line. The further the first via is separated from the second via, the less the process risk is.
  • the touch line and the light shielding block are disposed in the same layer in the first metal layer, and the first metal layer is connected to the common electrode layer through the first via hole to realize the touch function of the touch display panel.
  • the steps of making the touch line can be simplified, and the manufacturing cost can be saved. Since the first via hole is provided in the vertical projection area of the partial light blocking block, the interval between the first via hole and the second via hole for connecting the drain electrode and the pixel electrode can be widened, thereby reducing the risk of the process.
  • the common electrode of the present invention connects the touch line located in the first metal layer through the first via hole, and the touch line is formed in the same layer or in the same process in the first metal layer. .
  • This can reduce the steps and costs of making the touch line, and simplifying the steps can also help reduce the risk of the process.
  • the touch line and the light blocking block partially overlap, so that the first opening can be disposed in the vertical projection of the partial light blocking block, so that the common electrode layer is connected to the touch layer through the light shielding block to realize the touch function. In this way, the position of the first via hole is farther away from other via holes that need to be opened, further reducing the process risk.

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Abstract

本发明公开了一种触摸显示面板及其制造方法。该触摸显示面板包括：基板；第一金属层，包括设置于基板之上的触控线和遮光块；TFT功能层，位于第一金属层之上，TFT功能层上设有第一过孔；公共电极层，位于TFT功能层之上，并与触控线通过第一过孔连接。通过上述方式，本发明能够降低制作成本，提高制程可靠性。

Description

一种触摸显示面板及其制造方法
【技术领域】
本发明涉及显示面板领域，特别是涉及一种触摸显示面板及其制造方法。
【背景技术】
LTPS（Low Temperature Poly-silicon，低温多晶硅技术）显示面板的触控类型常采用自感电容型，通过将sensor pad集成在阵列基板上实现ITP（In Cell Touch Panel，内嵌式触摸屏）提高产品的品质和价值。Sensor pad的结构一般包含Common ITO和触控线走线。触控线走线的制作可单独设计光罩，即单独设置触控线走线；也可以采用数据线的光罩，即与数据线同层设置或同一工艺形成，使用相同的金属同步制作的方式，但是两种方案都有成本和制程风险增加的问题。
【发明内容】
本发明主要解决的技术问题是提供一种触摸显示面板及其制造方法，能够降低制作成本，减小制程风险，提高制程可靠性。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种触摸显示面板，其中，包括：基板；第一金属层，所述第一金属层包括设置于所述基板之上的触控线和遮光块，所述触控线和部分的所述遮光块一体成型；TFT功能层，所述TFT功能层位于所述第一金属层之上，所述TFT功能层上设有第一过孔，所述第一过孔位于部分的所述遮光块的垂直投影内；公共电极层，位于第一金属层所述TFT功能层之上，并与所述触控线通过所述第一过孔连接。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种触摸显示面板，包括：基板；第一金属层，所述第一金属层包括设置于所述基板之上的触控线和遮光块；TFT功能层，所述TFT功能层位于所述第一金属层之上，所述TFT功能层上设有第一过孔；公共电极层，位于所述TFT功能层之上，并与所述触控线通过第一过孔连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种一种制造触摸显示面板的方法，包括：在基板的一侧设置第一金属层，所述第一金属层包括设置于所述基板之上的触控线和遮光块；在所述第一金属层之上设置TFT功能层，所述TFT功能层上设有第一过孔；在所述TFT功能层之上设置公共电极层，所述公共电极层与所述触控线通过第一过孔连接。
第一金属层本发明的有益效果是：区别于现有技术的情况，本发明通过将触控线与用于遮挡背光对半导体层的照射的遮光块同层设置或同一工艺形成，使得公共电极层可以通过第一过孔与触控线连接，以实现触摸显示面板的触摸功能，这样可以有效减少制造触控线时的成本，且第一开孔是在公共电极层下方，制程风险小。
【附图说明】
图1是本发明提供的触摸显示面板的一实施例的截面示意图；
图2是本发明提供的触摸显示面板的一实施例的第一金属层的俯视示意图；
图3是本发明提供的触摸显示面板的一实施例的第一金属层与半导体层俯视示意图；
图4是本发明提供的触摸显示面板的制造方法的实施例的流程示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，均属于本发明保护的范围。
请参阅图1，图1是本发明提供的触摸显示面板的第二实施例的截面示意图。触摸显示面板包括基板10、第一金属层20、缓冲层30、栅绝缘层50、层间绝缘层60和平坦化层70、公共电极层80、钝化层90、像素电极层100以及漏极电极41和源极电极42。缓冲层30、栅绝缘层50、层间绝缘层60和平坦化层70属于TFT功能层。其中，第一金属层20是以金属钼（Mo）为材料采用物理气相沉积的方法在基板10上制成的。基板10设有第一金属层20的一侧，第一金属层20远离基板10的一侧覆盖有缓冲层30，其材料组成为SiNx/SiOx。在缓冲层30远离基板10的一侧设置有半导体层40，半导体层40与第一金属层20在垂直投影方向上的覆盖面积至少部分重合，半导体层40的材料是使用准分子激光退火而从非晶硅转化而成的多晶硅。在半导体层40远离基板10的一侧设置有栅绝缘层50，其材料组成为SiOx。在栅绝缘层50远离基板10的一侧设置有层间绝缘层60。在层间绝缘层60上设置有漏极电极41和源极电极42，漏极电极41和源极电极42通过层间绝缘层60上的第二过孔91与半导体层40实现电连接。在层间绝缘层60远离基板10的一侧设置有平坦化层70。平坦化层70远离基板10的一侧还依次设置了钝化层90和像素电极层100。
其中，平坦化层70远离基板10的一侧设置有公共电极层80。缓冲层30、栅绝缘层50、层间绝缘层60和平坦化层70在相同的位置设置有第一过孔81，以使得公共电极层80通过该第一过孔81连接第一金属层20，实现触摸显示面板的触摸功能。为了能让共电极层顺利通过该第一过孔81连接第一金属层20，半导体层40以及设置在半导体层40上的漏极电极41和源极电极42都要错开第一开孔的位置。此外，层间绝缘层60上还设有第二过孔91，是为了让像素电极层100通过该第二过孔91与漏极电极41连接，以实现触摸显示面板的显示功能。因为半导体层40以及源极电极42和漏极电极41的位置都与第一过孔81错开，那么连接漏极电极41与像素电极层100的第二过孔91必然错开第一过孔81的位置。
请结合参考图2，图2是本发明提供的触摸显示面板的第二实施例的第一金属层20的俯视示意图。在图3中，可以看到，在本实施例中，第一金属层20包括用于与公共电极层80组合实现面板的触摸功能的触控线22和用于遮挡背光对半导体层40的照射的遮光块21。触控线22与至少一个遮光块21部分重叠。一般来说，第一金属层20的主要材料为金属钼（Mo），在本实施例中，触控线22与遮光块21采用相同的材料，使用同一工艺在层第一金属层20中制成。例如，采用物理气相沉积的方法，采用金属钼（Mo）一次性在基板10的表面制成如图3所示的包括触控线22和遮光块21的第一金属层20。采用这种方法，可以避免为了制成触控线22而单独制作光罩，一次性完成遮光块21与触控线22两者的布局，可以有效节约时间和制作成本，制作步骤简化，。
在其他实施例中，触控线22可以采用其他材料和/或其他工艺与遮光块21一起在第一金属层20中制成。例如，可以先使用一种工艺（例如，物理气相沉积）在基板10上沉积出若干个材料为金属钼（Mo）的遮光块21，然后在使用另一种工艺再在基板10上设置材料为金属铂的触控线22。在另外的实施例中，遮光块21和触控线22的材料可以一致（例如，金属钼（Mo）），但是可以先后以不同的工艺制得。
请继续参阅图3，第一过孔81位于遮光块21的垂直投影内，因为在本实施例中，第一金属层20中的遮光块21与触控线22是采用同种材料一体成型的，因此遮光块21与触控线22之间彼此导通，因此当第一过孔81位于遮光块21的垂直投影内即公共电极层80与遮光块21连接，而又因为遮光块21与触控线22之间彼此导通，因此公共电极层80等同于连接触控线22。在其他实施场景中，即使遮光块21与触控线22不是一体成型，但只需两者部分重叠，彼此导通也可以实现本发明的目的。
请结合参阅图1和图3，图3是本发明提供的触摸显示面板第二实施例的第一金属层20与半导体层40俯视示意图。根据图2可知，在平坦化层70上有第一过孔81和第二过孔91两种过孔，第一过孔81是用于公共电极层80与第一金属层20连接以实现触摸显示面板的触摸功能，第二过孔91是用于像素电极层100与漏极电极41连接以实现触摸显示屏的显示功能。第一过孔81和第二过孔91的位置可以参阅图3，如图3中所示的，第一过孔81和第二过孔91的位置相互错开，也没有紧靠在一起，且第一过孔81设在遮光块21的垂直投影内比设置在触控线22距离第二过孔91更远。第一过孔81与第二过孔91之间的间隔只要不为零即可以有效避免制程风险，且第一过孔81与第二过孔91相隔越远，制程风险就越小。
通过上述描述可知，本实施例通过将触控线与遮光块在第一金属层中同层设置，并通过第一过孔与公共电极层连接以实现触摸显示面板的触摸功能，可以简化制成触控线的步骤，节省制作成本。因为本实施例中触控线与部分遮光块连接，因此在部分遮光块的垂直投影区域设置第一过孔，以拉大第一过孔和用于连接漏极电极和像素电极的第二过孔之间的间隔，提高制程可靠性。
请参参阅图4，图4是本发明提供的触摸显示面板的制造方法的实施例的流程示意图。本发明提供的触摸显示面板的制造方法包括如下步骤：
S401：在基板的一侧设置第一金属层，所述第一金属层包括设置于所述基板之上的触控线和遮光块。
在一个具体的实施场景中，在基板的一侧设置第一金属层，第一金属层以金属钼（Mo）为材料采用物理气相沉积的方法在基板上制成，包括用于遮挡背光对半导体层的照射的遮光块和触控线，其中触控线与部分遮光块的部分区域重叠。在本实施场景中，第一金属层中的触控线与遮光块是一体成型，在其他实施场景中，第一金属层中的触控线和遮光块可以是由不同材料，先后分别通过不同工艺制作成型。
S402：在所述第一金属层之上设置TFT功能层，所述TFT功能层上设有第一过孔。
在一个具体的实施场景中，在第一金属层上设置TFT功能层，TFT功能层包括：缓冲层、栅绝缘层、层间绝缘层和平坦化层，并在缓冲层、栅绝缘层、层间绝缘层和平坦化层的相同的位置上设置第一过孔，
在本实施场景中，触摸显示面板除去第一金属层以外的其他各层的制作方法为：缓冲层材料为SiNx/SiOx，覆盖于第一金属层上，待其成膜后，在预设的第一过孔的位置打孔。在缓冲层上用化学气相沉积制作一层非晶硅，使用准分子激光退火转化成半导体层。在半导体层上使用化学气相沉积一层栅绝缘层，其材料组成为SiOx，同样的，栅绝缘层成膜后在第一过孔的位置开孔。栅绝缘层上用化学气相沉积一层层间绝缘层，同样等成膜后在第一过孔的位置开孔。此外，栅绝缘层上还需要开设另外的过孔，该过孔位于半导体层上方，用于设置漏极电极和源极电极。漏极电极和源极电极通过物理气相沉积制成。栅绝缘层成膜后开两个孔，一个为第一过孔，另一个为第二过孔，第二过孔用于连接漏极和像素电极层，以实现触摸显示面板的显示功能。制作平坦化层。
S403：在所述TFT功能层之上设置公共电极层，所述公共电极层与所述触控线通过第一过孔连接。
在一个具体的实施场景中，第一金属层远离基板的一侧设置公共电极层，该公共电极层通过该第一过孔连接第一金属层。此外在缓冲层上设置半导体层，该半导体层的位置错开所述第一过孔位置。半导体层上设置源极电极和漏极电极，所述源极电极和所述漏极电极的位置错开第一过孔的位置。
公共电极层通过物理气相沉积的方法制成，并通过第一过孔与第一金属层连接。因为半导体层以及源极电极和漏极电极的位置都与第一过孔错开，那么连接漏极电极与像素电极层的第二过孔必然错开第一过孔的位置。
在本实施场景中，第一过孔位于部分遮光块的垂直投影区域中。因为在本实施场景中，第一金属层中的遮光块与触控线是采用同种材料一体成型的，因此遮光块与触控线之间彼此导通，因此当第一过孔位于遮光块的垂直投影内即公共电极层与遮光块连接，而又因为遮光块与触控线之间彼此导通，因此公共电极层等同于连接触控线。第一过孔设在遮光块的垂直投影内比设置在触控线距离第二过孔更远。而第一过孔与第二过孔相隔越远，制程风险就越小。
通过上述描述可知，本实施例通过将触控线与遮光块在第一金属层中同层设置，与公共电极层通过第一过孔连接第一金属层以实现触摸显示面板的触摸功能，这可以简化制成触控线的步骤，节省制作成本。因在部分遮光块的垂直投影区域设置第一过孔，可以拉大第一过孔和用于连接漏极电极和像素电极的第二过孔之间的间隔，减小制程的风险。
区别于现有技术，本发明中的公共电极通过第一过孔连接位于第一金属层中的触控线，该触控线与遮光块在第一金属层中同层设置或同一工艺制得。这样可以减少制成触控线的步骤和成本，简化步骤也有利于降低制程的风险。此外，因为在本发明中触控线与遮光块存在部分重叠，因此可以将第一开孔设置在部分遮光块的垂直投影中，这样公共电极层通过遮光块连接触控层，实现触摸功能，这样第一过孔的位置距离其他需要开设的过孔更远，进一步降低制程风险。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种触摸显示面板，其中，包括：
    基板；
    第一金属层，所述第一金属层包括设置于所述基板之上的触控线和遮光块，所述触控线和部分的所述遮光块一体成型；
    TFT功能层，所述TFT功能层位于所述第一金属层之上，所述TFT功能层上设有第一过孔，所述第一过孔位于部分的所述遮光块的垂直投影内；
    公共电极层，位于第一金属层所述TFT功能层之上，并与所述触控线通过所述第一过孔连接。
  2. 根据权利要求1所述的面板，其中，
    所述第一金属层的材料包括金属钼。
  3. 根据权利要求1所述的面板，其中，所述TFT功能层包括：
    依次设置于所述第一金属层和所述公共电极层之间的缓冲层、栅绝缘层、层间绝缘层和平坦化层，所述缓冲层、所述栅绝缘层、所述层间绝缘层和所述平坦化层在相同的位置设有所述第一过孔，以使得所述公共电极层连接所述触控线。
  4. 根据权利要求3所述的面板，其中，
    所述缓冲层的材料包括氮化硅和氧化硅。
  5. 根据权利要求3所述的面板，其中，所述面板进一步包括：
    所述缓冲层上设置的半导体层，所述半导体层的位置错开所述第一过孔位置；
    所述半导体层上设置源极电极和漏极电极，所述源极电极和所述漏极电极的位置错开所述第一过孔的位置。
  6. 根据权利要求5所述的面板，其中，
    所述半导体层的材料包括多晶硅。
  7. 一种触摸显示面板，其中，包括：
    基板；
    第一金属层，所述第一金属层包括设置于所述基板之上的触控线和遮光块；
    TFT功能层，所述TFT功能层位于所述第一金属层之上，所述TFT功能层上设有第一过孔；
    公共电极层，位于第一金属层所述TFT功能层之上，并与所述触控线通过所述第一过孔连接。
  8. 权利要求7所述的面板，其中，
    所述第一过孔位于部分的所述遮光块的垂直投影内。
  9. 权利要求7所述的面板，其中，
    所述触控线和部分的所述遮光块一体成型。
  10. 根据权利要求7所述的面板，其中，
    所述第一金属层的材料包括金属钼。
  11. 权利要求7所述的面板，其中，所述TFT功能层包括：
    依次设置于所述第一金属层和所述公共电极层之间的缓冲层、栅绝缘层、层间绝缘层和平坦化层，所述缓冲层、所述栅绝缘层、所述层间绝缘层和所述平坦化层在相同的位置设有所述第一过孔，以使得所述公共电极层连接所述触控线。
  12. 根据权利要求11所述的面板，其中，
    所述缓冲层的材料包括氮化硅和氧化硅。
  13. 根据权利要求12所述的面板，其中，所述面板进一步包括：
    所述缓冲层上设置的半导体层，所述半导体层的位置错开所述第一过孔位置；
    所述半导体层上设置源极电极和漏极电极，所述源极电极和所述漏极电极的位置错开所述第一过孔的位置。
  14. 根据权利要求13所述的面板，其中，
    所述半导体层的材料包括多晶硅。
  15. 一种制造触摸显示面板的方法，其中，包括：
    在基板的一侧设置第一金属层，所述第一金属层包括设置于所述基板之上的触控线和遮光块；
    在所述第一金属层之上设置TFT功能层，所述TFT功能层上设有第一过孔；
    在所述TFT功能层之上设置公共电极层，所述公共电极层与所述触控线通过第一过孔连接。
  16. 根据权利要求15所述的方法，其中，
    所述第一过孔位于部分的所述遮光块的垂直投影内。
  17. 根据权利要求15所述的方法，其中，
    所述在基板的一侧设置第一金属层包括：
    在同一工艺中形成所述触控线和与其一体成型的部分的所述遮光块。
  18. 根据权利要求15所述的方法，其中，在基板上设置第一金属层的步骤之后，所述方法进一步包括：
    所述遮光块上依次设置缓冲层、栅绝缘层、层间绝缘层和平坦化层，并在缓冲层、所述栅绝缘层、所述层间绝缘层和所述平坦化层的相同的位置上设置第一过孔，以使得所述公共电极层连接所述遮光块。
  19. 根据权利要求18所述的方法，其中，所述遮光块上设置缓冲层的步骤之后，所述方法进一步包括：
    在所述缓冲层上设置半导体层，所述半导体层的位置错开所述第一过孔位置；
    在所述半导体层上设置源极电极和漏极电极，所述源极电极和所述漏极电极的位置错开所述第一过孔的位置。
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