CN104937596A - 用于3d集成电路的时钟分布网络 - Google Patents

用于3d集成电路的时钟分布网络 Download PDF

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CN104937596A
CN104937596A CN201380071377.XA CN201380071377A CN104937596A CN 104937596 A CN104937596 A CN 104937596A CN 201380071377 A CN201380071377 A CN 201380071377A CN 104937596 A CN104937596 A CN 104937596A
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clock
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K·萨马迪
S·A·潘
J·谢
Y·杜
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Abstract

本发明的示例性实施例涉及用于设计用于集成电路的时钟分布网络(34)的系统和方法。实施例识别时钟偏移的关键来源，严格控制时钟的时序并将该时序构建到总体时钟分布网络和集成电路设计中。所公开的实施例将时钟分布网络(CDN)，即时钟发生电路、接线、缓冲和寄存器，与逻辑的其余部分分离，以改进时钟树设计并减小面积占用。在一个实施例中，CDN被分离到3D集成电路(31)的单独的层(34)，并且CDN经由高密度层间通孔(13)而被连接到(多个)逻辑层。实施例对于具有单片式3D集成电路的实施方式尤其有利。

Description

用于3D集成电路的时钟分布网络
根据35U.S.C§119的优先权主张
本专利申请要求如下申请的优先权：
2012年11月28日提交、题为“CLOCK DISTRIBUTION NETWORKFOR 3D INTEGRATED CIRCUIT”、并且被转让给本申请的受让人的临时申请No.61/730755，并且通过引用的方式被明确地并入本文中。
2012年11月28日提交、题为“DATA TRANSFER ACROSS POWERDOMAINS”、并且被转让给本申请的受让人的临时申请No.61/730767，并且通过引用的方式被明确地并入本文中。
对共同未决的专利申请的引用
本专利申请涉及以下共同未决的(多个)美国专利申请：
2013年3月5日提交的Yang Du、Jing Xie和Kambiz Samadi的“MONOLITHIC 3D IC FLIP-FLOP DESIGN”，代理人案号No.123412，被转让给本申请的受让人，并且通过引用的方式被明确地并入本文中；
2013年3月7日提交的Yang Du的“MONOLITHIC THREEDIMENSIONAL INTEGRATION OF SEMICONDUCTOR INTEGRATEDCIRCUITS”，代理人案号No.120600，被转让给本申请的受让人，并且通过引用的方式被明确地并入本文中；以及
[****]提交的Jing Xie和Yang Du的“DATA TRANSFER ACROSSPOWER DOMAINS”，代理人案号No.124716，被转让给本申请的受让人，并且通过引用的方式被明确地并入本文中。
技术领域
所公开的实施例总体上涉及集成电路中的时钟信号的产生。更具体而言，所公开的实施例涉及用于开发具有高速度、低偏移和低功耗的可缩放时钟分布网络的高效率系统和方法。
背景技术
在同步集成电路(IC)中，时钟信号用于为电路内的数据的移动定义时间参考。IC的时钟分布网络(例如，时钟发生电路、接线、缓冲和寄存器)产生时钟信号并将它们从特定点分布到需要它们的所有电路元件。同步IC的性能严重依赖于其时钟分布网络设计。时钟分布网络的适当设计有助于确保满足关键的时序要求并且控制时钟偏移。随着IC变得越来越大，它们的时钟分布网络开始占据设计资源的很大部分。时钟信号通常具有最大的扇出，并且必须要在整个设计内的任何控制或数据信号的最高速度下进行操作。时钟功率通常超过典型IC的总功耗的三分之一，并且是由于(i)时钟树接线、(ii)时钟树缓冲、以及(iii)时钟树汇点(例如，触发器)。因此，考虑到大型IC中的现有偏移/旋转约束，开发可缩放的、高速、高性能且低功耗的时钟分布网络设计是极其困难的。
3D IC是能够提供较高性能/较低功率设计的新兴技术。然而，已知的3D IC实施方式容易加剧时钟分布网络设计的难题，因为时钟信号不得不在严苛的偏移/旋转约束下可靠地跨越多个层。因此，不同的层将具有其自己的时钟树网络。还不可能在跨越不同层的不同时钟网络间满足偏移/旋转约束而不降低性能和功率。为了应对这个问题，需要芯片级的异步操作，而其在包括功耗、速度和面积占用的各种参数上具有其自己的缺点。
因此，需要用于开发可缩放、低偏移、高速和高性能的时钟分布网络的系统和方法。还需要用于在3D IC内开发可缩放、低偏移、高速和高性能的时钟分布网络的系统和方法。
发明内容
本发明的示例性实施例涉及用于设计用于集成电路的时钟分布网络的系统和方法。实施例识别时钟偏移的关键来源，严格控制时钟的时序并将该时序构建到总体时钟分布网络和集成电路设计中。所公开的实施例将时钟分布网络(CDN)，即时钟发生电路、接线、缓冲和寄存器，与逻辑的其余部分分离，以改进时钟树设计并减小面积占用。在一个实施例中，CDN被分离到3D集成电路的单独的层，并且CDN经由高密度层间通孔而连接到(多个)逻辑层。实施例对于具有单片式3D集成电路的实施方式尤其有利。
所公开的实施例包括开发用于集成电路的时钟分布网络的方法，步骤包括：捕捉时钟偏移的来源，所述来源包括时钟汇点之间的时序失配；合成集成电路和时钟偏移的所述来源的较高级行为描述，以产生包括时钟分布网络和组合逻辑的2D布局；将所述时钟分布网络与所述组合逻辑分离，并且将所述时钟分布网络设置在集成电路的第一区域；以及对所述第一区域的所述组合逻辑进行布图规划。在另一实施例中，集成电路包括多层电路；所述第一区域包括所述多层电路的第一层；并且所述组合逻辑位于所述多层电路的第二层。
所公开的实施例还包括集成电路的时钟分布网络，其包括：被分离到所述集成电路的第一区域的时钟分布网络；被分离到所述集成电路的第二区域的所述集成电路的组合逻辑；以及将所述第一区域连接到所述第二区域的通孔。在另一实施例中，集成电路还包括：包括多层电路的集成电路；所述第一区域包括所述多层电路的第一层；并且所述第二区域包括所述多层电路的第二层。
附图说明
给出附图以辅助描述所公开的实施例，并且附图仅是出于说明实施例而非限制实施例的目的而提供的。
图1是示出所公开的实施例的方法的高级流程图；
图2是图1流程图的更详细的示例；
图3是所公开的实施例的2D时序弧和3D时序弧的示例；
图4是图3的时钟分布网络的更详细的示例；以及
图5是图4的时钟分布网络的另一个更详细的示例。
具体实施方式
在以下描述和涉及本发明的具体实施例的相关附图中公开了本发明的各方面。可以在不脱离本发明的范围的情况下构思替代的实施例。另外，本发明的公知元件将不会被详细描述或将被省略，以避免使本发明的相关细节难以理解。
本文使用词语“示例性”来表示“用作示例、实例或例证”。本文被描述为“示例性”的任何实施例不一定被解释为相对于其它实施例是优选或有利的。同样地，术语“本发明的实施例”不需要本发明的所有实施例都包括所论述的特征、优点或操作模式。
本文使用的术语仅仅是出于描述特定实施例的目的，并且并不是要限制本发明的实施例。如本文所用，除非上下文另外明确指示，否则单数形式“一”和“该”旨在也包括复数形式。要进一步理解的是，在本文中使用时，术语“包括”、“包含”指定所论述的特征、整数、步骤、操作、元件和/或部件的存在，但不排除存在或增加一个或多个其它特征、整数、步骤、操作、元件、部件和/或其组。
此外，根据要由例如计算设备的元件执行的动作的顺序来描述许多实施例。将要认识到，可以由特定电路(例如，特殊应用集成电路(ASIC))、由被一个或多个处理器执行的程序指令、或由两者的组合来执行本文描述的各种动作。另外，本文描述的动作的顺序可以被认为完全体现于任何形式的计算机可读存储介质内，该存储介质中存储了对应的计算机指令集，该指令集在被执行时会使相关联的处理器执行本文描述的功能。因此，本发明的各方面可以以许多不同形式来体现，所有形式都被认为是处于所要求保护的主题的范围内。另外，对于本文中描述的实施例中的每一个，例如，任何这种实施例的对应形式在本文中可以被描述为“被配置为”执行所述动作的“逻辑”。
图1是示出所公开的实施例的设计技术100的高级方框图。设计技术100开发了严格控制时钟的时序并将该时序构建到总体IC设计中的时钟分布网络(CDN)。IC可以包括数字部件、模拟部件或两者的组合。在本公开内容中的各处对“逻辑”电路的引用旨在涵盖数字电路部件、模拟电路部件及两者的组合。设计技术100在步骤102执行合成操作，其采用较高级的行为描述，并将其合成到执行所描述的操作的复杂逻辑电路中。可以将较高级的行为描述实施为能够映射到门函数库的寄存器传输级(RTL)描述。RTL描述描述了电路的寄存器和寄存器之间的传输序列。在步骤102执行的合成捕捉了时钟分布网络时序信息。
步骤104将CDN(包括时钟发生电路、接线、缓冲和寄存器)与步骤102处开发的其余组合逻辑分离。由于CDN与组合逻辑的其余部分分离，所以单独的CDN覆盖较小的面积。较小的CDN产生较小的缓冲、较少的接线和减小的功率。分离CDN降低了组合逻辑的复杂性，以实现较好的可布线性、减小的线路长度、提高的性能以及减小的功耗。步骤106将布图规划技术应用于单独的组合逻辑。如本公开内容随后所更详细描述的，布图规划技术可以是2D或3D的。在步骤108，通孔被绘制以将单独的CDN的时钟汇点连接到单独的组合逻辑的对应逻辑。通孔优选是能够在单个半导体晶片上的各层中以高密度制造的类型。步骤110将其它优化技术应用于被分离且经布图规划的CDN，直到已经实现了期望的总体性能参数。
图2是设计技术200的流程图，设计技术200是图1中所示的设计技术100的更详细的实施方式。可以有利地将设计技术200应用于3D IC。针对功能块执行步骤202到210，并且在3D IC的块级上执行步骤212到218。步骤202处执行的合成操作实质上与步骤102处执行的合成操作相同。步骤204将时钟汇点移动到单独的CDN区域并利用端口替代合成电路的时钟汇点，以提供时钟汇点在每个功能块内部的实际位置的指示。根据设计技术200的单独的CDN区域优选是专用于CDN(时钟发生电路、接线、缓冲、寄存器等)的3D IC的单独的层。步骤206为CDN层与组合逻辑之间的通孔连接确定放置阻塞部位。通孔连接时钟汇点在合成电路中所处的位置。因为通孔是高密度的，所以用于特定时钟汇点的通孔的数量可以对应于来自时钟汇点的输出的数量。例如，在时钟汇点是触发器并且通孔是层间通孔的情况下，可以为特定触发器分配k个层间通孔，其中k代表至触发器输出的连接的数量。步骤206优选地以网状方式插入阻塞，以提高时钟汇点在整个块中的可到达性。步骤208在逻辑层上放置组合逻辑，并且步骤210将时钟汇点中的每一个映射到其相关联的阻塞部位。
在3D IC的块级上执行步骤212到218。步骤212将布图规划技术应用于逻辑层。由于所公开的实施例是可缩放的，所以通过增加更多的CDN层来容纳越来越大的IC和CDN。因此，步骤212的布图规划技术可以是2D(单CDN层)或3D(多CDN层)。步骤214到218将其它优化技术应用于被分离且经布图规划的逻辑和CDN，直到已经实现了期望的总体性能参数。步骤214将时钟树合成应用于经布图规划的CDN层。时钟树合成包括时钟缓冲插入，并且利用与来自步骤206的阻塞部位的放置有关的信息。步骤216执行块级布线，并且步骤218执行后布线优化。可以使用常规的2D后布线优化引擎来实现步骤218。
因此，上述设计技术提供了许多益处。多层设计中的至少一层主要专用于容纳CDN，因此不必为每层设计时钟树，从而降低了设计复杂性。而且，根据所公开的实施例的设计方法，存在更少的金属层，与已知的3D集成电路技术相比，这节省了成本。较小的CDN占用面积导致较少的时钟功率(例如，大约30％的功率降低)，这实现了较少的接线和较少的缓冲。从所公开的实施例的方法获得的时钟树设计更精炼，因为所有的时钟汇点和CDN(包括时钟缓冲器)都在一层上。分离的CDN对于工艺偏差明显更鲁棒(由于占用面积较小，甚至比2D更鲁棒)。由于逻辑层上的逻辑复杂性较小，因而减小了线路长度，实现了改进的性能。改进的时钟树设计实现了改进的时序收敛。设计复杂性降低是因为：(i)可以将现有的2D时序优化引擎用于没有针对时序优化的3D网络的实施例，(ii)扫描链布线得以简化，因为不必通过逻辑层。在现有顺序(非存储器)与组合单元相比占据大约一半设计区域的情况下，层间容易得到平衡。
图3-5示出了通过实施图1和2所示的设计技术可以得到的电路布局的一般构造。图3示出了2D时序弧10和3D时序弧30的示例。图3-5是一般构造，其宽泛地代表某些类型的电路/元件(例如，时钟发生、接线、组合逻辑、时钟汇点)，但并非要传达特定的电路示例。时序弧10包括时钟发生模块(CGM)14、时钟汇点(CS)16、18、接线11和组合逻辑20，全部都是2D形式并且散布于整个单层12中。在实践中，可以将CGM 14实施为锁相环电路，并且可以将时钟汇点16、18实施为触发器电路。通常，时序弧10、30准确地捕捉时钟偏移的关键来源，例如包括从所谓的启动时钟汇点16到所谓的捕捉时钟汇点18的设计和/或延迟失配。因此，时钟时序要求受到严格控制并且被构造到总体IC设计中。
时序弧30示出了分离到多层IC 31的单层34的CDN(CGM 14、CS 16、18、19和接线11)。时序严格的组合逻辑20是在分离CDN之后放置的。在CDN不占据整个层的限度内，可以在同一CDN层上放置时序严格的组合逻辑20的一些或全部。因此，如果在放置CDN之后仍有空间，可以将时序严格的组合逻辑20放置于CDN层34上，或者将其放置于与CDN层34相邻的层32或36上。如果在放置CDN和任何时序严格的组合逻辑20之后仍有空间，则还可以将非时序严格的组合逻辑40放置于CDN层34上，或者放置在任何其它层32、36、38、39上，无论该层是否与CDN层相邻。高密度通孔13被构建到多层电路31中并且将CS 16、18、19连接到时序严格的组合逻辑20。
时序弧30还示出了所公开的实施例的可缩放性。对于越来越大的IC而言，多层电路31是容易缩放的，只要将CDN分离到容纳CDN的尺寸所需的数量的层。在图3中所示的示例中，CDN(16，18，19，14，11)在单层34上，但如果CDN尺寸增大，其可以扩展到更多CDN层(未示出)。类似地，随着时序严格的组合逻辑20的尺寸增大，可以添加附加层以容纳较大的时序严格的逻辑，只要附加层是CDN层或与CDN层相邻。最后，随着非时序严格的组合逻辑40的尺寸增大，可以添加附加层以容纳较大的非时序严格的组合逻辑。
图4是通过实施图1和2中所示的设计技术能够得到的电路布局的一般构造的另一图示。类似于图3的时序弧，图4示出了具有CDN和对应的逻辑的2D布局以及2D布局的多层实施方式的示例。图4是一般构造，其宽泛地代表某些类型的电路/元件(例如，时钟发生、接线、组合逻辑、时钟汇点)，但并非要传达特定的电路示例。2D布局10a包括时钟发生模块(CGM)15、时钟汇点(CS)16、接线11和组合逻辑20，全部都是2D形式并且散布于整个单层12中。在实践中，可以将CGM 15实施为锁相环电路，并且可以将时钟汇点16实施为触发器电路。为简单起见以H树的格式示出了接线11，但其可以被实施成多种不同的时钟树格式(例如，栅格、棘状等)。通常，2D布局10准确地捕捉时钟偏移的关键来源，例如包括时钟汇点16之间的设计和/或延迟失配。由此，时钟时序要求受到严格控制并且被构建到总体IC设计中。
图4进一步示出了被分离到多层IC 31a的单层34的CDN(时钟缓冲器15、CS 16和接线11)。时序严格的组合逻辑20是在分离CDN之后放置的。在CDN不占据整个层的限度内，可以在同一CDN层上放置时序严格的组合逻辑20的一些或全部。因此，如果在放置CDN之后仍有空间，则可以将时序严格的组合逻辑20放置于CDN层34上，或者将其放置于与CDN层34相邻的任何层(例如，层36)上。如果在放置CDN和任何时序严格的组合逻辑20之后仍有空间，则还可以将非时序严格的组合逻辑40(图3中所示)放置于CDN层34上，或者将其放置于任何其它层32、36、38(图3中所示)上，无论该层是否与CDN层相邻。高密度通孔13被构建到多层电路31中并且将CS 16连接到时序严格的组合逻辑20。
图5是图3和4所示的多层电路31a的更详细示例。图5的多层电路被示出为单片式3D IC 33，其至少具有CDN层34和逻辑层36。图5的时钟汇点被实施为触发器(FF)电路17。图3和4的高密度通孔13被实施并在图5中被示出为单片式层间通孔(MIV)15。在单片式3D IC中，电子部件及其连接(接线)构建在单个半导体晶片上的层中，该单个半导体晶片然后被切割成3D IC。仅存在一个衬底，因此不需要对准或穿硅通孔。
因此，上述实施例将时钟分布网络与逻辑的其余部分分离。优选地，使用单片式3D集成技术来实施时钟分布网络。因此，单个层将主持时钟子系统，并且(多个)其它层将容纳其余的组合逻辑。根据本公开内容的时钟层将包括时钟发生电路(即，PLL或DLL)、时钟分布接线(H树、栅格、棘状等)和设计的时序元件中的大多数(例如，75％)。时钟层将包含最宽的金属线，以实现更好的时钟分布控制。由于时钟分布与逻辑的其余部分分离，因而时钟分布网络包括较小的占用面积。较小的时钟网络导致较小的缓冲器、较少的接线和减小的功率。将时钟分布分离降低了逻辑层的复杂性，以实现更好的可布线性、减少的线路长度、提高的性能和减小的功耗。由单片式3D集成提供的高密度层间通孔用于将时钟层上的时钟汇点连接到逻辑层上的对应逻辑。
尽管以上公开内容和图示示出了本发明的实施例，但应当注意，可以在不脱离由所附权利要求限定的本发明的范围的情况下对本文做出各种改变和修改。例如，不必按照任何特定次序来执行根据本文描述的发明的实施例的方法权利要求的功能、步骤和/或动作。此外，尽管可以采用单数形式来描述或要求保护本发明的元件，但是除非明确指出限制为单数，否则也考虑了复数形式。
相关领域的技术人员还将领会，可以将结合本文中所公开的实施例所描述的各种说明性的逻辑块、装置、电路和算法步骤实施为电子硬件、计算机软件、或两者的组合。为了清楚地示出硬件与软件的该互换性，上文总体上在其功能方面对各种说明性部件、方框、装置、电路和步骤进行了描述。这种功能被实施为硬件或软件取决于特定应用和施加在整体系统上的设计约束。对于每个特定应用，技术人员可以采用不同方式来实施所描述的功能，但是这种实施方式决策不应该被理解为脱离本发明的范围。
结合本文中公开的实施例所描述的方法、序列和/或算法可以直接体现在硬件、由处理器执行的软件装置、或两者的组合中。软件装置可以存在于RAM存储器、闪速存储器、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移除磁盘、CD-ROM、或本领域中已知的任何其它形式的存储介质中。示例性存储介质耦合到处理器，以使处理器能够从存储介质读取信息并向其写入信息。在替代方案中，存储介质可以与处理器是一体的。因此，本发明的实施例可以包括体现用于执行所公开并要求保护的实施例的方法的计算机可读介质。因此，本发明不限于所示示例，并且用于执行本文所述功能的任何装置都包括在本发明的实施例中。

Claims (25)

1.一种开发用于集成电路的时钟分布网络的方法(100)，步骤包括：
捕捉时钟偏移的来源，所述来源包括时钟汇点之间的时序失配；
合成(102)集成电路与所述时钟偏移的来源的高级行为描述，以产生包括时钟分布网络和组合逻辑的2D布局；
将所述时钟分布网络与所述组合逻辑分离(104)，并且将所述时钟分布网络设置在所述集成电路的第一区域；以及
对所述第一区域的所述组合逻辑进行布图规划(106)。
2.根据权利要求1所述的方法，还包括将进一步优化应用(110)于所述第一区域的所述时钟分布网络的步骤。
3.根据权利要求2所述的方法，其中，所述进一步优化包括时钟树合成(214)。
4.根据权利要求3所述的方法，其中，所述进一步优化包括块级布线(216)。
5.根据权利要求4所述的方法，其中，所述进一步优化包括后布线优化(218)。
6.根据权利要求2所述的方法，其中：
所述集成电路包括多层电路(31)；
所述第一区域包括所述多层电路的第一层(34)；并且
所述组合逻辑位于所述多层电路的第二层(36)。
7.根据权利要求6所述的方法，其中，所述第一层与所述第二层相邻。
8.根据权利要求6所述的方法，其中，从所述时钟分布网络到所述组合逻辑的连接包括通孔(13)。
9.根据权利要求8所述的方法，其中，所述通孔包括层间通孔。
10.根据权利要求9所述的方法，其中，所述层间通孔包括高密度。
11.根据权利要求6所述的方法，其中：
所述组合逻辑还包括非时序严格的组合逻辑(40)；并且
所述非时序严格的组合逻辑位于所述多层电路的第三层(38)。
12.根据权利要求11所述的方法，其中，所述第三层与所述第一层不相邻。
13.根据权利要求6所述的方法，其中：
所述组合逻辑还位于所述多层电路的第四层(32)；并且
所述第四层与所述第一层相邻。
14.根据权利要求13所述的方法，其中：
所述组合逻辑包括其它非时序严格的组合逻辑(40)；并且
所述其它非时序严格的组合逻辑位于所述多层电路的第五层(39)。
15.根据权利要求14所述的方法，其中，所述第五层与所述第一层不相邻。
16.一种集成电路(33)装置的时钟分布网络(34)，包括：
被分离到所述集成电路的第一区域(34)的所述时钟分布网络；
被分离到所述集成电路的第二区域(36)的所述集成电路的组合逻辑(20)；以及
将所述第一区域连接到所述第二区域的通孔(15)。
17.根据权利要求16所述的装置，其中：
所述集成电路包括多层电路(34，36)；
所述第一区域包括所述多层电路的第一层(34)；并且
所述第二区域包括所述多层电路的第二层(36)。
18.根据权利要求17所述的装置，其中，所述第一层与所述第二层相邻。
19.根据权利要求16所述的装置，其中，所述通孔包括层间通孔(15)。
20.根据权利要求19所述的装置，其中，所述层间通孔包括高密度。
21.根据权利要求17所述的装置，其中：
所述集成电路还包括非时序严格的组合逻辑(40)；所述非时序严格的组合逻辑被分离到所述集成电路的第三区域(38)；并且
所述第三区域包括所述多层电路的第三层。
22.根据权利要求21所述的装置，其中，所述第三层与所述第一层不相邻。
23.根据权利要求17所述的装置，其中：
所述组合逻辑还位于所述多层电路的第四层(32)；并且
所述第四层与所述第一层相邻。
24.根据权利要求23所述的装置，其中：
所述集成电路还包括非时序严格的组合逻辑(40)；并且
所述非时序严格的组合逻辑位于所述多层电路的第五层(39)。
25.根据权利要求24所述的装置，其中，所述第五层与所述第一层不相邻。
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