CN104282683B - 半导体组件及制造方法 - Google Patents
半导体组件及制造方法 Download PDFInfo
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Abstract
本发明为半导体组件及制造方法。提出了一种单片集成半导体组件。该半导体组件包括具有碳化硅(SiC)的衬底,和在衬底上制造的氮化镓(GaN)半导体器件。该半导体组件还包括制造在衬底中或衬底上的至少一个瞬态电压抑制器(TVS)结构,其中TVS结构与GaN半导体器件电接触。该TVS结构被配置成当跨GaN半导体器件施加的电压大于阈值电压时,在击穿模式、雪崩模式或其组合模式下操作。还提出了一种制造单片集成半导体组件的方法。
Description
技术领域
本发明一般涉及到氮化镓(GaN)基半导体器件的过压保护,以及更具体地,涉及到GaN基晶体管的过压保护。
背景技术
GaN半导体器件诸如场效应晶体管(FET)、特别是高电子迁移率场效应晶体管(HEMT)跨越各行业得到应用,诸如医疗、国防、航空等。但是,GaN器件易于受到由于电路和静电放电(ESD)中的瞬态事件导致的电过应力的影响。电应力会引起器件中的雪崩,这会导致器件老化以及最终灾难性的故障。虽然GaN开关具有若干优势,但是该安全性考虑(由于可忍受的雪崩方面的不足)已经排除了其在高速开关和功率电子系统中的广泛应用。
GaN基器件,特别是晶体管,由于晶体缺陷而已经不能展示持续的雪崩。观测到由于在诸如硅、蓝宝石、碳化硅(SiC)或其他材料的外来衬底上生长GaN材料引起的高密度(大于1000每平方厘米)缺陷,导致GaN材料不能保持稳定雪崩条件,引起GaN材料物理上退化且不可逆。
更广为人知作为浪涌电压保护器的瞬态电压抑制器(TVS)器件是用于保护敏感电子器件不受诸如尖峰电压损伤的电子部件。瞬态或过电压(或电流)是可伤害敏感电子电路的电压(或电流)的瞬态或短暂浪涌。
硅基TVS器件通常用于保护敏感电子部件免受由雷击或电磁干扰引起的电流或电压瞬态。但是,硅基TVS器件更倾向于随着温度增加而产生高泄漏电流。特别是,当环境温度达到不可接受的高值时,例如225摄氏度,由于过多的泄漏电流导致硅基TVS器件变得不适合操作。
因此,需要一种GaN器件的过压保护,以排除雪崩条件。而且,希望在高温操作(大于150摄氏度)期间提供GaN器件的过压保护。
发明内容
本技术的一个方面涉及到单片集成的半导体组件。该半导体组件包括含有SiC的衬底,和制造在衬底上的GaN半导体器件。该半导体组件还包括制造在衬底中或衬底上的至少一个瞬态电压抑制器(TVS)结构,其中TVS结构与GaN半导体器件电接触。该TVS结构被配置成当跨GaN半导体器件施加的电压大于阈值电压时,在击穿(punch-through)模式、雪崩模式或者其组合模式下操作。
本技术的另一方面涉及到单片集成的半导体组件。该半导体组件包括含有SiC的衬底,和制造在衬底上的GaN半导体器件。该半导体组件还包括含有制造在衬底中或上的SiC的至少一个TVS结构。该TVS结构与GaN半导体器件电接触,以及该TVS结构被配置成当跨GaN半导体器件施加的电压大于阈值电压时以击穿模式操作。
本技术的另一方面涉及到制作单片集成的半导体组件的方法。该方法包括(a)提供含有SiC的衬底;(b)在衬底上制造GaN半导体器件;(c)在衬底中或上制造至少一个TVS;和(d)将TVS结构和GaN半导体器件电耦合。该TVS结构被配置成当跨GaN半导体器件施加的电压大于阈值电压时,以击穿模式、雪崩模式或者其组合模式操作。
根据本公开的第一方面,提供了一种单片集成的半导体组件,包括:
包括碳化硅(SiC)的衬底;
制造在衬底上的氮化镓(GaN)半导体器件;和
制造在衬底中或上的至少一个瞬态电压抑制器(TVS)结构,
其中TVS结构与GaN半导体器件电接触,并且其中TVS结构被配置成当跨GaN半导体器件施加的电压大于阈值电压时,以击穿模式、雪崩模式或者其组合模式操作。
根据第一方面的半导体组件,其中TVS结构包括碳化硅、氮化镓、金刚石、氮化铝、氮化硼或其组合物中的至少一种。
根据第一方面的半导体组件,其中TVS结构横向配置。
根据第一方面的半导体组件,其中TVS结构垂直配置。
根据第一方面的半导体组件,其中TVS结构包括:
具有第一导电类型的第一半导体区;
具有第二导电类型且与第一半导体区电接触的第二半导体区;和
具有第一导电类型且与第二半导体区电接触的第三半导体区。
根据第一方面的半导体组件,其中第一导电类型是n+型和第二导电类型是p型。
根据第一方面的半导体组件,其中第一半导体区、第二的半导体区和第三半导体区形成在SiC衬底中。
根据第一方面的半导体组件,其中第一半导体区、第二半导体区和第三半导体区外延生长在SiC衬底上。
根据第一方面的半导体组件,其中TVS结构还包括设置在SiC衬底至少一部分上的GaN层,和其中第一半导体区、第二半导体区和第三半导体区形成在GaN层中。
根据第一方面的半导体组件,其中TVS结构经由栅-源端子、漏-源端子、栅-漏端子或者其组合与GaN半导体器件电接触。
根据第一方面的半导体组件,其中GaN半导体器件包括高电子迁移率晶体管(HEMT)、结栅场效应晶体管(JFET)、金属氧化物半导体场效应晶体管(MOSFET)、二极管或其组合等。
根据本公开的第二方面,提供了—种单片集成的半导体组件,包括:
包括碳化硅(SiC)的衬底;
制造在衬底上的氮化镓(GaN)半导体器件;和
包括制造在衬底中或上的碳化硅(SiC)的至少一个瞬态电压抑制器(TVS)结构,
其中TVS结构与GaN半导体器件电接触,并且其中TVS结构被配置成当跨GaN半导体器件施加的电压大于阈值电压时,在击穿模式下操作。
根据第二方面的单片集成组件,其中该组件被配置成在大于150摄氏度的温度下操作。
根据第二方面的单片集成组件,其中该组件被配置成在90%击穿电压下具有低于约1μA/cm2的泄漏电流。
根据第二方面的单片集成组件,其中该组件被配置成具有大于约150A/cm2的操作电流密度。
根据本公开的第三方面,提供了一种制造单片集成半导体组件的方法,包括:
(a)提供包括碳化硅(SiC)的衬底;
(b)在衬底上制造氮化镓(GaN)半导体器件;
(c)在衬底中或上制造至少一个瞬态电压抑制器(TVS);和
(d)将TVS结构与GaN半导体器件电耦合,
其中,TVS结构被配置成当跨GaN半导体器件施加的电压大于阈值电压时,在击穿模式、雪崩模式或者其组合模式下操作。
根据第三方面的方法,其中步骤(c)包括:
形成第一导电类型的第一半导体区;
形成第二导电类型且与第一半导体区电接触的第二半导体区;和
形成第一导电类型且与第二半导体区电接触的第三半导体区。
根据第三方面的方法,其中第一导电类型是n+型和第二导电类型是p型。
根据第三方面的方法,其中步骤(c)包括通过离子注入在SiC衬底中形成第一半导体区、第二半导体区和第三半导体区。
根据第三方面的方法,其中步骤(c)包括在SiC衬底上外延生长第一半导体区、第二半导体区和第三半导体区。
根据第三方面的方法,还包括在SiC衬底的至少一部分上设置GaN层,和在GaN层内形成第一半导体区、第二半导体区和第三半导体区。
根据第三方面的方法,其中步骤(d)包括经由栅-源端子、漏-源端子、栅-漏端子或其组合将TVS结构与GaN半导体器件电耦合。
根据第三方面的方法,其中GaN半导体器件包括高电子迁移率晶体管(HEMT)、结栅场效应晶体管(JFET)、金属氧化物场效应及晶体管(MOSFET)、二极管或其组合。
附图说明
当参考附图阅读以下具体描述时本发明的这些和其他特征、方面和优势将更好理解,贯穿附图相同符号表示相同部件,其中:
图1是根据本发明某些实施例的半导体组件的横截面图。
图2是根据本发明某些实施例的半导体组件的横截面图。
图3是根据本发明某些实施例的半导体组件的横截面图。
图4是根据本发明某些实施例的半导体组件的横截面图。
图5是根据本发明某些实施例的半导体组件的横截面图。
图6是根据本发明某些实施例的半导体组件的横截面图。
图7是根据本发明某些实施例的半导体组件的横截面图。
图8是根据本发明某些实施例的半导体组件的横截面图。
具体实施方式
如下文具体讨论的,本发明的某些实施例包括具有GaN半导体器件和TVS结构的单片集成半导体组件。
如本文中贯穿说明书和权利要求使用的近似的语言用于修正允许变化而不会导致与其相关的基本函数变化的任何定量表达。因此,由一项或多项修正的值诸如“约”和“实质上”不限于所指定的精确值。在一些情况下,近似的语言可对应于用于测量该值的手段精确度。此处和贯穿说明书和权利要求,可组合和/或互换范围限制,确定这种范围并且该范围包括其中含有的所有子范围,除非上下文或者语言另外指出。
在下述说明书和权利要求书中,单数形式“一个”和“这个”包括复数的指示物,除非上下文清楚地另外指出。如本文所使用的,术语“或者”并不意味着排他并且指的是存在所涉及部件(例如区域)中的至少一个且包括其中存在所涉及部件的组合的情况,除非上下文另外清楚指出。
如本文所使用的,术语“层”指的是以连续或者不连续方式设置在下层表面的至少一部分上的材料。而且,术语“层”不必意味着所设置材料厚度均匀,和所设置材料可具有均匀或者变化的厚度。而且,如本文所使用的术语“一层”指的是单层或多层,除非上下文另外清楚指出。
如本文所使用的,术语“设置在……上”指的是层彼此直接接触或者通过其间存在的中间层间接接触,除非另外明确指出。如本文所使用的术语“相邻”意思是两层连续设置且彼此直接接触。
在本公开中,当一层/器件被描述为在另一层或衬底“上”,则应当理解,多个层/器件可直接彼此接触或者在该多个层和器件之间具有一个(或多个)层或特征。而且,由于在上或在下的相对位置取决于器件对观测者的方位,因此术语“上”描述了层/器件彼此的相对位置而不必意味着“在顶部上”。而且,为了便利使用“顶部”、“底部”、“上方”、“下方”和这些术语的变形,且不需要部件的任何特定取向,除非另外说明。
如稍后具体描述的,提出了单片集成的半导体组件。本文所使用的术语“单片集成”指的是所有部件被制造/制备成单个衬底或者在单个衬底顶部上的半导体组件。图1和2示意性示出了根据本发明一些实施例的单片集成半导体组件100。如图1和2中所示,半导体组件100包括衬底110和制造在衬底110上的氮化镓(GaN)半导体器件120。半导体组件还包括至少一个瞬态电压抑制器(TVS)结构130。TVS结构可制造在衬底中,如图1中所示,或者,备选地,该TVS结构可制造在衬底上,如图2中所示。该TVS结构130与GaN半导体器件120电接触140,如图1和2中所示。
为了简要,本文可交换使用术语“氮化镓半导体器件”和“GaN器件”。而且,本文可交换使用术语“瞬态电压抑制器结构”和“TVS结构”。
对于特定结构,衬底包括SiC。如之前所述,本发明的实施例提供了实质上高温下的瞬态电压保护GaN器件,如大于约150摄氏度的温度下,和更特别地,在大于约200摄氏度的温度下。不受任何理论的限制,相信SiC衬底允许GaN器件的高温操作(大于150摄氏度)。
半导体组件可包括基于组件最终用途应用的任意合适的GaN器件120。对于特定结构,GaN器件120包括GaN晶体管、GaN二极管或者其组合。GaN晶体管的合适的非限制性实例包括场效应晶体管(FET)诸如高电子迁移率晶体管(HEMT)、结栅场效应晶体管(JFET)、金属氧化物半导体场效应晶体管(MOSFET)、或者其组合。一个或多个GaN器件120可以横向结构或者垂直结构制造在衬底110上。对于特定结构,GaN器件120是HEMT。
现在参考图3,示出了示范性GaN HEMT器件120的示意图。如图3中所示的示范性HEMT器件120包括设置在SiC衬底110上的缓冲层121(任选的)。对于特定结构,可将一个或多个中间层(未示出)设置在缓冲层121和SiC衬底之间。对于图3中所示的结构,GaN层122设置在缓冲层121上,以及氮化铝镓(AlGaN)层设置在GaN层122上。对于所示出的配置,HEMT器件120还包括栅极端子125、源极端子126和漏极127端子,如图3中所示。对于特定结构,GaN层122和AlGaN层123是本征型(i型)和其他p型AlGaN层(未示出)可设置在AlGaN层123和栅极端子126之间。覆盖层124(任选的)可进一步插入到源极端子125/漏极端子127和阻挡层123之间。
可通过顺序设置或者形成一个或多个前述层将GaN HEMT器件制造在SiC衬底110上。如本文所使用的术语“被制造在……上”或者“制造在……上”意味着可将GaN器件120/TVS结构130制造成与至少一部分衬底110直接接触,或者,备选地,一个或多个层/特征插入到GaN器件120/TVS结构130和衬底110之间。对于特定结构,可将GaN器件120制造在被进一步设置在至少—部分衬底110上的一个或多个中间层或特征上。例如,在一些实施例中,可将GaN器件120制造在设置在衬底上的至少一部分TVS结构130上,如图8中所示(下文将具体描述)。
如前所述,也称作浪涌保护器的瞬态电压抑制器(TVS)结构是用于保护敏感电子器件不受损伤诸如尖峰电压影响的电子部件。瞬态或过电压(或电流)是电压(或电流)的瞬态或短暂浪涌,这会损伤敏感电子电路。以下,术语“电压浪涌”和“瞬态电压”可交换使用以表示与跨该系统的平均电压相比不希望的或者过大的电压增加。相似地,术语“电流浪涌”和“瞬态电流”可交换使用以表示与通过该系统传输的平均电流相比不希望的电流增加。以下,术语“瞬态的”可用于一般性提及的瞬态电压或瞬态电流。
通常,瞬态电压抑制器件依据两个原理操作:削弱过大电流或瞬态电流从而限制剩余电流,或者自敏感电子部件转移瞬态或过大电流。削弱瞬态电流通常通过确保瞬态电流不会到达或影响敏感电子部件来实现,通常通过使用与电子部件串联插入的滤波器来实现。转移瞬态电流通常通过使用电压箝位装置就或者短路型器件来实现。操作中,电压箝位装置具有可变阻抗,其响应于流过电压箝位装置的电流而变化。
对于特定结构,TVS结构130可以是箝位装置。特别是,TVS结构130可被配置成当跨GaN器件120施加的电压大于阈值电压时,在击穿模式、雪崩模式或者其组合模式下操作。
如本文所使用的术语“击穿模式”意思是TVS结构使用“击穿”或者也公知为“穿通”物理过程进行操作,这样,当跨TVS结构的电压增加时,耗尽区跨该结构延伸,且大量电流能够流过TVS结构。该TVS结构进一步能够保持该条件,跨其的电压变化最小。
如本文所使用的术语“雪崩模式”指的是其中半导体保持器件一个区域或多个区域内部的电场,从而开始发生离子化过程,导致载流子倍增的过程。如果需要这样的话,TVS结构可保持该条件,但是,在器件开启电压之上,这通常包括电流的非线性增加,且在这些条件下,会注意到器件中电流和因此热量的极大增加。如本文所使用的术语阈值电压指的是TVS器件将有效开启或者开始传导电流的电压。
TVS结构130可包括碳化硅、氮化镓、氮化镓、金刚石、氮化铝、氮化硼、氧化锌、氧化镓或其组合物。对于特定结构,这里将TVS结构130制造在SiC衬底中,该TVS结构可包括与衬底(SiC)相同的材料,如图3-6中所示。在一些这种情况下,可由再生长外延将GaN器件120制造在SiC衬底110上。
对于其他结构,可将TVS结构制造在衬底上,如图7和8中所示。在一些这种配置中,TVS结构130可包括碳化硅、氮化镓或其组合物。在这种情况下,TVS结构可由再生长外延与衬底(即SiC,图8)相同的材料或者再生长外延GaN(图7)来制造。
TVS结构130可横向或者替换地垂直配置在半导体组件100中。图3-7示出了其中横向配置TVS结构130的示范性结构。图8示出了其中垂直配置TVS结构130的示范性结构。
再次参考图3-8,示范性的TVS结构130包括具有第一导电类型的第一半导体区131,和具有第二导电类型且与第一半导体区电接触的第二半导体区132。TVS结构130还包括具有第一导电类型且与第二半导体区电接触的第三半导体区133。
对于特定结构,第一导电型是p型和第二导电型是n型。这种情况下,TVS结构包括p-n-p器件。对于其他配置,第一导电型是n型和第二导电型是n型。这种情况下,TVS结构包含n-p-n器件。
这里应当明白,半导体材料的导电型是表示半导体材料中的多数和少数电荷载流子。例如,n型半导体材料包括“负电荷载流子”作为多数电荷载流子和“正电荷载流子”作为少数电荷载流子。例如,p型半导体材料包括“负电荷载流子”作为少数电荷载流子和“正电荷载流子”作为多数电荷载流子。如本领域技术人员所理解的,“负电荷载流子”指的是电子而“正电荷载流子”指的是空穴。
对于特定结构,第一导电类型是n+型和第二导电类型是p型。在n-p-n型器件中,当跨两个n型层对该器件施加电势时,由于其掺杂与两个n型层相比低很多,因此在p型层中形成耗尽层(大部分)。例如,低一个至五个数量级,或者n型层掺杂剂浓度的十分之一至万分之一。对于进一步的实例,如果n型层中的掺杂浓度为约1018/cm3,则p型层中的掺杂浓度可为约1015/cm3。
随着跨器件的电压增加,耗尽区跨过p型层整个延伸并接触另一侧上的n型层。这引起前文讨论的公知为“击穿”的模式,和大量电流开始在器件中流动。该器件能保持该条件,跨其的电压变化最小。相似的解释描述了当该层极性变为p-n-p时的操作模式。雪崩结构与图3-8中示出的击穿结构相似。通过调整第二半导体区132的厚度和掺杂,可使得TVS结构130在雪崩模式而非击穿模式下工作。
如前所述,TVS结构130与GaN器件120电接触140。对于特定结构,TVS结构130经由栅-源端子、漏-源端子、栅-漏端子或者其组合与GaN器件120电接触。图4示出了其中第一半导体区131与GaN器件130的源极端子126电接触140、和第三半导体区133与GaN器件120的栅极端子125电接触的配置。图5示出了其中第一半导体区131与GaN器件130的源极端子126电接触140、和第三半导体区133与GaN器件120的漏极端子127电接触的替换配置。
而且,在一些结构中,半导体组件可包括多个TVS结构130。图6示出了包括两个TVS结构130的配置。这种情况下,两个TVS结构可电连接到GaN器件120的相同端子或者不同端子。图6示出了其中第一TVS结构130电连接到GaN器件120的源极端子126和栅极端子125的构造。第二TVS结构电连接到源极端子126和漏极端子127。对于特定结构,GaN器件120可被一系列环包围,包括TVS结构130,以容纳更大的电流。
对于特定结构,第一半导体区131、第二半导体区132和第三半导体区133形成在SiC衬底110中,如图4-6中所示。这种情况下,TVS结构130包括SiC。这种情况下,可使用任意合适的技术将第一半导体区131、第二半导体区132和第三半导体区133形成在SiC衬底110中,例如离子注入n型掺杂剂或者p型掺杂剂。p型掺杂剂的合适的非限制性实例包括硼、铝、镓、镁、碳、钙或其组合物。n型掺杂剂的合适的非限制性实例包括氮、磷、砷、锑、或其组合物。
图7示出了其中TVS结构130被制造在SiC衬底110上的配置。在该示范性实施例中,TVS结构130包括GaN。图7中,TVS结构130还包括设置在至少一部分SiC衬底110上的GaN层134。第一半导体区131、第二半导体区132和第三半导体区133形成在GaN层134中,如图7中所示。这种情况下,可使用任意合适的技术例如离子注入n型掺杂剂或p型掺杂剂将第一半导体区1 3 1、第二半导体区132和第三半导体区133形成在GaN层134中。
对于其他结构,第一半导体区131、第二半导体区132和第三半导体区133外延生长在SiC衬底110上,如图8中所示,其示出了TVS结构130的垂直构造。在示范性配置中,半导体组件100包括台结构,其包括SiC衬底(例如具有n+型导电性)。半导体组件100还包括外延生长的第一半导体区131(例如具有n+型导电性),与第一半导体区131电接触的外延生长的第二半导体区132(例如具有p型导电性),和与第二半导体区132电接触的外延生长的第三半导体区133(例如具有n+型导电性)。
在示范性配置中,与第一半导体区131和第三半导体区133相比,第二半导体区132相对轻掺杂。对于特定构造,衬底110和区域131、132和133的均匀掺杂浓度提高了耗尽区中电场分布的均匀性,从而提高了击穿电压特性。
而且,对于特定构造,如图8中所示,TVS结构可具有倾斜侧壁。倾斜侧壁可关于相邻接触层之间的界面成约5度至约80度的角度,以降低组件表面处的最大电场分布。
对于特定构造,半导体组件100可被配置成在大于约150摄氏度的温度、更特别地在大于约200摄氏度的温度、和再特别地在大于约250摄氏度的温度下操作。而且,半导体组件100可被配置成在90%击穿电压下具有低于约1μA/cm2的泄漏电流,和更特别地在90%击穿电压下具有低于约0.5μA/cm2的泄漏电流。
半导体组件100可进一步被配置成具有大于约150A/cm2的操作电流密度,和更特别地大于约200A/cm2。在一些实施例中,半导体组件100被配置成显示出约5伏特至约75伏特之间的击穿特性,和更特别地,从约75伏特至约200伏特。在一些实施例中,TVS结构130可与SiC或GaN集成电路一起使用。
也提出了制造单片集成半导体组件的方法。再参考图1和2,该方法包括步骤(c)提供包括碳化硅(SiC)的衬底110;(b)在衬底110上制备氮化镓(GaN)半导体器件120;(c)在衬底110中或上制备至少一个瞬态电压抑制器(TVS)130;和(d)将TVS结构130和GaN半导体器件120电耦合。如前所述,TVS结构130被配置成当跨GaN半导体器件120施加的电压大于阈值电压时,在击穿模式、雪崩模式或其组合模式下操作。应当注意,在一些实施例中,在步骤(c)之前步骤(b)可受到影响,或者替换地,在一些其他实施例中,在步骤(b)之前可执行步骤(c)。
可通过外延生长GaN器件120的一层或多层,将GaN器件120制造在SiC衬底110上。例如,再次参考图3,在一些实施例中,可通过顺序设置或者形成层121、122和123中的一个或多个,和形成源极、栅极和漏极端子125、126和127,来制造GaN器件120。
对于特定构造,该方法还包括通过形成第一导电类型的第一半导体区131来制造TVS结构130,如图4-8所示。该方法还包括形成第二导电类型且与第一半导体区131电接触的第二半导体区133;和形成第一导电类型且与第二半导体区132电接触的第三半导体区133,如图4-8中所示。
对于特定构造,第一导电性是p型和第二导电性是n型。在这种情况下,TVS结构包括p-n-p器件。在一些其他实施例中,第一导电性是n型和第二导电性是n型。在这种情况下,TVS结构包括n-p-n器件。对于特定构造,第一导电类型是n+型和第二导电类型是p型。
通过连续参考图4-6,对于特定工艺,形成TVS结构的步骤可包括在SiC衬底130中形成第一半导体区131、第二半导体区132和第三半导体区133。在这种情况下,可使用任意合适的技术形成TVS结构130,诸如离子注入。
图7示出了另—特定工艺,其中形成TVS结构130的步骤包括将GaN层134设置在SiC衬底110的至少一部分上。该方法还包括在GaN层134中形成第一半导体区131、第二半导体区132和第三半导体区133,以形成TVS结构130,如图7中所示。在这种情况下,可使用任意合适的技术形成TVS结构130,诸如离子注入。
对于其他特定工艺,如图8中所示,形成TVS结构130的步骤可包括在SiC衬底110上外延生长第一半导体区131、第二半导体区132和第三半导体区133。如图8中所示,在这种工艺中,在SiC衬底110上制造TVS步骤之后,将GaN器件120制造在TVS结构130上。
该方法还包括经由栅-源端子、漏-源端子、栅-漏端子或者其组合,电耦合140TVS结构130和GaN半导体器件120,如图4-7中所示。
上述半导体组件提供了成本有效且可靠的手段,用于过压保护GaN器件以排除雪崩条件。更具体地,本文所述的半导体组件提供在高温操作期间(大于150摄氏度)GaN器件。
所附权利要求意在尽可能宽地要求本发明,如其被构思的那样,且本文描述的实例说明原自所有可能实施例的多种方式的所选实施例。因此,申请人的意图在于所附权利要求不受用于说明本发明特征的实例选择的限制。如权利要求中所使用的,词语“包括”和其语法上的变形在逻辑上也包括在内,且包括变化和不同范围内的短语表达,例如但是不限于,“实质上由……构成”和“由……构成”。只要必要,就提供范围;这些范围包括其间的所有子范围。希望这些范围内的变化为他们自己提出具有本领域常识且还未贡献到公众中的实践者,只要可以,就认为这些变化被所附权利要求涵盖。还可预期,科学和技术的进步会得到由于语言不严密的原因导致现在未设想到的可能等价物和替换物,并且也认为只要可能,这些变形被所附权利要求涵盖。
Claims (21)
1.一种单片集成的半导体组件,包括:
包括碳化硅SiC的衬底;
制造在所述衬底上的氮化镓GaN半导体器件;和
制造在所述衬底中或所述衬底上的至少一个瞬态电压抑制器TVS结构,
其中所述TVS结构与所述GaN半导体器件电接触,并且其中所述TVS结构被配置成当跨
所述GaN半导体器件施加的电压大于阈值电压时,在击穿模式下操作;
其中所述TVS结构包括:
具有第一导电类型的第一半导体区;
具有第二导电类型且与所述第一半导体区电接触的第二半导体区;和
具有第一导电类型且与所述第二半导体区电接触的第三半导体区。
2.如权利要求1所述的半导体组件,其中所述TVS结构包括碳化硅、氮化镓、金刚石、氮化铝、氮化硼或其组合中的至少一种。
3.如权利要求1所述的半导体组件,其中所述TVS结构横向配置。
4.如权利要求1所述的半导体组件,其中所述TVS结构垂直配置。
5.如权利要求1所述的半导体组件,其中所述第一导电类型是n+型以及所述第二导电类型是p型。
6.如权利要求1所述的半导体组件,其中所述第一半导体区、所述第二半导体区和所述第三半导体区形成在所述SiC衬底中。
7.如权利要求1所述的半导体组件,其中所述第一半导体区、所述第二半导体区和所述第三半导体区外延生长在所述SiC衬底上。
8.如权利要求1所述的半导体组件,其中所述TVS结构还包括设置在所述SiC衬底的至少一部分上的GaN层,以及其中所述第一半导体区、所述第二半导体区和所述第三半导体区形成在所述GaN层中。
9.如权利要求1所述的半导体组件,其中所述TVS结构经由栅-源端子、漏-源端子、栅-漏端子或其组合与所述GaN半导体器件电接触。
10.如权利要求1所述的半导体组件,其中所述GaN半导体器件包括高电子迁移率晶体管HEMT、结栅场效应晶体管JFET、金属氧化物半导体场效应晶体管MOSFET、二极管或其组合。
11.一种单片集成半导体组件,包括:
包括碳化硅SiC的衬底;
制造在所述衬底上的氮化镓GaN半导体器件;和
包括碳化硅SiC的至少一个瞬态电压抑制器TVS结构,所述至少一个瞬态电压抑制器TVS制造在所述衬底中或所述衬底上,
其中所述TVS结构与所述GaN半导体器件电接触,并且其中所述TVS结构被配置成当跨
所述GaN半导体器件施加的电压大于阈值电压时,在击穿模式下操作;
其中所述TVS结构包括:
具有第一导电类型的第一半导体区;
具有第二导电类型且与所述第一半导体区电接触的第二半导体区;和
具有第一导电类型且与所述第二半导体区电接触的第三半导体区。
12.如权利要求11所述的单片集成半导体组件,其中所述组件被配置成在大于150摄氏度的温度下操作。
13.如权利要求11所述的单片集成半导体组件,其中所述组件被配置成在90%击穿电压下具有低于约1μA/cm2的泄漏电流。
14.如权利要求11所述的单片集成半导体组件,其中所述组件被配置成具有大于约150A/cm2的操作电流密度。
15.一种制造单片集成半导体组件的方法,包括:
(a)提供包括碳化硅SiC的衬底;
(b)在所述衬底上制造氮化镓GaN半导体器件;
(c)在所述衬底中或所述衬底中上制造至少一个瞬态电压抑制器TVS;和
(d)将所述TVS结构与所述GaN半导体器件电耦合,
其中,所述TVS结构被配置成当跨所述GaN半导体器件施加的电压大于阔值电压时,在击穿模式下操作;
其中所述步骤(c)包括:
形成第一导电类型的第一半导体区;
形成第二导电类型且与所述第一半导体区电接触的第二半导体区;和
形成第一导电类型且与所述第二半导体区电接触的第三半导体区。
16.如权利要求15所述的方法,其中所述第一导电类型是n+型和所述第二导电类型是p型。
17.如权利要求15所述的方法,其中所述步骤(c)包括通过离子注入在所述SiC衬底中形成所述第一半导体区、所述第二半导体区和所述第三半导体区。
18.如权利要求15所述的方法,其中所述步骤(c)包括在所述SiC衬底上外延生长所述第一半导体区、所述第二半导体区和所述第三半导体区。
19.如权利要求15所述的方法,还包括在所述SiC衬底的至少一部分上设置GaN层,和在所述GaN层内形成所述第一半导体区、所述第二半导体区和所述第三半导体区。
20.如权利要求15所述的方法,其中所述步骤(d)包括经由栅-源端子、漏-源端子、栅-漏端子或其组合将所述TVS结构与GaN半导体器件电耦合。
21.如权利要求15所述的方法,其中所述GaN半导体器件包括高电子迁移率晶体管HEMT、结栅场效应晶体管JFET、金属氧化物场效应及晶体管MOSFET、二极管或其组合。
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- 2014-06-27 EP EP14174706.3A patent/EP2819156B1/en not_active Not-in-force
- 2014-06-27 KR KR1020140079461A patent/KR101654975B1/ko active IP Right Grant
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EP2819156A3 (en) | 2015-05-20 |
TW201517238A (zh) | 2015-05-01 |
JP2015012297A (ja) | 2015-01-19 |
TWI540700B (zh) | 2016-07-01 |
US9111750B2 (en) | 2015-08-18 |
JP5868457B2 (ja) | 2016-02-24 |
EP2819156B1 (en) | 2019-05-22 |
CN104282683A (zh) | 2015-01-14 |
KR101654975B1 (ko) | 2016-09-06 |
EP2819156A2 (en) | 2014-12-31 |
KR20150002520A (ko) | 2015-01-07 |
US20150001551A1 (en) | 2015-01-01 |
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