CN103972189B - 半导体器件、其制造方法及半导体器件封装 - Google Patents

半导体器件、其制造方法及半导体器件封装 Download PDF

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Publication number
CN103972189B
CN103972189B CN201310583359.1A CN201310583359A CN103972189B CN 103972189 B CN103972189 B CN 103972189B CN 201310583359 A CN201310583359 A CN 201310583359A CN 103972189 B CN103972189 B CN 103972189B
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convex block
substrate
semiconductor devices
insulation material
material layer
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CN103972189A (zh
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陈依婷
施应庆
蔡柏豪
卢思维
林俊成
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了半导体器件、其制造方法以及半导体器件封装。在一个实施例中，半导体器件包括在衬底的表面上具有开口的绝缘材料层。一个或多个插入凸块设置在绝缘材料层上方。半导体器件包括具有不设置在绝缘材料层上方的部分的信号凸块。

Description

半导体器件、其制造方法及半导体器件封装
相关申请的交叉参考
本申请涉及以下于2011年07月28日提交，标题为“Self-aligning ConductiveBump Structure and Method of Making the Same”的序列号为13/192,756的共同未决和共同转让的美国专利申请，其全部内容结合于此作为参考。
技术领域
本发明一般地涉及半导体技术领域，更具体地来说，涉及半导体器件，其制造方法及其封装。
背景技术
例如，半导体器件用于多种电子应用中，诸如，个人计算机、移动电话、数码相机和其他电子设备。通常通过在半导体衬底上方顺序地沉积绝缘层或介电层、导电层、以及半导体材料层，并且使用光刻图案化多个材料层以在其上形成电路组件和元件来制造半导体器件。通常在单个半导体晶圆上制造数十或数百个集成电路。通过沿着划线切割集成电路来分割(singulate)独立管芯。然后，单独封装独立管芯或将独立管芯与其他独立管芯封装在一起。
半导体工业通过最小特征尺寸的连续减小来继续改进多种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，从而允许更多部件集成在给定区域中。在一些应用中，这些较小电子部件还要求利用比过去的封装件更小面积的更小封装件。
用于已被开发的半导体器件的一种类型的较小封装是晶圆级封装(WLP)。倒装芯片接合利用导电凸块在集成电路管芯的接触焊盘和封装衬底之间建立电接触。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种半导体器件，包括：衬底；绝缘材料层，在所述衬底的表面上具有开口；一个或多个插入凸块，设置在所述绝缘材料层上方；以及多个信号凸块，具有不设置在所述绝缘材料层上方的部分。
在该半导体器件中，所述多个信号凸块包括：不设置在所述绝缘材料层上方的第一部分和设置在所述绝缘材料层上方的第二部分。
在该半导体器件中，所述多个信号凸块中的每个信号凸块都在所述衬底的所述表面上设置在接触焊盘上方。
在该半导体器件中，从上往下看时，所述一个或多个插入凸块包括：形成多边形的顶点的三个或更多个插入凸块。
在该半导体器件中，所述一个或多个插入凸块之一是插头。
在该半导体器件中，所述一个或多个插入凸块之一具有空心的插座形状。
在该半导体器件中，所述一个或多个插入凸块具有楔形侧壁。
在该半导体器件中，所述一个或多个插入凸块具有基本竖直的侧壁。
在该半导体器件中，从上往下看时，具有所述空心的所述插座形状的所述一个或多个插入凸块包括圆形或正方形。
根据本发明的另一方面，提供了一种制造半导体器件的方法，所述方法包括：在衬底上方形成绝缘材料层；去除所述绝缘材料层的一部分，以暴露所述衬底的信号凸块区域；在所述绝缘材料层上方形成一个或多个插入凸块；以及在所述衬底的所述信号凸块区域中形成多个信号凸块。
该方法进一步包括：在所述衬底的所述信号凸块区域上方以及所述绝缘材料层上方沉积晶种层；在所述绝缘材料层上方图案化部分所述晶种层上方的掩蔽材料；去除图案化的掩蔽材料；以及去除部分所述晶种层，其中，形成所述一个或多个插入凸块和形成所述多个信号凸块包括：在所述掩蔽材料图案之间的所述晶种层上镀导电材料。
在该方法中，所述绝缘材料层包括：氮化硅、聚酰亚胺或聚苯并恶唑(PBO)。
在该方法中，所述绝缘材料层是厚度为约5μm至约10μm的材料层。
在该方法中，形成所述一个或多个插入凸块和形成所述多个信号凸块包括：使用镀工艺同时形成所述一个或多个插入凸块和所述多个信号凸块。
该方法进一步包括：在形成所述插入凸块之前，从所述衬底接近所述一个或多个插入凸块的区域中去除所述绝缘材料；在所述绝缘材料层、所述信号凸块区域以及所述衬底上方形成晶种层；在所述晶种层上方形成掩蔽材料；去除所述掩蔽材料位于所述信号凸块区域和所述绝缘材料层上方的部分；使用镀工艺形成所述多个信号凸块和所述一个或多个插入凸块；去除所述掩蔽材料；以及去除所述晶种层的暴露部分。
该方法进一步包括：在所述绝缘材料层、所述信号凸块区域的暴露部分以及所述衬底上方形成晶种层；图案化所述晶种层上方的掩蔽材料；镀所述一个或多个插入凸块和所述多个信号凸块；去除所述掩蔽材料；以及去除所述晶种层的暴露部分，其中，去除部分所述绝缘材料层还暴露所述衬底接近所述一个或多个插入凸块的区域，并且所述多个信号凸块包括由所述绝缘材料层在周围包围的第一部分和位于所述第一部分和周围的所述绝缘材料层上方的第二部分。
根据本发明的又一方面，提供了一种半导体器件封装，包括：第一半导体器件，包括：衬底；绝缘材料层，在所述衬底的表面上具有开口；一个或多个第一插入凸块，设置在所述绝缘材料层上方；以及多个信号凸块，具有不设置在所述绝缘材料层上方的部分；以及第二半导体器件，连接至所述第一半导体器件的所述多个信号凸块，所述第二半导体器件包括一个或多个第二插入凸块，其中，所述一个或多个第二插入凸块与所述一个或多个第一插入凸块机械地对准。
该半导体器件封装进一步包括：多个第三半导体器件，设置在所述第一半导体器件和所述第二半导体器件之间，所述多个第三半导体器件中的每个都包括设置在第一侧面上的一个或多个第三插入凸块和设置在第二侧面上的一个或多个第四插入凸块，所述第二侧面与所述第一侧面相反，其中，所述第一半导体器件、所述第二半导体器件以及所述多个第三半导体器件中的相邻半导体器件通过所述第一插入凸块、所述第二插入凸块以及所述第三插入凸块或所述第四插入凸块机械地对准。
在该半导体器件封装中，所述衬底包括第一衬底，所述绝缘材料层包括第一绝缘材料层，并且所述第二半导体器件包括第二衬底以及设置在所述第二衬底和所述第二插入凸块之间的第二绝缘材料层。
在该半导体器件封装中，所述第一半导体器件和所述第二半导体器件包括集成电路管芯、封装器件或封装衬底。
附图说明
为了更完整地理解本发明及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1是根据本发明的一些实施例包括信号凸块和插入凸块的半导体器件的截面图；
图2a和图2b是根据一些实施例的图1所示的插入凸块的俯视图；
图3是根据本发明的其他实施例包括信号凸块和插入凸块的半导体器件的截面图；
图4a和图4b是根据一些实施例的图3所示的插入凸块的俯视图；
图5a和图5b是根据一些实施例的图3所示的插入凸块的一部分的透视图；
图6至图13是示出根据一些实施例制造半导体器件的方法的截面图；
图14和图15是包括根据图6至图13所示的方法所制造的半导体器件的半导体器件封装的截面图；
图16至图21是示出根据一些实施例制造半导体器件的方法的截面图；
图22和图23是包括根据图16至图21所示的方法所制造的半导体器件的半导体器件封装的截面图；
图24至图29是示出根据一些实施例制造半导体器件的方法的截面图；
图30和图31是包括根据图24至图29所示的方法所制造的半导体器件的半导体器件封装的截面图；
图32和图33示出根据其他实施例的半导体器件的截面图；
图34是包括图32和图33所示的半导体器件的半导体器件封装的截面图；
图35至图38是示出根据一些实施例的封装半导体器件的方法的截面图；以及
图39是根据一些实施例的制造半导体器件的方法的流程图。
除非另外指定，否则不同附图中的相应数字和符号通常是指相应的部件。绘制附图被以清楚地示出实施例的相关方面并且不必按比例绘制附图。
具体实施方式
以下详细地论述本发明的一些实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体实现的可应用的创造性概念。所论述的特定实施例仅示出制造和使用本发明的具体方式，并且没有限定本发明的范围。
本发明的一些实施例涉及半导体器件和半导体器件的封装。本文中将描述新半导体器件、其制造方法以及半导体器件封装。
图1是包括设置在衬底102的表面上方的多个导电凸块114/116的半导体器件100的截面图。作为实例，多个导电凸块114/116包括微凸块、可控坍塌芯片连接(C4)凸块、或其他类型的电接触件。根据本发明的一些实施例，多个导电凸块114/116包括多个信号凸块114和一个或多个插入凸块116。根据本发明的一些实施例，插入凸块116形成在具有开口的绝缘材料层106上方，该绝缘材料层设置在衬底102的表面上。信号凸块114至少具有不设置在绝缘材料106上方的部分。例如，在所示的实施例中，在绝缘材料层106上方没有形成信号凸块114。半导体器件100与另一个半导体器件100′封装在一起，以形成半导体器件封装120。半导体器件100和100′可以包括集成电路管芯、封装器件、封装衬底或其他类型的衬底。
在衬底102上信号凸块114形成在接触焊盘104上方。信号凸块114包括本文中要进一步进行描述的晶种层108、导电材料110以及保护层112。插入凸块116包括晶种层108、导电材料110、以及保护层112。图1中仅示出了一个信号凸块114和两个插入凸块116；然而，根据一些实施例，在衬底102的整个表面上形成多个信号凸块114，并且在衬底102的整个表面上形成一个或多个插入凸块116。信号凸块114可以被布置为阵列、随机布置、在衬底102的一个或多个边缘上的一行或多行或其他结构。一个或多个插入凸块116可以置于衬底102的一个或多个边缘处、衬底102的中心区域中或衬底102的其他区域中。在一些实施例中，作为另一个实例，一个或多个插入凸块116置于衬底102的三个或更多区域中。作为其他实例，一个或多个插入凸块116可以置于衬底102的中心区域周围，管芯边缘周围或衬底102或管芯的角部区域中。
半导体器件100′包括衬底102′，衬底102′包括形成在其上的信号凸块114′和插入凸块116′。半导体器件100′的插入凸块116′没有形成在绝缘材料层上；插入凸块116′直接形成在衬底102′上。在衬底102′上信号凸块114′形成在接触焊盘104′上，并且信号凸块114′包括晶种层108′、导电材料110′以及保护层112′。插入凸块116′包括晶种层108′、导电材料110′以及保护层112′。在一些实施例中，作为实例，可以使用于2011年07月28日提交的标题为“Self-aligning Conductive Bump Structure and Method of Making the Same”的序列号为13/192,756的美国专利申请(其全部内容结合于此作为参考)中所述的方法来制造半导体器件100′的至少一部分。可选地，可以使用其他方法形成半导体器件100′。
有利地，半导体器件100的插入凸块116和半导体器件100′的插入凸块116′在将两个半导体器件100和100′连接在一起以形成半导体器件封装120期间分别提供机械定位(mechanical registration)和对准。半导体器件100的绝缘材料层106产生插入凸块116和116′的重叠。在一些实施例中，信号凸块114的保护层112和信号凸块114′的保护层112′分别包括焊料或其他类型的共晶材料，对焊料或其他类型的共晶材料进行回流以将半导体器件100附接至半导体器件100′。有利地，插入凸块116和116′在焊料回流工艺期间保持信号凸块114和114′的正确对准。
在一些实施例中，在半导体器件100的信号凸块114和插入凸块116上包括保护层112，但是在半导体器件100′的信号凸块114′和插入凸块116′上不包括保护层112′。在其他实施例中，在半导体器件100′的信号凸块114′和插入凸块116′上包括保护层112′，但是在半导体器件100的信号凸块114和插入凸块116上不包括保护层112。作为另一个实例，根据一些实施例，半导体器件100和100′中的至少一个包括保护层112或112′。
根据本发明的一些实施例，分别来自相邻半导体器件100和100′的插入凸块116与116′之间的间隙在它们相配之后不大于信号凸块114和114′的宽度的约一半。例如，包括该尺寸的插入凸块116和116′之间的间隙确保信号凸块114和114′不会滑脱或者变得未对准，同时仍然提供用于一些未对准的一些机械偏差空间。可选地，插入凸块116和116′之间的间隙可以包括其他相对尺寸。
图2a和图2b分别是根据一些实施例的图1所示的半导体器件100和100′的插入凸块116和116′的俯视图。根据一些实施例，半导体器件100包括三个或更多插入凸块116。在一些实施例中，一个或多个插入凸块116包括在俯视图中形成多边形的顶点的3个或更多个插入凸块。在一些实施例中，一个或多个插入凸块116′是插头(plug)。
在图2a中，示出三个插入凸块116的布置。三个插入凸块116布置在中心区域周围，其中，中心区域设置在三个插入凸块116之间。如图2a所示，半导体器件100′的插入凸块116′包括插座形状，并且适用于装配在设置在半导体器件100的三个插入凸块116之间的中心区域中。可选地，接近半导体器件100′的插入凸块116′，可以包括四个或更多个插入凸块116。例如，图2b中示出了布置在中心区域周围的四个插入凸块116。
在一些实施例中，半导体器件100上的多个插入凸块116包括具有空心的插座形状，并且半导体器件100′上的插入凸块116′包括插头形状。作为实例，多个插入凸块116用作当半导体器件100和100′连接到一起时将插入凸块116′插入的插座。多个插入凸块116之间的中心区域包括插座形状的中空区域。
在图1、图2a和图2b所示的实施例中，单个插头形插入凸块116′被设置在半导体器件100′上，并且包括插座形状的多个插入凸块116被设置在半导体器件100上。可选地，单个插头形插入凸块116可以包括在半导体器件100上，并且包括插座形状的多个插入凸块116′可以包括在半导体器件100′上(参见图22)。根据一些实施例，例如，一个半导体器件100或100′包括用作插头的插入凸块116或116′，并且其他半导体器件100′或100包括用作插座的多个插入凸块116′或116。
图3是根据本发明的其他实施例的包括信号凸块114和插入凸块116的半导体器件100的截面图。用作插头并且包括插头形状的单个插入凸块116在半导体器件100的衬底102上设置在绝缘材料层106上方。半导体器件100′在衬底102′上方不包括绝缘材料层。插入凸块116′直接形成在衬底102′上方，并且插入凸块116′的宽度大于半导体器件100上的插入凸块116的宽度。作为实例，信号凸块114和插入凸块116的宽度可以为约5μm至约30μm，并且插入凸块116′的宽度可以为约5μm至约30μm。可选地，信号凸块114和插入凸块116和116′可以包括其他尺寸。插入凸块116′包括中空区域或空心118，包括插座形状，并且适用于接收半导体器件100上的插头功能插入凸块116。半导体器件100上的插入凸块116在半导体器件100′上装配在插入凸块116′的中空区域118内。在一些实施例中，插入凸块116′的中空区域118可以完全延伸到衬底102′。可选地，在其他实施例中，插入凸块116′的中空区域118可以延伸到衬底102′上方的预定点。
图4a和图4b是根据一些实施例的图3所示的插入凸块116和116′的俯视图。在俯视图中，插入凸块116′包括环形形状。在俯视图中，插入凸块116′可以是圆形(如图4a所示)或正方形(如图4b所示)。可选地，插入凸块116′可以是矩形的或者可以包括其他形状。
图5a和图5b是根据一些实施例的图3所示的半导体器件100′的插入凸块116′的一部分的透视图。如图5a所示，插入凸块116′的侧壁可以基本是直的，或者可选地，如图5b所示，插入凸块116′的侧壁可以是楔形的。例如，接近衬底102′的插入凸块116′的侧壁的宽度可以大于在插入凸块116′的顶面处的宽度。
接下来，将描述图1和图3所示的制造半导体器件100的方法。图6至图13是示出根据一些实施例的制造半导体器件100的方法的截面图。为了制造半导体器件100，首先，如图6所示，提供衬底102。例如，衬底102可以包括包含硅或其他半导体材料的半导体衬底，并且可以被绝缘层覆盖。衬底102可以包括包含有源部件或电路的集成电路管芯(未示出)。例如，衬底102可以包括单晶硅上硅氧化物。衬底102可以包括导电层或其他半导体元件，例如，晶体管、二极管、电容器、电阻器、电感器等。可以使用诸如GaAs、InP、Si/Ge或SiC的化合物半导体来代替硅。作为实例，衬底102可以包括绝缘体上硅(SOI)或绝缘体上锗(GOI)衬底。在一些实施例中，作为另一个实例，衬底102包括中介层衬底或封装衬底。
在附图中，仅示出了一个半导体器件100。然而，例如，多个半导体器件100形成在包括可以布置为行和列的多个衬底102的晶圆上。在制造半导体器件100之后，或者在将半导体器件100与另一个半导体器件100或100′封装在一起之前或之后，例如，使用锯或激光器沿着划线分割半导体器件100，以形成独立半导体器件100。
衬底102包括设置在其上的多个接触焊盘104(还在图6中示出)。接触焊盘104可以包括衬底102的上部金属化层或导电划线层。作为实例，接触焊盘104可以包括Al、Al合金、Cu、Cu合金、其他导电材料、或它们的组合或多层。可选地，接触焊盘104可以包括其他材料。在附图中仅示出了一个接触焊盘104；然而，作为实例，多个接触焊盘104设置在衬底102上方，并且在衬底102的一个或多个边缘或中心区域上可以布置为阵列、随机图案或者一行或多行。例如，在一些实施例中，接触焊盘104连接至下面的导线、通孔或形成在衬底102内的电路。在其他实施例中，一个或多个接触焊盘104可以使用在形成接触焊盘104的相同材料层中所形成的导线连接至其他接触焊盘104(未示出)。
衬底102包括形成多个信号凸块112(图6中未示出；参见图12和图13中的信号凸块114)的信号凸块区域124。根据一些实施例，衬底102还包括形成多个插入凸块116(在图6中也未示出；参见图12和图13中的插入凸块116)的插入凸块区域126。接触焊盘104设置在衬底102的信号凸块区域124中。
如图7所示，绝缘材料层106形成在接触焊盘104和衬底102上方。作为实例，绝缘材料层106包括氮化硅、聚酰亚胺或聚苯并恶唑(PBO)，但是绝缘材料层106可以可选地包括其他介电材料和绝缘材料。绝缘材料层106的厚度包括尺寸d1，其中，作为实例，尺寸d1包括约5μm至约10μm。可选地，绝缘材料层106的尺寸d1可以包括其他尺寸。作为实例，可以使用化学汽相沉积(CVD)、物理汽相沉积(PVD)、旋涂方法或溅射方法沉积绝缘材料层106。可选地，可以使用其他方法形成绝缘材料层106。如图6所示，绝缘材料层106在沉积时是基本共形的。可选地，绝缘材料层106可以符合衬底102和接触焊盘104的构形(未示出)。绝缘材料层106被用于升高插入凸块116(图7中未示出；参见图12)并且形成插入凸块116与另一个半导体器件的插入凸块的重叠。
接下来，从衬底102的信号凸块区域124的至少一部分去除绝缘材料层106。在图6至图12所示的实施例中，例如，从衬底102的信号凸块区域124完全去除绝缘材料层106。在其他实施例中，从衬底102的信号凸块区域124的一部分去除绝缘材料层106，以在本文中参考图24至图29进行进一步描述。
如图8所示，在一些实施例中，为了从衬底102的信号凸块区域124去除绝缘材料层106，掩蔽材料122可以形成在绝缘材料层106上方。在一些实施例中，掩蔽材料122包括光刻胶，但是可选地，可以使用其他材料。也如图8所示，使用光刻(例如，通过使掩蔽材料122暴露于传输穿过在其上具有期望图案的光刻掩模或从其反射的能量或光中，此后，对掩蔽材料进行显影)，从衬底102的信号凸块区域124去除掩蔽材料122，图案化掩蔽材料122。
如图9所示，使用蚀刻工艺蚀刻掉绝缘材料层106的暴露部分，并且去除掩蔽材料122。在信号凸块区域124中通过绝缘材料层106暴露接触焊盘104。衬底102的插入凸块区域126保持被绝缘材料层106覆盖。
在一些实施例中，如果绝缘材料层106包括感光材料，则在处理流程中不包括掩蔽材料122，并且直接对绝缘材料层106进行图案化。
接下来，如图10所示，在绝缘材料层106上方以及衬底102的信号凸块区域124中的接触焊盘104上方形成或沉积晶种层108。作为实例，晶种层108包括Cu、Cu合金、Ti或其组合或多层。在一些实施例中，作为另一个实例，晶种层108包括第一层Ti和设置在第一层Ti上方的第二层Cu。可选地，晶种层108可以包括其他材料。晶种层108的厚度为约100埃至约10,000埃，或者在一些实施例中，介于约100埃至约1000埃之间。在一些实施例中，溅射晶种层108。晶种层108可以使用其他方法形成并且可以包括其他尺寸。在一些实施例中，例如，晶种层108包括焊球底部金属化(UBM)层。
如图11所示，包括所述的用于掩蔽材料122的类似材料的掩蔽材料122′形成在晶种层108上方。使用如所述的用于掩蔽材料122的光刻来图案化掩蔽材料122′，以从信号凸块区域124和插入凸块区域126去除掩蔽材料122′的多个部分。例如，根据一些实施例中，通过用于信号凸块114和插入凸块116的期望形状来图案化掩蔽材料122′。
如图12所示，使用喷镀工艺在掩蔽材料122′内形成信号凸块114和插入凸块116。使用第一喷镀工艺以在图案化的掩蔽材料122′和绝缘材料层106内部的晶种层108上方形成导电材料110。在一些实施例中，导电材料110包括Cu或Cu合金，但是可选地，可以使用其他材料。在一些实施例中，使用第二喷镀工艺在掩蔽材料122′内的导电材料110上方形成保护层112。在其他实施例中，不包括保护层112。保护层112包括诸如焊料的共晶材料，但是可选地，可以使用其他材料。例如，在一些实施例中，使用一种喷镀工艺或多种喷镀工艺同时形成信号凸块114和插入凸块116。例如，在一些实施例中，形成插入凸块116和信号凸块114包括：在掩蔽材料112′图案之间的晶种层108上喷镀导电材料110或110/112。
然后，如图13所示，去除掩蔽材料122′。还去除晶种层108的多个部分，例如，晶种层108的暴露部分。如果包括保护层112，则信号凸块114和插入凸块116包括晶种层108、导电材料110以及保护层112。每个信号凸块114都连接至接触焊盘104并设置在接触焊盘104上方，该接触焊盘设置在衬底102的表面上。信号凸块114提供与衬底102的电连接。插入凸块116帮助半导体器件100与另一个半导体器件的对准。插入凸块116可以包括环绕另一个半导体器件上的插入凸块可以插入的中心区域所布置的多个插入凸块116。可选地，插入凸块116可以包括具有形成在其中的中空区域118的单个凸块，其中，另一个半导体器件上的插入凸块可以插入该中空区域118中。
在其他实施例中，在插入凸块区域126(在图6至图13中未示出；参见图3)中形成一个插头形插入凸块116。插头形插入凸块116适用于将半导体器件100与另一个半导体器件上的插座形插入凸块对准。例如，可以使用所述的用于图6至图13的方法形成单个插头形插入凸块116。
图14和图15是包括根据图6至图13所示的方法制造的半导体器件100的半导体器件封装120的截面图。如图14所示，倒置或“翻转”图13所示的半导体器件100，并且半导体器件100连接至另一个半导体器件100′。例如，在一些实施例中，倒装接合半导体器件100和100′。半导体器件100′包括连接至半导体器件100的信号凸块114的信号凸块114′。插头形插入凸块116′直接形成在半导体器件100′的衬底102′上方，而不是如半导体器件100所示，形成在设置在衬底102上方的绝缘材料层106上方。插头形插入凸块116′插入一个或多个插入凸块116的中空区域118中，使半导体器件100和100′共同对准。
包括形成在绝缘材料层106上方的新插入凸块116的一个半导体器件100可以连接至包括形成在本文中所述的绝缘材料层106上方的插入凸块116的另一个半导体器件100。图15示出以倒装接合方法连接的第一半导体器件100a和第二半导体器件100b。通过将信号凸块114a和114b的顶面升高为分别高于插入凸块116a和116b的顶面以提供插入凸块116a和116b的增加重叠量，绝缘材料层106a和106b提供用于半导体器件封装120的改进对准。
图16至图21是示出根据一些实施例制造半导体器件100的方法的截面图。在这些实施例中，信号凸块区域124和插入凸块区域126从衬底102上方去除绝缘材料层106的多个部分。例如，仅在将形成一个或多个插入凸块116的区域中保留绝缘材料层106。在图6和图7所示的制造步骤之后，如图16所示，在绝缘材料层106上方形成掩蔽材料122。还如图16所示，使用光刻图案化掩蔽材料122，并且如图17所示，使用掩蔽材料122作为蚀刻掩模，同时蚀刻掉或去除绝缘材料106的多个部分。从信号凸块区域124完全去除绝缘材料层106。例如，在插入凸块区域126中将形成一个插入凸块116或多个插入凸块116的多个部分中保留绝缘材料层106。例如，在这些实施例中，在形成一个插入凸块116或多个插入凸块116之前，从衬底102接近一个插入凸块116或多个插入凸块116的多个区域去除绝缘材料层106。然后，还如图17所示，去除掩蔽材料122。在其他实施例中，如果绝缘材料层106包括感光材料，则可以不要求掩蔽材料122。
如图18所示，晶种层108形成在绝缘材料层106上方、信号凸块区域124中的接触焊盘104上方、以及衬底102在信号凸块区域124和插入凸块区域126中的暴露部分上方。如图19所示，掩蔽材料122′形成在晶种层108上方，并且使用光刻图案化掩蔽材料122′，以在信号凸块区域124和插入凸块区域126中从晶种层108上方去除掩蔽材料122′的多个部分。在插入凸块区域126中从绝缘材料层106上方的晶种层108上方去除掩蔽材料122′。例如，根据一些实施例，通过用于信号凸块114和插入凸块116的期望形状来图案化掩蔽材料122′。
如图20所示，喷镀工艺用于在图案化的掩蔽材料122′内形成信号凸块114和插入凸块116。在信号凸块114和插入凸块116的导电材料110上方可以包括或可以不包括保护层112。然后，如图21所示，去除掩蔽材料122′和晶种层108的暴露部分。
如图6至图13所示的实施例所述，半导体器件100的插入凸块116可以包括环绕另一个半导体器件上的插入凸块可以插入的中心区域布置的多个插入凸块116。可选地，插入凸块116可以包括具有形成在其中的中空区域118的单个凸块，另一个半导体器件上的插入凸块可以插入该中空区域中。或者，可以在包括插头形状的半导体器件100上形成单个插入凸块116。插头形插入凸块116适用于将半导体器件100与另一个半导体器件上的插座形插入凸块对准。例如，如图22所示，也可以使用所述的图16至图21的方法在半导体器件100上形成单个插头形插入凸块116。
图22和图23是包括根据图16至图21所示的方法制造的半导体器件100的半导体器件封装120的截面图。半导体器件100可以连接至不包括形成在如图22所示的绝缘材料层上方的插入凸块的半导体器件100′。可选地，如图23所示，包括形成在绝缘材料层106a上方的插入凸块116a或插入凸块116a的半导体器件100a可以连接至包括形成在绝缘材料层106b上方的一个插入凸块116b或多个插入凸块116b的半导体器件100b。
图24至图29是示出根据其他实施例的制造半导体器件100的方法的截面图。在这些实施例中，如图16至图21所示的实施例所述，从信号凸块区域124的多个部分和插入凸块区域126的多个部分去除绝缘材料层106。然而，绝缘材料层106的一部分也保留在信号凸块区域124中。在这些实施例中，绝缘材料层106的多个部分围绕信号凸块114的导电材料110的下部，并且有利地，提供对信号凸块114的增强的结构支撑。例如，多个信号凸块114中的每个都包括不设置在绝缘材料层106上方的第一部分和设置在绝缘材料层106上方的第二部分。
在图6和图7所示的制造步骤之后，如图24所示，在绝缘材料层106上方形成掩蔽材料122。与在其他实施例中一样，如果绝缘材料层106包括感光材料，则可以不要求掩蔽材料122。还如图24所示，使用光刻图案化掩蔽材料122，并且如图25所示，掩蔽材料122用作蚀刻掩模，同时蚀刻掉或去除绝缘材料106的多个部分。从信号凸块区域124设置在接触焊盘104上方的第一部分去除绝缘材料层106。例如，在一些实施例中，从信号凸块区域124设置在接触焊盘104的中心区域上方的第一部分去除绝缘材料层106。可选地，作为另一个实例，在其他实施例中，可以从信号凸块区域124设置在边缘区域或从接触焊盘104的中心区域偏移的区域上方的第一部分去除绝缘材料层106。在信号凸块区域124的第二部分中保留绝缘材料层106。例如，在一些实施例中，如图25所示，在信号凸块区域124设置在接触焊盘104的一个边缘区域或多个边缘区域上方的第二部分中保留绝缘材料层106。例如，在一些实施例中，环绕接触焊盘104保留绝缘材料层106。插入凸块区域126内将形成一个插入凸块116或多个插入凸块116的区域中也保留绝缘材料层106。在这些实施例中，例如，在形成一个插入凸块116或多个插入凸块116之前，从衬底102接近一个插入凸块116或多个插入凸块116的区域中去除绝缘材料层106。例如，在去除绝缘材料层106的多个部分之后，暴露衬底102接近插入凸块116的多个区域。然后，还如图25所示，去除掩蔽材料122。
如图26所示，晶种层108形成在绝缘材料层106上方、信号凸块区域124(例如，信号凸块区域124中的接触焊盘108上方)的暴露部分上方以及衬底102在信号凸块区域124和插入凸块区域126中的暴露部分上方。如图27所示，掩蔽材料122′形成在晶种层108上方，并且使用光刻图案化掩蔽材料122′，以在信号凸块区域124和插入凸块区域126中从晶种层108上方去除掩蔽材料122′的多个部分。在信号凸块区域124的第一部分上方从绝缘材料层106上方的晶种层108上方去除掩蔽材料122′。还在插入凸块区域126中从绝缘材料层106上方的晶种层108上方去除掩蔽材料122′。例如，根据一些实施例，通过用于信号凸块114和插入凸块116的期望形状来图案化掩蔽材料122′。
然后，如图28所示，喷镀工艺用于在掩蔽材料122′内形成信号凸块114和插入凸块116。在信号凸块114和插入凸块116的导电材料110上方可以包括或可以不包括保护层112。然后，如图29所示，去除掩蔽材料122′和晶种层108的暴露部分。信号凸块114包括由绝缘材料层106在周围包围的第一部分(例如，图29中的下部)和设置在第一部分和周围绝缘材料层106上方的第二部分(例如，图29中的上部)。
如图6至图13和图16至图21所示的实施例所述，半导体器件100的插入凸块116可以包括环绕另一个半导体器件上的插入凸块可以插入的中心区域布置的多个插入凸块。可选地，插入凸块116可以包括具有形成在其中的中空区域118的单个凸块，另一个半导体器件上的插入凸块可以插入该中空区域中。或者，可以在包括插头形状的半导体器件100上形成单个插入凸块116。插头形插入凸块116适用于将半导体器件100与另一个半导体器件上的插座形插入凸块对准。例如，如图30所示，还可以使用所述的图24至图29的方法在半导体器件100上形成单个插头形插入凸块116。
图30和图31是包括根据图24至图29所示的方法制造的半导体器件100的半导体器件封装120的截面图。如图30所示，半导体器件100可以连接至不包括形成在绝缘材料层上方的插入凸块的半导体器件100′。可选地，如图31所示，包括形成在绝缘材料层106a上方的一个插入凸块116a或多个插入凸块116a的半导体器件100a可以连接至包括形成在绝缘材料层106b上方的一个插入凸块116b或多个插入凸块116b的半导体器件100b。
图32和图33示出根据其他实施例的半导体器件100的截面图。半导体器件100包括第一侧面132和与第一侧面132相反的第二侧面134。在图32中，包括所述的用于绝缘材料层106的类似材料的绝缘材料层136在信号凸块114和插入凸块116之间设置在半导体器件100的第一侧面132上的绝缘材料层106上方。在一些实施例中，不包括绝缘材料层136。在一些实施例中，多个焊球138连接至信号凸块114和插入凸块116的保护层112。在一些实施例中，插入凸块116设置在衬底102的边缘区域上，即，设置在衬底102的中心区域中的信号凸块114周围。
在图33中，半导体器件100包括形成在第一侧面132上的绝缘材料层136和形成在信号凸块114和插入凸块116上的焊球138。衬底102包括在其中形成的多个衬底通孔(TSV)140。TSV 140包括导电材料或半导体材料，并且提供用于半导体器件100的垂直电连接件。半导体器件100包括形成在其第二侧面134上的多个信号凸块144和多个插入凸块146。与本文中先前所述的半导体器件100′一样，信号凸块144和插入凸块146可以直接形成在衬底102上，或者可选地，与本文中所述的半导体器件100一样，信号凸块144可以直接形成在衬底102上，而插入凸块146可以形成在设置在衬底102上方的绝缘材料层(例如，诸如绝缘材料层106，未示出)上。
有利地，图33所示的半导体器件100可以使用用于电和机械连接的信号凸块114和用于对准和机械定位的插入凸块116，连接至第一侧面132上的另一个半导体器件100或100′。半导体器件100还可以使用用于电和机械连接的信号凸块144和用于对准和机械定位的插入凸块146，连接至第二侧面134中的另一个半导体器件100或100′。
在一些实施例中，第一侧面132上的插入凸块116包括插头形状，而第二侧面134上的插入凸块146包括插座形状，使得多个半导体器件100可以相互垂直地堆叠。可选地，第一侧面132上的插入凸块116包括插座形状，而第二侧134上的插入凸块146包括插头形状，使得多个半导体器件100可以相互垂直地堆叠。在其他实施例中，半导体器件100可以包括分别位于第一侧面132和第二侧面134上的插头形插入凸块116和146，或者半导体器件100可以包括分别位于第一侧面132和第二侧面134上的插座形插入凸块116和146(未示出)。
图34是包括以分层布置的方式堆叠的图32所示的半导体器件100和图33所示的多个半导体器件100的半导体器件封装160的截面图。例如，半导体器件100b、100c和100d均包括图33所示的半导体器件100，并且半导体器件100e包括图32所示的半导体器件100。参见图32和图33，在图34中没有标记出用于半导体器件100b、100c、100d和100e的每个元件。
半导体器件100a′包括形成在衬底102a上方的如图33所示的信号凸块144a和插入凸块146a。衬底102a包括在其中形成的多个TSV 140a。焊球158连接至衬底102a的底面，并且半导体器件100b的信号凸块114b连接至半导体器件100a′的信号凸块144a。半导体器件100b分别通过半导体器件100b的插入凸块116b和半导体器件100a′的插入凸块146a与半导体器件100a′对准。
在半导体器件100b和100a′上方以分层布置的方式类似地堆叠半导体器件100c、100d、和100e。半导体器件100c的信号凸块114c连接至半导体器件100b的信号凸块144b，并且半导体器件100c分别通过半导体器件100c的插入凸块116c和半导体器件100b的插入凸块146b与半导体器件100b对准。半导体器件100d的信号凸块114d连接至半导体器件100c的信号凸块144c，并且半导体器件100d分别通过半导体器件100d的插入凸块116d和半导体器件100c的插入凸块146c与半导体器件100c对准。半导体器件100e的信号凸块114e连接至半导体器件100d的信号凸块144d，并且半导体器件100e分别通过半导体器件100e的插入凸块116e和半导体器件100d的插入凸块146d与半导体器件100d对准。
例如，半导体器件100a′的衬底102a可以包括中介层衬底、封装衬底、或封装器件。半导体器件100b、100c、100d和100e的衬底102可以包括具有诸如存储器件、逻辑电路或其他功能的不同功能电路的集成电路管芯。可选地，半导体器件100b、100c、100d和100e的衬底102可以包括具有在其上设置的相同或类似功能电路的集成电路管芯。例如，在一些实施例中，半导体器件封装160包括芯片上系统(SOC)器件。可选地，半导体器件100a′、100b、100c、100d和100e的衬底102可以包括其他类型的衬底，并且半导体器件封装160可以包括其他类型的器件。
图35至图38是示出根据一些实施例将半导体器件100a′、100b、100c、100d和100e封装在一起以形成半导体器件封装160的方法的截面图。首先，提供衬底162。衬底162可以包括印刷电路板(PCB)和其他类型的衬底。参考图34所述的半导体器件100a′使用焊球158连接至衬底162。半导体器件100b、100c、100d和100e顺序地分别置于半导体器件100a、100b、100c和100d的顶部上。例如，在图36中，半导体器件100b置于半导体器件100a′上，并且在图37中，半导体器件100c置于半导体器件100b上。如图38所示，在以分层布置的形式顺序地堆叠所有半导体器件100a′、100b、100c、100d和100e之后，半导体器件封装160经过焊料回流工艺，从而对信号凸块114和144(参见图32和图33)上的焊料或共晶材料进行回流，以进行用于半导体器件封装160的电和机械连接。有利地，插入凸块116和146(参见图32和图33)在堆叠工艺期间提供半导体器件100a′、100b、100c、100d和100e中的每个之间的对准。插入凸块116和146还在焊料回流处理期间保持半导体器件100a′、100b、100c、100d和100e的对准位置，以防止管芯移动、短路或开路的形成，并且导致改进的成品率。
在一些实施例中，如图38所示，顶部和底部半导体器件100a′和100e包括分别仅设置在一个侧面上的插入凸块116a′和116e。其他半导体器件100b、100c、100d在两个侧面上分别包括插入凸块116b′和116b、116c′和116c以及116d′和116d。在一些实施例中，半导体器件100b、100c和100d包括设置在第一半导体器件100a′和第二半导体器件100e之间的多个第三半导体器件，多个第三半导体器件100b、100c和100d中的每个都包括设置在第一侧面上的一个或多个第三插入凸块116b′、116c′、以及116d′和设置在第二侧面上的一个或多个第四插入凸块116b、116c和116d，第二侧面与第一侧面相反。第一半导体器件100a′、第二半导体器件100e以及多个第三半导体器件100b、100c和100d中的相邻半导体器件通过第一插入凸块116a′、第二插入凸块116e、第三插入凸块和/或第四插入凸块116b′和116b、116c′和116c、116d′和116d机械地对准。
在其他实施例中，分别包括仅设置在一个侧面上的插入凸块116a′和116e的顶部半导体器件100a′和底部半导体器件100e可以连接在一起。例如，第一半导体器件100a′的信号凸块114′可以连接至第二半导体器件100e的信号凸块114，并且通过插入凸块116a′和116e(图38中未示出；参见图1、图3、图14、图15、图22、图23、图30和图31所示的实施例)对准。
图39是根据一些实施例制造半导体器件100的方法的流程图170。在步骤172中，绝缘材料层106形成在衬底102上方。在步骤174中，从衬底102的信号凸块区域124的至少一部分去除绝缘材料层106的一部分，以暴露衬底102的信号凸块区域124。例如，在图8和图9中，从信号凸块区域124完全去除绝缘材料层106。作为另一个实例，在图16和图17中，也从信号凸块区域124完全去除绝缘材料层106。作为又一个实例，在图24和图25中，从信号凸块区域124的一部分去除绝缘材料层106，在信号凸块区域124的另一部分中仍然保留绝缘材料层106。在步骤176中，一个或多个插入凸块116形成在绝缘材料层106上方。在步骤178中，信号凸块114形成在衬底100的信号凸块区域中。
本发明的一些实施例包括制造半导体器件的方法，并且还包括使用本文中所述的方法制造的半导体器件。本发明的一些实施例还包括具有本文中所述的新半导体器件的半导体器件封装。
本发明的一些实施例的优点包括：提供具有形成在绝缘材料层106上方的插入凸块116(如图1和图3所示)的半导体器件100，从而远离衬底102升高插入凸块116，使得插入凸块116的顶面高于信号凸块114的顶面，以在封装工艺期间提供改进的机械对准和插入。当两个半导体器件100和/或100′连接在一起时，在绝缘材料层106上形成插入凸块116产生插入凸块116与插入凸块116、116′或146的重叠，从而减小管芯移动的风险。
当将一个半导体器件附接至另一个半导体器件时，插入凸块116、116′和146提供改进的对准，以确保信号凸块114、114′和144的正确对准。在用于电和机械地连接相邻半导体器件的信号凸块114和144的焊料回流工艺之前、期间和之后，插入凸块116、116′和146还保持半导体器件100的正确对准。新插入凸块116、116′和146还改进对准精度。
本发明的一些实施例利用插入焊接，以避免由于管芯附接和封装传送所导致的弯曲和/或管芯移动。作为另一个实例，在一些实施例中，尤其在半导体器件100的边缘或角部中，由于重叠的插入凸块116、116′以及146所产生的摩擦力可以避免大弯曲。
具有插入凸块116、116′和146的半导体器件100和100′提供可靠的和低成本的管芯堆叠结构和制造方法。可以垂直地堆叠半导体器件100和100′，而不使用焊剂或热压接合(TCB)，从而导致减少的热预算。因为不使用焊剂，所以有利地不要求从半导体器件封装120和160去除焊剂的清洁工艺。插入凸块116、116′和146防止管芯附接之后的管芯移动，并且从而改进成品率和可靠性。减少了制造处理时间，从而导致每小时生产的晶圆(WPH)增加。
在一些实施例中，信号凸块114的多个部分也形成在绝缘材料层106的多个部分上方，有利地，从而提供用于信号凸块114的增加的结构支撑。在一些实施例中，因为在回流工艺期间还在插入凸块116、116′上回流焊料，所以用于连接相邻封装件的信号凸块114、114′和144的焊料回流工艺还导致相邻封装件的插入凸块116、116′、和146的机械连接，从而导致用于半导体器件封装120和160的总体结构强度的改进。在一些实施例中，插入凸块116、116′、和/或146包括楔形侧壁，从而放大自对准容限。
新插入凸块结构和设计在制造和封装处理流程中可容易地实现，并且在一些实施例中，仅要求一个附加材料层(例如，绝缘材料层106)和光刻工艺。在其他实施例中，例如，在半导体器件的另一部分上所使用的绝缘材料层和光刻处理可以用于形成设置在插入凸块下方的绝缘材料层106。
根据本发明的一些实施例，半导体器件包括：衬底；绝缘材料层，在衬底的表面上具有开口；一个或多个插入凸块，设置在绝缘材料层上方。半导体器件包括具有不设置在绝缘材料层上方的部分的多个信号凸块。
根据其他实施例，制造半导体器件的方法包括：在衬底上方形成绝缘材料层，并且去除绝缘材料层的一部分，以暴露衬底的信号凸块区域。该方法包括：在绝缘材料层上方形成一个或多个插入凸块，以及在衬底的信号凸块区域中形成多个信号凸块。
根据其他实施例，半导体器件封装包括第一半导体器件，第一半导体器件包括：衬底；绝缘材料层，在衬底的表面上具有开口；一个或多个第一插入凸块，设置在绝缘材料层上方；以及多个信号凸块，具有不设置在绝缘材料层上方的部分。半导体器件封装包括：第二半导体器件，连接至第一半导体器件的多个信号凸块，第二半导体器件包括一个或多个第二插入凸块，其中，一个或多个第二插入凸块与一个或多个第一插入凸块机械对准。
虽然详细地描述了本发明的一些实施例及其优点，但是应该理解，可以在不脱离如所附权利要求限定的本发明的精神和范围的情况下，作出多种改变、替换和更改。例如，本领域技术人员容易地理解，本文中所述的多个特征、功能、工艺和材料可以改变，同时保持在本发明的范围内。而且，本申请的范围不旨在限于在说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。由于本领域普通技术人员根据本公开可以很容易地想到，目前存在的或者随后开发的执行与这里所述的相应实施例基本相同的功能或者完成与这里所述的相应实施例基本相同的结果的工艺、机器、制造、材料组分、装置、方法和步骤的组合可以根据本公开被利用。从而，所附权利要求旨在在它们的范围内包括这种工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (18)

1.一种半导体器件，包括：
衬底；
绝缘材料层，在所述衬底的表面上具有开口；
一个或多个插入凸块，设置在所述绝缘材料层上方；以及
多个信号凸块，具有不设置在所述绝缘材料层上方的部分；
其中，所述一个或多个插入凸块的最顶部分和所述多个信号凸块的最顶部分不在一个水平面上，所述一个或多个插入凸块包括导电材料并且和所述多个信号凸块通过喷镀工艺同时形成，所述一个或多个插入凸块的最顶部分与所述衬底的表面之间的第一距离大于所述多个信号凸块的最顶部分与所述衬底的表面之间的第二距离；
另一衬底，接合至所述衬底，其中，所述一个或多个插入凸块与位于所述另一衬底上的插入凸块机械地对准，所述一个或多个插入凸块与位于所述另一衬底上的插入凸块之间存在间隙。
2.根据权利要求1所述的半导体器件，其中，所述多个信号凸块包括：不设置在所述绝缘材料层上方的第一部分和设置在所述绝缘材料层上方的第二部分。
3.根据权利要求1所述的半导体器件，其中，所述多个信号凸块中的每个信号凸块都在所述衬底的所述表面上设置在接触焊盘上方。
4.根据权利要求1所述的半导体器件，其中，从上往下看时，所述一个或多个插入凸块包括：形成多边形的顶点的三个或更多个插入凸块。
5.根据权利要求1所述的半导体器件，其中，所述一个或多个插入凸块之一是插头。
6.根据权利要求1所述的半导体器件，其中，所述一个或多个插入凸块之一具有空心的插座形状。
7.根据权利要求6所述的半导体器件，其中，所述一个或多个插入凸块具有楔形侧壁。
8.根据权利要求6所述的半导体器件，其中，所述一个或多个插入凸块具有竖直的侧壁。
9.根据权利要求6所述的半导体器件，其中，从上往下看时，具有所述空心的所述插座形状的所述一个或多个插入凸块包括圆形或正方形。
10.一种制造半导体器件的方法，所述方法包括：
在衬底上方形成绝缘材料层；
去除所述绝缘材料层的一部分，以暴露所述衬底的信号凸块区域；
在所述绝缘材料层上方形成一个或多个插入凸块；以及
在所述衬底的所述信号凸块区域中形成多个信号凸块；
其中，所述一个或多个插入凸块的最顶部分和所述多个信号凸块的最顶部分不在一个水平面上，所述一个或多个插入凸块的最顶部分与所述衬底的表面之间的第一距离大于所述多个信号凸块的最顶部分与所述衬底的表面之间的第二距离，形成所述一个或多个插入凸块和形成所述多个信号凸块包括：使用镀工艺同时形成所述一个或多个插入凸块和所述多个信号凸块；
将所述衬底接合至另一衬底，其中，所述一个或多个插入凸块与位于所述另一衬底上的插入凸块机械地对准，所述一个或多个插入凸块与位于所述另一衬底上的插入凸块之间存在间隙。
11.根据权利要求10所述的方法，进一步包括：
在所述衬底的所述信号凸块区域上方以及所述绝缘材料层上方沉积晶种层；
在所述绝缘材料层上方图案化部分所述晶种层上方的掩蔽材料；
去除图案化的掩蔽材料；以及
去除部分所述晶种层，其中，形成所述一个或多个插入凸块和形成所述多个信号凸块包括：在所述掩蔽材料的图案之间的所述晶种层上镀导电材料。
12.根据权利要求10所述的方法，其中，所述绝缘材料层包括：氮化硅、聚酰亚胺或聚苯并恶唑(PBO)。
13.根据权利要求10所述的方法，其中，所述绝缘材料层是厚度为5μm至10μm的材料层。
14.根据权利要求10所述的方法，进一步包括：
在形成所述插入凸块之前，从所述衬底接近所述一个或多个插入凸块的区域中去除所述绝缘材料层；
在所述绝缘材料层、所述信号凸块区域以及所述衬底上方形成晶种层；
在所述晶种层上方形成掩蔽材料；
去除所述掩蔽材料位于所述信号凸块区域和所述绝缘材料层上方的部分；
使用镀工艺形成所述多个信号凸块和所述一个或多个插入凸块；
去除所述掩蔽材料；以及
去除所述晶种层的暴露部分。
15.根据权利要求10所述的方法，进一步包括：
在所述绝缘材料层、所述信号凸块区域的暴露部分以及所述衬底上方形成晶种层；
图案化所述晶种层上方的掩蔽材料；
镀所述一个或多个插入凸块和所述多个信号凸块；
去除所述掩蔽材料；以及
去除所述晶种层的暴露部分，其中，去除部分所述绝缘材料层还暴露所述衬底接近所述一个或多个插入凸块的区域，并且所述多个信号凸块包括由所述绝缘材料层在周围包围的第一部分和位于所述第一部分和周围的所述绝缘材料层上方的第二部分。
16.一种半导体器件封装，包括：
第一半导体器件，包括：衬底；绝缘材料层，在所述衬底的表面上具有开口；一个或多个第一插入凸块，设置在所述绝缘材料层上方；以及多个信号凸块，具有不设置在所述绝缘材料层上方的部分，其中，所述一个或多个第一插入凸块的最顶部分和所述多个信号凸块的最顶部分不在一个水平面上，所述一个或多个第一插入凸块包括导电材料并且和所述多个信号凸块通过喷镀工艺同时形成，所述一个或多个第一插入凸块的最顶部分与所述衬底的表面之间的第一距离大于所述多个信号凸块的最顶部分与所述衬底的表面之间的第二距离；以及
第二半导体器件，连接至所述第一半导体器件的所述多个信号凸块，所述第二半导体器件包括一个或多个第二插入凸块，其中，所述一个或多个第二插入凸块与所述一个或多个第一插入凸块机械地对准，所述一个或多个第二插入凸块与所述一个或多个第一插入凸块之间存在间隙。
17.根据权利要求16所述的半导体器件封装，其中，所述衬底包括第一衬底，所述绝缘材料层包括第一绝缘材料层，并且所述第二半导体器件包括第二衬底以及设置在所述第二衬底和所述第二插入凸块之间的第二绝缘材料层。
18.根据权利要求16所述的半导体器件封装，其中，所述第一半导体器件和所述第二半导体器件包括集成电路管芯、封装器件或封装衬底。
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