CN104299952A - 在宽金属焊盘上方形成凸块结构的机制 - Google Patents

在宽金属焊盘上方形成凸块结构的机制 Download PDF

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Publication number
CN104299952A
CN104299952A CN201310464580.5A CN201310464580A CN104299952A CN 104299952 A CN104299952 A CN 104299952A CN 201310464580 A CN201310464580 A CN 201310464580A CN 104299952 A CN104299952 A CN 104299952A
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groove
conductive layer
solder projection
semiconductor element
layer
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CN104299952B (zh
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蔡仲豪
王垂堂
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了用于形成半导体管芯的机制的实施例。半导体管芯包括半导体衬底和形成在半导体衬底上方的保护层。半导体管芯还包括共形地形成在保护层上方的导电层和形成在导电层中的凹槽。凹槽环绕导电层的区域。半导体管芯还包括形成在被凹槽围绕的导电层区域上方的焊料凸块。本发明还提供了在宽金属焊盘上方形成凸块结构的机制。

Description

在宽金属焊盘上方形成凸块结构的机制
技术领域
本发明总的来说涉及半导体领域，更具体地，涉及在宽金属焊盘上方形成凸块结构的机制。
背景技术
半导体器件用于各种电子应用中，诸如个人电脑、手机、数码相机或其他电子设备。一般通过在半导体衬底上方依次沉积绝缘层或介质层、导电层和半导体层，然后使用光刻和蚀刻工艺图案化各个材料层以在半导体衬底上形成电路部件和元件来制造半导体器件。
半导体产业通过不断减小最小部件的尺寸，来不断提高各种电子部件（例如，晶体管、二极管、电阻器、电容器等）的集成度，这允许更多的部件被集成到给定区域中。在一些应用中，这些更小的电子部件还需要利用更小面积或更小高度的更小封装件。
已经开发出新的封装技术以提高半导体器件的密度和功能。这些用于半导体器件的相关新型封装技术面临着制造的挑战。
发明内容
根据本发明的一个方面，提供了一种半导体管芯，包括：半导体衬底；保护层，形成在半导体衬底上方；导电层，共形地形成在保护层上方，在导电层中形成一个凹槽，并且凹槽围绕导电层的区域；以及焊料凸块，形成在导电层被凹槽围绕的区域上方。
优选地，凹槽是环形凹槽。
优选地，凹槽被焊料凸块完全填满，并且焊料凸块延伸跨过导电层的区域。
优选地，焊料凸块的一部分延伸至凹槽内。
优选地，凹槽是弧形凹槽。
优选地，保护层沿着穿过焊料凸块的中心点的垂直线位于半导体衬底与中心点之间。
优选地，由聚合物材料制成保护层。
优选地，在保护层的凹槽开口上方共形地形成导电层。
优选地，保护层和导电层在衬底上方延伸，并且焊料凸块设置在衬底上方。
优选地，该半导体管芯还包括形成在导电层上方且与焊料凸块相邻的第二焊料凸块。
优选地，凹槽的宽度与区域的直径的比率介于约1.6%至约40%之间。
优选地，导电层在凹槽边缘处具有凸起结构。
根据本发明的另一方面，提供了一种半导体管芯，包括：半导体衬底；保护层，形成在半导体衬底上方；导电层，共形地形成在保护层上方，在导电层中形成多个凹槽，并且凹槽围绕导电层的区域；以及焊料凸块，形成在导电层被凹槽围绕的区域上方。
优选地，凹槽包括第一凹槽和第二凹槽，第一凹槽和第二凹槽是环形的，并且第二凹槽围绕第一凹槽。
优选地，焊料凸块完全填满第一凹槽并延伸至第二凹槽内。
优选地，凹槽是弧形的。
优选地，凹槽包括第一凹槽、第二凹槽、第三凹槽和第四凹槽，并且第三凹槽和第四凹槽围绕第一凹槽和第二凹槽。
优选地，第一凹槽与第三凹槽与第四凹槽之间的第一空间相邻，以及第二凹槽与第三凹槽与第四凹槽之间的第二空间相邻。
根据本发明的又一方面，提供了一种半导体管芯，包括：半导体衬底；保护层，形成在半导体衬底上方；导电层，共形地形成在保护层上方，在导电层中形成第一凹槽和第二凹槽，第一凹槽围绕导电层的第一区域，且第二凹槽围绕导电层的第二区域；第一焊料凸块，形成在导电层被第一凹槽围绕的第一区域上方；以及第二焊料凸块，形成在导电层被第二凹槽围绕的第二区域上方。
优选地，第一焊料凸块的尺寸和形状与第二焊料凸块的尺寸和形状基本相同。
附图说明
为了更完整地理解实施例及其优势，现结合附图参考以下描述，其中：
图1A和图1B分别是根据一些实施例的半导体管芯的截面图和半导体管芯在形成焊接凸块之前的顶视图。
图2A至图2I是根据一些实施例的用于形成半导体管芯的工艺在各个阶段的截面图。
图3是根据一些实施例的半导体管芯的导电层的顶视图。
图4A和图4B是根据一些实施例的用于形成半导体管芯的工艺在各个阶段的截面图。
图4C是根据一些实施例的半导体管芯的截面图。
图5A和图5B分别是根据一些实施例的半导体管芯的截面图和半导体管芯的导电层的顶视图。
图6A和图6B分别是根据一些实施例的半导体管芯的截面图和半导体管芯的导电层的顶视图。
图6C是根据一些实施例的半导体管芯的导电层的顶视图。
图6D是根据一些实施例的半导体管芯的导电层的顶视图。
图7A和图7B分别是根据一些实施例的半导体管芯的截面图和半导体管芯的导电层的顶视图。
图8A和图8B分别是根据一些实施例的半导体管芯的截面图和半导体管芯的导电层的顶视图。
图9A和9B分别是根据一些实施例的半导体管芯的截面图和半导体管芯的导电层的顶视图。
图10A和10B分别是根据一些实施例的半导体管芯的截面图和半导体管芯的导电层的顶视图。
图11是根据一些实施例的管芯封装件的截面图。
具体实施方式
下面将详细论述本发明的实施例的制造与使用。然而，应该理解，本发明的实施例可以体现在各种具体环境中中。论述的具体实施例仅用于说明，而不限制本发明的范围。
应该理解，以下公开内容提供了用于实施本发明的不同特征的许多不同的实施例或实例。以下描述了部件和布置的具体实施例以简化本发明。当然，这些仅仅是实例而不旨在限制本发明。另外，在下面的描述中，在第二工艺之前实施第一工艺包括在第一工艺之后立即实施第二工艺的实施例，并且还包括在第一和第二工艺之间实施额外工艺的实施例。为了简化和清楚起见，可以按不同的比例任意绘制各种部件。此外，在下面的描述中，在第二部件上方或之上形成第一部件包括第一和第二部件以直接接触的方式形成的实施例，并且也包括在第一和第二部件之间形成额外的部件，从而使得第一和第二部件不直接接触的实施例。
描述了实施例的一些变体。在各个附图和示例性实施例中，相似的参考数字用于代表相似的元件。
图1A和1B分别是根据一些实施例的半导体管芯190A的截面图和半导体管芯190A在形成焊接凸块122a和122b之前的顶视图。图1A是沿着图1B所示的剖线I-I′的半导体管芯190A的一部分在形成焊料凸块之后的截面图。在一些实施例中，部件190A是管芯封装件。
如图1A和1B所示，提供半导体衬底100。在一些实施例中，在半导体衬底100中和/或上形成器件元件。半导体衬底100被定义为是包括半导体材料的任何结构。半导体衬底100包括块状硅衬底、部分半导体晶圆、绝缘体上硅（SOI）衬底或硅锗衬底。也可以使用包括III族、IV族和V族元素的其他半导体材料。
半导体衬底100还可包括隔离部件（未示出），诸如浅沟槽隔离（STI）部件或硅局部氧化（LOCOS）部件。隔离部件限定和隔离各种器件元件。
可在半导体衬底100中形成的各种器件元件的实例包括晶体管（比如，金属氧化物半导体场效应晶体管（MOSFET）、互补金属氧化物半导体（CMOS）晶体管、双级结型晶体管（BJT）、高压晶体管、高频晶体管、p沟道和/或n沟道场效应晶体管（PFET/NFET）等）、二极管、其他可应用元件或它们的组合。
根据一些实施例，如图1A所示，半导体衬底100上方形成互连结构102。互连结构102包括介电层和金属层。如图1A和1B所示，在半导体衬底100上的互连结构102上方形成接触焊盘104。互连结构102的金属层在形成在半导体衬底100中的各种器件元件与接触焊盘104之间提供电连接。可由铝、铜、金、铂、其他可适用的材料或它们的组合制成接触焊盘104。可通过各种沉积和图案化工艺形成互连结构102和接触焊盘104。
根据一些实施例，如图1A所示，在互连结构102和接触焊盘104上方沉积并图案化第一钝化层106。图案化第一钝化层106以具有露出接触焊盘104的开口。可由氧化硅、氮化硅、氮氧化硅、其他可应用材料或它们的组合制成第一钝化层106。可通过使用CVD工艺沉积第一钝化层106，然后通过使用光刻工艺和蚀刻工艺进行图案化。
根据一些实施例，如图1A所示，然后在第一钝化层106和接触焊盘104上方沉积并图案化第二钝化层108。图案化第二钝化层108以具有露出接触焊盘104的开口。可由诸如聚合物材料的介电材料制成第二钝化层108。聚合物材料可包括聚苯并恶唑（PBO）、环氧树脂、聚酰亚胺、其他适合的材料或它们的组合。在一些实施例中，通过使用旋涂工艺沉积第二钝化层108，并通过光刻工艺进行图案化。根据一些实施例，在第二钝化层108和接触焊盘104上方沉积并图案化导电层116。
导电层116也被称为后钝化互连（PPI）层。导电层116用于在接触焊盘104与诸如焊料凸块122a和122b的焊料凸块之间提供电连接。可由Cu、Al、Au、Pt、Ti、其他可应用的材料或它们的组合制成导电层116。导电层116可通过使用镀工艺、PVD工艺、CVD工艺、其他可应用的工艺沉积，然后通过使用光刻工艺和蚀刻工艺进行图案化。
导电层116的图案包括任何期望的图案。例如，导电层116具有如图1B所示的图案。导电层116可具有彼此电绝缘的多个部分。
如图1B所示，每一部分都具有互连部分16i和球焊盘部分16b。互连部分16i用于将球焊盘部分16b电连接至相应的一个接触焊盘104。球焊盘部分16b用于限定形成焊料凸块的位置。
导电层116的部分也可包括宽焊盘部分16w，其可用于电源和/或接地。宽焊盘部分16w的面积是球焊盘部分16b的面积的若干倍。因此，需要在宽焊盘部分16w上形成多个焊料凸块。在随后的接合工艺期间，多个焊料凸块一起支撑半导体衬底100。例如，半导体管芯190A接合至另一个封装件（诸如管芯封装件）或衬底（诸如PCB板或板）。
根据一些实施例，在导电层116上形成焊料凸块122a和122b。于球焊盘部分16b的其中一个上形成焊料凸块122a。在用于形成焊料凸块122a和122b的回流工艺期间，用于形成焊料凸块122a的焊料限制在导电层116的球焊盘部分16b上。因此焊料凸块122a形成在期望位置并具有期望的结构。在一些实施例中，如图1A所示，焊料凸块122a覆盖导电层116的球焊盘部分16b的边缘。
然而，在回流工艺期间，与球焊盘部分16b上的焊料相比，宽焊盘部分16w上的焊料相对自由地移动。在一些实施例中，起初预期在宽焊盘部分16w的位置L上形成焊料凸块122b。由于焊料在宽焊盘部分16w上相对自由移动，所以宽焊盘部分16w上的焊料可从位置L扩展。从而，焊料凸块122并未精确地形成于位置L处，而是具有比预期结构（如图1A中虚线123所示）更宽和更矮的结构。
焊料凸块122b具有高度H2，高度H2小于焊料凸块122a的高度H1。因此，当半导体管芯190A接合至另一个元件（诸如衬底或封装件）时，焊料凸块122b可能不能接合至元件。焊料凸块122b可具有宽度W2，宽度W2大于焊料凸块122a的宽度W1。因此，在回流工艺期间，焊料凸块122b与相邻凸块之间的距离会变短。
根据一些实施例，为减少或解决上面所述的问题，在导电层上形成凹槽以帮助限制焊料凸块的位置和结构。
图2A至图2I是根据一些实施例的用于形成半导体管芯190B的工艺在各个阶段的截面图。在一些实施例中，部件190B是管芯封装件。
根据一些实施例，如图2A所示，在半导体衬底100上方形成互连结构102、接触焊盘104和第一钝化层106。上面已经描述了这些元件的材料和制造方法。然后，如图2B所示，在第一钝化层106和接触焊盘104上方沉积第二钝化层108。
根据一些实施例，如图2C所示，图案化第二钝化层108以在第二钝化层108中形成孔110和凹槽开口111。孔110露出了接触焊盘104。凹槽开口111露出了第一钝化层106。在一些实施例中，凹槽开口111是环形的。凹槽开口111可以是圆环形、方环形、矩形环形或具有其他适合的形状。因此，图2C中所示的两个孔状凹陷（标记为“111”）实际上是互相连接的。两个孔状凹陷是同一个环形凹槽的一部分。
虽然图2C中所示的凹槽开口111露出了第一钝化层106，但是本发明的实施例并不限于此。在一些其他实施例中，凹槽开口111自第二钝化层108的上表面延伸而不会完全穿透保护层。因此，第一钝化层106并未通过凹槽开口111露出。
然后，在第二钝化层108和接触焊盘104上方形成导电层。如上所述，可通过使用多种工艺形成导电层。在以下说明中，电镀工艺被用作用于说明的实例。
如图2D所示，在第二钝化层108和接触焊盘104上方沉积晶种层112。在一些实施例中，晶种层112由Cu或Cu合金制成。也可使用诸如Au的其他导电材料。在一些实施例中，阻挡层（未示出）位于晶种层112下面且夹在晶种层112与第二钝化层108或第一钝化层106之间。在一些实施例中，阻挡层由Ti或Ti合金制成。晶种层112和阻挡层可用作UBM层。可通过PVD工艺或其他可应用的工艺依次地沉积阻挡层和晶种层112。
然后，根据一些实施例，在晶种层112上方沉积并图案化掩膜层114。掩膜层114包括光刻胶层。掩膜层114被图案化为具有多个开口，其与预期将要形成的导电层的期望图案相应。如图2D所示，被掩膜层114的其中一个开口露出的晶种层112限定导电层的部分图案。露出的晶种层112的顶视图与图1B中所示的导电层116的顶视图类似。然而，应该指出，根据需求可以改变图案。
根据一些实施例，如图2E所示，通过电镀工艺，在露出的晶种层112上方沉积导电层116。在一些实施例中，导电层116由Cu或Cu合金制成。也可使用其他导电材料。在电镀工艺期间，没有金属材料沉积在被掩膜层114覆盖的晶种层112上。
在一些实施例中，在晶种层112上方共形地形成导电层116。同样在第二钝化层108上方共形地形成晶种层112。通过调整第二钝化层108的表面轮廓，相应地调整导电层116的表面轮廓。在一些实施例中，导电层116具有开口113和凹槽115。
如图2F所示，依次去除掩膜层114和位于掩膜层114下方的晶种层112部分。在去除掩膜层114之后，可实施蚀刻工艺以去除露出的晶种层112。在用于去除最初位于掩膜层114下方的那部分晶种层112的蚀刻工艺期间，也可以去除导电层116的上部。如图2F所示，从而形成具有期望图案的导电层116。
图3是根据一些实施例的图2F中所示的导电层116的顶视图。如图3所示，凹槽115是圆环形凹槽。凹槽115的外缘围绕将要形成焊料凸块的导电层116的区域R。凹槽115的宽度W3介于约5μm至约40μm之间。区域R的直径D可介于约100μm至约300μm之间。宽度W3与直径D的比率介于约1.6%至约40%之间。另外，开口113的宽度W4介于约5μm至约30μm之间。在一些实施例中，凹槽115是圆环形、方环形、矩形环形或具有其他适合的形状。
根据一些实施例，如图2G所示，助焊剂118施加在导电层116上方。助焊剂118施加在被凹槽115（即，环形凹槽）围绕的区域R上方。由于凹槽115的存在，所以助焊剂118被限定在区域R内。即使提供过量的助焊剂118，凹槽115也容纳助焊剂118的过量部分。防止助焊剂118延伸跨过区域R。
根据一些实施例，如图2H所示，将焊球120放置在助焊剂118上。焊球120通过助焊剂118粘附至导电层116且被放置在期望的位置（区域R上方）。焊球120可包括铅或不含铅。在一些实施例中，在放置焊球之后，助焊剂118流入凹槽115内。由于凹槽115，所以助焊剂118基本上被限定在相同位置（区域R）。因此，焊球120被放置在区域R上方而不会移动。
根据一些实施例，如图2I所示，实施回流工艺以形成焊料凸块122。在回流工艺期间，助焊剂118蒸发而焊球120熔化并被回流成焊料凸块122。由于凹槽115，使来源于焊球120的焊料限定在凹槽115围绕的区域R内。防止焊料凸块122的位置从区域R中扩散和移动。因此，由于限定了焊料，所以当形成焊料凸块122时，获得了期望的结构。精确地控制焊料凸块122的宽度、高度、位置和形状。
在一些其他实施例中，焊料可完全填满凹槽115并延伸跨过区域R。焊料的大部分被限制在区域R中，而焊料的剩余部分小幅地延伸在区域R上方。焊料材料仍然被限制在区域R上方。因此，仍然精确地控制了焊料凸块122的宽度、高度、位置和形状。
根据一些实施例，如图2I所示，部分第二钝化层108正好位于焊料凸块122的中心点C下方。垂直线ML穿过焊料凸块122的中心点C并与半导体衬底100的顶面基本垂直，垂直线ML也穿过第二钝化层108。第二钝化层108沿着垂直线ML夹在焊料凸块122的中心点C与半导体衬底100之间。由于第二钝化层108是有弹性和柔软的，所以第二钝化层108可降低施加在位于焊料凸块122正下方的半导体衬底100上的应力。显著降低了半导体衬底100的破裂风险。
本发明的实施例具有很多变化例。在下面的说明中描述了一些变化例。图4A和4B是根据一些实施例的用于形成半导体管芯190C的工艺在各个阶段的截面图。根据一些实施例，如图4A所示，导电层116在凹槽115边缘处具有凸起结构101。因此，通过凸起结构101进一步限制助焊剂118以防止助焊剂118流入凹槽115内。在一些实施例中，导电层116在开口113的边缘处也具有凸起结构103。
根据一些实施例，如图4B所示，然后实施回流工艺以形成焊料凸块122。在回流工艺过程中，助焊剂118蒸发而焊球120熔化并被回流成焊料凸块122。由于凸起结构101，来源于焊球120的焊料被限定在凸起结构101和凹槽115围绕的区域R内。在一些实施例中，焊料凸块122没有延伸至凹槽115内。
图4C是根据一些实施例的半导体管芯190D的截面图。如图4C所示，部分焊料凸块122可能延伸跨过凸起结构101并填充凹槽115。
图5A和5B分别是根据一些实施例的半导体管芯190E的截面图和半导体管芯190E的导电层116的顶视图。如图5A和5B所示，包括凹槽115a和115b的多个凹槽用于限制焊料凸块122的位置和结构。凹槽115a和115b可以是环形凹槽。环形凹槽可以是圆形、方形、矩形或具有其他适合的形状的凹槽。
在一些实施例中，在第二钝化层108上方共形地形成导电层116之后，形成凹槽115a和115b。因此，同时形成凹槽115a和115b。第二钝化层108被图案化以具有与凹槽115a和115b相应的凹槽开口。例如，第二钝化层108具有环形凹槽开口。
在一些实施例中，凹槽115b的外缘围绕区域R，而凹槽115a围绕比区域R更小的区域。用于形成焊料凸块122的焊料可完全填满凹槽115a并延伸至凹槽115b内。焊料凸块122延伸到形成在导电层116中的一个以上的凹槽上方。
凹槽115b进一步确保焊料位于区域R内。因此，焊料凸块122被限制在区域R内。因此，获得位于期望位置上方并具有期望结构的焊料凸块122。在一些实施例中，富有弹性的和柔软的第二钝化层108位于焊料凸块122的中心点正下方以支撑焊料凸块122。由于第二钝化层108位于焊料凸块122正下方，因此防止破坏半导体衬底100。
在一些实施例中，凹槽115a的宽度W5与凹槽115b的宽度W6相同。在一些实施例中，凹槽115a的宽度W5与凹槽115b的宽度W6不同。凹槽115a宽度W5介于约5μm至约40μm之间。凹槽115b的宽度W6介于约5μm至约40μm之间。区域R的直径D介于约100μm至约300μm之间。宽度W5与直径D的比率介于1.6%至40%之间。宽度W6与直径D的比率介于1.6%至40%之间。
图6A和6B分别是根据一些实施例的半导体管芯190F的截面图和半导体管芯190F的导电层116的顶视图。导电层116具有包括排列成圆形的凹槽117a、117b、117c和117d的多个凹槽。凹槽117a、117b、117c和117d不限于环形凹槽。如图6A所示，凹槽117a、117b、117c和117d是形成于导电层116中但没有穿透导电层116的开口。凹槽117a、117b、117c和117d的形状可包括圆形、矩形、正方形或其他适合的形状。凹槽的数量不只限于四个。在一些其他实施例中，使用更多或更少的凹槽。
在一些实施例中，凹槽117a、117b、117c和117d围绕区域R并且也能够限制用于形成焊料凸块122的焊料。焊料凸块122的位置和结构也被精确地控制。如图6A所示，第二钝化层108位于焊料凸块122的中心点C的正下方以支撑焊料凸块122。从而保护位于焊料凸块122正下方的半导体衬底100。
凹槽117a、117b、117c和117d分别具有宽度W7、W8、W9和W10。在一些实施例中，宽度W7、W8、W9和W10是相同的。在一些实施例中，宽度W7、W8、W9和W10的一些或全部互不相同。
图6C是根据一些实施例的半导体管芯的导电层116的顶视图。如图6C所示，导电层116具有排列成圆形的凹槽610a、610b、610c和610d。根据一些实施例，凹槽610a、610b、610c和610d是弧形的且彼此分离。凹槽610a、610b、610c和610d围绕区域R且能够限制用于形成焊料凸块的焊料。也精确地控制了焊料凸块的位置和结构。应该注意的是，所述凹槽的数量并不限于四个。凹槽的数量可以是两个、三个、五个或六个。
图6D是根据一些实施例的半导体管芯的导电层116的顶视图。如图6D所示，在一些实施例中，导电层116具有排列成圆形的凹槽610a、610b、610c和610d。此外，导电层116还具有被凹槽610a、610b、610c和610d围绕的排列成另一个圆形的凹槽610e、610f、610g和610h。
根据一些实施例，凹槽610e、610f、610g和610h是弧形的且彼此分离。凹槽610e与凹槽610a与凹槽610c之间的空间S1相邻。凹槽610f与凹槽610b与凹槽610c之间的空间S2相邻。凹槽610g与凹槽610b与凹槽610d之间的空间S3相邻。凹槽610h与凹槽610a与凹槽610d之间的空间S4相邻。这些凹槽能够限制用于形成焊料凸块的焊料。也精确地控制了焊料凸块的位置和结构。
图7A和7B分别是根据一些实施例的半导体管芯190G的截面图和半导体管芯190G的导电层116的顶视图。类似于图3中所示的实施例，导电层116包括凹槽115，凹槽115是环形的且限定区域RA。在一些实施例中，区域RA的面积小于图3、图5B和图6B中所示的区域R的面积。在一些实施例中，用于形成焊料凸块122的焊料完全填满凹槽115并小幅地延伸跨过区域RA。因此，焊料凸块122覆盖凹槽115并延伸到围绕凹槽115的部分导电层116上。焊料凸块122仍然基本上被限制在区域RA上方。也精确地控制了焊料凸块122的位置和结构。
图8A和8B分别是根据一些实施例的半导体管芯190H的截面图和半导体管芯190H的导电层116的顶视图。在导电层116中形成凹槽119。凹槽119不限于环形的或圆孔。例如，凹槽119是弧形的。在一些实施例中，图8A和8B中的导电层116是图1B中所示半导体衬底100的拐角区N中的导电层116。凹槽119限定区域RB。凹槽119与导电层116的边缘共同将用于形成焊料凸块122的焊料基本上限制在区域RB内。也精确地控制了焊料凸块122的位置和结构。在一些实施例中，如图8A所示，焊料凸块122覆盖导电层116的边缘。
图9A和9B分别是根据一些实施例的半导体管芯190I的截面图和半导体管芯190I的导电层116的顶视图。
如图9A和9B所示，包括凹槽115a和115b的多个凹槽用于限制焊料凸块122的位置和结构。凹槽115a和115b可以是环形凹槽。环形凹槽可以是圆形、正方形、矩形，或具有其他适合的形状。在一些实施例中，凹槽115b的外缘围绕区域RC以保证焊料凸块122形成在区域RC内。凹槽115a的外缘围绕区域R，其中区域R的面积小于区域RC的面积。
如图9A所示，在凹槽115a围绕的区域R内形成焊料凸块122。凹槽115b用作阻挡件（back up）以将用于形成焊料凸块122的焊料保持在区域RC内。因此获得位于期望位置上方并具有期望结构的焊料凸块122。在一些实施例中，焊料凸块122的中心点C位于第二钝化层108的正上方。第二钝化层108向焊料凸块122提供支撑。因此，位于焊料凸块122正下方的半导体衬底100受到第二钝化层108的保护。
图10A和10B分别是根据一些实施例的半导体管芯190J的截面图和半导体管芯190J的导电层116的顶视图。如图10A和10B所示，除了半导体管芯190J具有多个彼此相邻的焊料凸块122之外，半导体管芯190J与图2I中所示的半导体管芯190B相似。导电层116具有分别位于两个焊料凸块122下方的多个凹槽115。也就是说，在导电层116上有不只一个焊料凸块122且它们被焊料凸块122下方的凹槽115所限制。
本发明的实施例不仅可用于扇入结构，还可用于扇出结构。图11是根据一些实施例的管芯封装件1100的截面图。
如图11所示，可将半导体衬底100安装在衬底1110中。衬底1110可由模塑料或其他可应用的材料制成。可在第二钝化层108和第一钝化层106之间形成钝化层107。可在接触焊盘104和晶种层112之间形成导电元件109。第二钝化层108和导电层116可在衬底1110上方延伸。导电层116也可具有凹槽115。因此，焊料凸块122基本上被限制在由凹槽115围绕的区域R上方。也精确地控制了焊料凸块122的位置和结构。
应该注意，在以上实施例中，焊料凸块122具有类似于图1A中的焊料凸块122a的宽度W1和高度H1的宽度和高度。降低了相邻凸块之间短路的风险。提高了将以上实施例的半导体管芯接合至另一个封装件（或衬底）的产量。
提供了在宽导电层上形成焊料凸块的机制的实施例。在焊料凸块的边缘上形成凹槽以限制焊料凸块。可使用各种结构的凹槽。用于形成焊料凸块的焊料被限制在凹槽围绕的区域内或小幅地延伸跨过凹槽。该机制使焊料凸块具有期望的宽度和高度。从而，精确地控制了焊料凸块的位置和结构。因此，大大地提高了将半导体管芯接合至另一个衬底或封装件的产量。
根据一些实施例，提供了一种半导体管芯。该半导体管芯包括半导体衬底和形成于半导体衬底上方的保护层。半导体管芯还包括共形地形成于保护层上方的导电层和形成于导电层中的凹槽。凹槽围绕导电层的区域。半导体管芯还包括形成于被凹槽围绕的导电层区域上方的焊料凸块。
根据一些实施例，提供了一种半导体管芯。该半导体管芯包括半导体衬底和形成于半导体衬底上方的保护层。半导体管芯还包括共形地形成于保护层上方的导电层和形成于导电层中的多个凹槽。多个凹槽围绕导电层的一个区域。半导体管芯还包括形成于被凹槽围绕的导电层区域上方的焊料凸块。
根据一些实施例，提供了一种半导体管芯。该半导体管芯包括半导体衬底和形成于半导体衬底上方的保护层。半导体管芯还包括共形地形成于保护层上方的导电层和形成于导电层中的第一凹槽与第二凹槽。第一凹槽围绕导电层的第一区域，而第二凹槽围绕导电层的第二区域。半导体管芯还包括形成于被第一凹槽围绕的导电层的第一区域上方的第一焊料凸块。另外，半导体管芯包括形成于被第二凹槽围绕的导电层的第二区域上方的第二焊料凸块。
虽然详细描述了实施例及它们的优势，但应该理解，在不背离所附权利要求限定的本发明的精神和范围的情况下，可对本发明作出各种变化、替代和修改。此外，本申请的范围不旨在限制于说明书中所述的工艺、机器、制造、物质组成、工具、方法和步骤的特定实施例。根据本发明，作为本领域的普通技术人员将容易地从本发明中理解，根据本发明，可以利用现有的或今后将被开发的、执行与在本发明所述的对应实施例基本相同的功能或实现基本相同的结果的现存的或之后被开发的工艺、机器、制造、物质组成、工具、方法或步骤可能被利用。因此，所附权利要求旨在将这些工艺、机器、制造、物质组成、工具、方法或步骤包括它们的范围内。另外，每个权利要求构成一个单独的实施例，且不同权利要求和实施例的组合都在本发明的范围之内。

Claims (10)

1.一种半导体管芯，包括：
半导体衬底；
保护层，形成在所述半导体衬底上方；
导电层，共形地形成在所述保护层上方，在所述导电层中形成一个凹槽，并且所述凹槽围绕所述导电层的区域；以及
焊料凸块，形成在所述导电层被所述凹槽围绕的区域上方。
2.根据权利要求1所述的半导体管芯，其中，所述凹槽是环形凹槽。
3.根据权利要求1所述的半导体管芯，其中，所述凹槽被所述焊料凸块完全填满，并且所述焊料凸块延伸跨过所述导电层的所述区域。
4.根据权利要求1所述的半导体管芯，其中，所述焊料凸块的一部分延伸至所述凹槽内。
5.根据权利要求1所述的半导体管芯，其中，所述凹槽是弧形凹槽。
6.根据权利要求1所述的半导体管芯，其中，所述保护层沿着穿过所述焊料凸块的中心点的垂直线位于所述半导体衬底与所述中心点之间。
7.根据权利要求6所述的半导体管芯，其中，由聚合物材料制成所述保护层。
8.根据权利要求1所述的半导体管芯，其中，在所述保护层的凹槽开口上方共形地形成所述导电层。
9.一种半导体管芯，包括：
半导体衬底；
保护层，形成在所述半导体衬底上方；
导电层，共形地形成在所述保护层上方，在所述导电层中形成多个凹槽，并且所述凹槽围绕所述导电层的区域；以及
焊料凸块，形成在所述导电层被所述凹槽围绕的区域上方。
10.一种半导体管芯，包括：
半导体衬底；
保护层，形成在所述半导体衬底上方；
导电层，共形地形成在所述保护层上方，在所述导电层中形成第一凹槽和第二凹槽，所述第一凹槽围绕所述导电层的第一区域，且所述第二凹槽围绕所述导电层的第二区域；
第一焊料凸块，形成在所述导电层被所述第一凹槽围绕的第一区域上方；以及
第二焊料凸块，形成在所述导电层被所述第二凹槽围绕的第二区域上方。
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