KR100555706B1 - 미세 솔더볼 구현을 위한 ｕｂｍ 및 이를 이용한 플립칩패키지 방법 - Google Patents

미세 솔더볼 구현을 위한 ｕｂｍ 및 이를 이용한 플립칩패키지 방법 Download PDF

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KR100555706B1
KR100555706B1 KR1020030093209A KR20030093209A KR100555706B1 KR 100555706 B1 KR100555706 B1 KR 100555706B1 KR 1020030093209 A KR1020030093209 A KR 1020030093209A KR 20030093209 A KR20030093209 A KR 20030093209A KR 100555706 B1 KR100555706 B1 KR 100555706B1
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South Korea
Prior art keywords
ubm
substrate
solder ball
metal film
region
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KR1020030093209A
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KR20050061783A (ko
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송훈
심동식
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삼성전자주식회사
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Priority to KR1020030093209A priority Critical patent/KR100555706B1/ko
Priority to EP04029916A priority patent/EP1544916A1/en
Priority to US11/012,294 priority patent/US7309924B2/en
Priority to JP2004367236A priority patent/JP4105150B2/ja
Publication of KR20050061783A publication Critical patent/KR20050061783A/ko
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Publication of KR100555706B1 publication Critical patent/KR100555706B1/ko

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Abstract

미세 솔더볼 구현을 위한 UBM(Under Bump Metal) 및 이를 이용한 플립칩 패키지 방법이 개시된다. 본 발명에 의한 미세 솔더볼 구현을 위한 UBM은, 제1 기판 및 제2 기판 상에 형성된 대응되는 적어도 하나 이상의 제1 및 제2 전극단자를 플립칩 본딩시 이용되는 미세 솔더볼 구현을 위한 UBM에 있어서, 제1 전극단자 및 솔더볼 사이에 배치되어 전기적으로 연결되며, 돌출부의 주변에 측면이 소정 경사를 이루는 함몰부를 구비하는 제1 기판의 돌출부에 형성되는 금속막 및 돌출부에 접하는 경사 측면 위에 형성된 금속막을 포함한다. 본 발명에 의하면, 프립칩 패키지에 있어서 UBM를 양각 패턴 구조로 구성함으로서 미세 솔더볼 구현할 수 있을 뿐만아니라 패키지의 신뢰성을 높일 수 있다.
마이크로 접합, 플립칩 본딩, 솔더볼, UBM

Description

미세 솔더볼 구현을 위한 ＵＢＭ 및 이를 이용한 플립칩 패키지 방법{ＵＢＭ for fine pitch solder ball and flip-chip package method using the UBM}
도 1a 및 도 1b는 종래의 UBM을 이용한 플립칩 패키지를 보이는 도면,
도 2a 및 도 2b는 본 발명의 일실시예에 의한 UBM을 이용한 플립칩 패키지를 보이는 도면,
도 3은 본 발명의 다른 일실시예에 의한 UBM을 이용한 플립칩 패키지를 보이는 도면, 그리고
도 4a 내지 도4i는 도 2b의 UBM을 이용한 플립칩 패키지의 단계별 공정을 나타내는 단면도이다.
* 도면의 주요 부호에 대한 설명*
100 : 기판 111,112,211,212 : UBM
121,122,123 : 포토레지스트막 131, 132 : 솔더 범프
131a, 132a, 133, 134 : 솔더볼 200 : 반도체 칩 패드
본 발명은 반도체 플립칩 패키지 기술에 관한 것으로서, 보다 상세하게는 미 세 솔더볼 구현을 위한 UBM 및 이를 이용한 반도체 플립칩 패키지 방법에 관한 것이다.
반도체 칩의 고속화, 고집적화에 따라 소자의 크기가 미세화 되고 I/O수가 증가하고 있다. 이러한 요구에 따라 최근 반도체 칩을 최소한의 공간상에 패키징하는 볼 그리드 어레이(Ball Grid Array) 패키지, 칩 스케일 패키지 등이 등장하게 되었으며, 이러한 패키지는 와이어 본딩(Wire Bonding), 탭(TAB, Tape Automated Bonding) 및 플립칩 본딩(Flip-Chip Bonding) 등의 다양한 전기적 접속 방법으로 실장된다. 이들 전기적 접속 방법 중에서 고속, 고기능, 고밀도 실장에 가장 효과적인 방법은 플립칩 본딩이며, 플립칩 본딩은 반도체 칩에 배치된 전극과 기판의 접속단자를 직접 연결시키는 방식이다.
도 1a 및 도 1b는 종래의 플립칩 본딩 방식에 의한 패키지를 보이는 도면이다. 도 1a를 참조하면, 기판(10) 상의 접속단자(미도시) 위에 접속 매개체로서 솔더 범프(Solder Bump, 31, 32)를 증착하고, 리플로우(Reflow) 공정으로 솔더(31, 32)의 형상을 구형으로 만든 후 반도체 칩 패드(40)를 접합시킨다.
이때, 솔더볼(31, 32)이 기판(10) 및 반도체 칩 패드(40)에 잘 접착할 수 있도록 기판(10) 및 반도체 칩 패드(40)의 접착 표면에 UBM(Under Bump Metal, 21, 22, 41, 42)을 형성한다. UBM(21, 22, 41, 42)은 기판(10) 및 반도체 칩 패드(40)의 접합 영역 위에 Cr, Au, Ti, Cu 등의 금속을 증착 또는 에칭 등의 방법으로 형성되며, 솔더볼(31, 32)의 웨팅(Wetting)이 잘 이루어 지도록 하고, 솔더 성분이 반도체 칩 내부로 침투하지 못하도록 확산 방지의 역할을 한다.
그런데 전자제품의 소형화에 따라 패키지의 크기에 대한 관심이 고조되어 미세 피치 솔더 범프를 형성하면서, 패키지 신뢰성에 대한 문제가 발생하였다. 특히 솔더볼(31, 32) 위에 반도체 칩 패드(40)를 본딩시, 기판(10)과 패드(40)로 부터의 압력에 의해 도 2b에 나타낸 바와 같이 솔더볼(31, 32)에 shear stess가 작용하게 된다. 솔더볼(31, 32) 간의 피치는 솔더볼의 크기, 온도 및 인가되는 힘에 의해 결정된다. 종래 기술로는 shear stess에 의해 솔더볼(31, 32)을 좌우로 퍼지는 형상 변형으로 솔더볼 사이의 피치에 한계가 있다. 따라서 미세 피치를 갖는 패턴에는 그 적용이 어려운 문제점이 있다.
본 발명은, 상기한 문제점을 해결하기 위해 안출된 것으로서, UBM을 평면 패턴이 아닌 양각 패턴으로 구성하여, 본딩시 솔더볼의 퍼짐을 감소시켜 신뢰성 높은 미세 피치 솔더볼을 구현하는 것이 그 목적이다.
본 발명에 의한 미세 솔더볼 구현을 위한 UBM은, 제1 기판 및 제2 기판 상에 형성된 대응되는 적어도 하나 이상의 제1 및 제2 전극단자를 플립칩 본딩시 이용되는 미세 솔더볼 구현을 위한 UBM(Under Bump Metal)에 있어서, 상기 제1 전극단자 및 상기 솔더볼 사이에 배치되어 전기적으로 연결되며, 돌출부의 주변에 측면이 소정 경사를 이루는 함몰부를 구비하는 상기 제1 기판의 상기 돌출부에 형성되는 금속막 및 상기 돌출부에 접하는 상기 경사 측면 위에 형성된 금속막을 포함한다.
여기서 상기 돌출부에 형성되는 금속막과 상기 경사 측면에 형성되는 금속막 은 소정 간격으로 분리되는 것이 바람직하다.
그리고 본 발명에 의한 UBM은 상기 제2 전극단자와 연결되는 돌출부의 주변에 측면이 소정 경사를 이루는 함몰부를 구비하는 상기 제2 기판의 상기 돌출부에 형성되는 금속막 및 상기 돌출부에 접하는 상기 경사 측면 위에 금속막을 포함할 수 있다.
한편, 본 발명에 의한 미세 솔더볼 구현을 위한 UBM을 이용한 플립칩 패키지 방법은, 제1 기판의 적어도 하나 이상의 제1 영역 주변에 측면이 소정 경사를 이루는 함몰부가 형성되도록 상기 기판을 식각하는 단계; 상기 함몰부가 형성된 제1 기판 위에 제1 금속막을 형성하는 단계; 상기 제1 영역 및 상기 제1 영역에 접하는 경사면 이외에 형성된 제1 금속막을 제거하여 상기 제1 기판의 전극단자와 연결되는 제1 UBM을 형성하는 단계; 상기 제1 영역에 형성된 제1 UBM 위에 도전성의 솔더볼을 형성하는 단계; 상기 제1 영역에 대응하는 제2 기판의 제2 영역 위에 도전물질을 증착하여 상기 제2 기판의 전극단자와 연결되는 제2 UBM을 형성하는 단계; 및 상기 제1 UBM 및 상기 솔더볼이 형성된 상기 제1 기판과 상기 제2 UBM이 형성된 제2 기판을 접합하는 단계를 포함한다.
상기 솔더볼을 형성하는 단계는, 상기 제1 UBM이 형성된 제1 영역 이외의 영역에 포토레지스트막을 형성하는 단계; 상기 제1 UBM이 형성된 제1 영역에 제2 금속막을 형성하는 단계; 상기 포토레지스트층을 제거하는 단계; 및 상기 제2 금속막을 소정 온도로 가열하여 솔더볼을 형성하는 단계를 포함할 수 있다.
또한, 상기 솔더볼을 형성하는 단계는, 상기 제1 UBM이 형성된 제1 영역 위 에 소정온도의 솔더볼을 스포이딩하는 것으로 구현될 수 있다.
상기 제1 영역의 금속막과 상기 경사면의 금속막은 소정 간격으로 분리되는 것이 바람직하며, 제2 UBM은 상기 제1 UBM에 대응되는 패턴 구조로 형성될 수 있다.
이하에서 첨부한 도면을 참조하여 본 발명을 보다 상세히 설명한다.
도 2a 및 도 2b는 본 발명의 일실시예에 의한 UBM을 이용한 플립칩 패키지를 보이는 도면이다. 도 2a를 참조하면, 기판(100)과 반도체 칩 패드(200)를 플립칩 본딩으로 접합하는 경우 접합 매개체로서 솔더볼(133, 134)을 사용한다. 이때, 이들 접합이 잘 이루어지도록 하고 솔더볼(133, 134)의 퍼짐을 방지하기 위해 솔더볼(133, 134)과 접착되는 기판(100) 및 반도체 칩 패드(200) 사이에 UBM(111, 112, 211, 212)을 배치한다.
본 발명에 의한 UBM(111, 112, 211, 212)의 구조는 종래의 평면 패턴 구조의 문제점을 해결하고자 양각 패턴으로 구성한다. 기판(100) 상에 형성되는 UBM(111, 112, 211, 212)은 솔더볼(133, 134)이 배치될 돌출 부분의 제1 UBM(111b, 112b)과 함몰부의 경사면에 형성되는 제2 UBM(111a, 111c, 112a, 112c)으로 나뉜다. 그리고 제1 및 제2 UBM은 서로 소정간격 분리 형성하여 기판(100)과 반도체 칩 패드(200) 본딩시 상기 분리된 부분의 기판과 솔더볼(133a, 134a)이 접촉될 수 있도록 한다.
반도체 칩 패드(200) 에 형성되는 UBM(211, 212)은 제1 UBM(111b, 112b)에 대응되는 위치에 형성된다.
솔더볼(133, 134)을 소정온도로 유지한 상태에서 그 위에 반도체 칩 패드(200)를 올려 놓으면, 솔더볼(133, 134)은 힘을 받아 도 2b와 같은 형상으로 제2 UBM(111a, 111c, 112a, 112c)에 접촉하게 되고, 그 상태로 냉각되어 기판(100)과 반도체 칩 패드(200)를 접합하게 된다. 이와 같은 양각 패턴의 UBM(111, 112)은 솔더볼(133, 134) 본딩시에 솔더볼(133, 134)이 받게되는 힘을 측면에 형성된 제2 UBM(111a, 111c, 112a, 112c) 방향으로 분산 시킴으로서, 솔더볼(133, 134)의 퍼짐을 막을 수 있어 미세 솔더볼의 구현을 가능하게 한다. 또한 솔더볼(133, 134)의 재료가 주변 소자로 흘러 들어감을 막을 수 있어 패키지의 신뢰성을 높일 수 있다.
UBM(111, 112, 211, 212)은 Ni 또는 Ni-Cu로 구성되며, 그 두께는 0.5~10㎛이다. UBM(111, 112, 211, 212)는 그 하부에 Ti, Cr 또는 TiW로 이루어지고 그 두께가 0.5~10㎛인 접착층 및 Au, Pt, Pd 또는 Cu로 이루어지고 그 두께가 0.5~2㎛인 산화방지층을 포함할 수 있다.
도 3은 본 발명의 다른 일실시예에 의한 UBM을 이용한 플립칩 패키지를 보이는 도면이다. 여기에서는 기판(100)에 형성되는 UBM(111, 112) 뿐만아니라 반도체 칩 패드(200)에 형성되는 UBM(211, 212)도 양각 패턴 구조를 가지도록 구성한다.
여기에서는 기판에 반도체 칩 패드를 접합하는 것을 예를들어 설명하였으나, 본발명은 이에 한정하지 않고 그 밖의 다양한 마이크로 접합 공정에 적용할 수 있다.
도 4a 내지 도4i는 도 2b의 UBM을 이용한 플립칩 패키지의 단계별 공정을 나타내는 단면도이다.
먼저, 솔더 범프(131,132)가 형성될 패턴을 제작하고 그 패턴에 따라 기판(100)을 식각하는 공정이다. 도 4a에 식각공정 후의 기판(100)의 구조를 나타낸다. 습식 식각 또는 건식 식각을 이용하여, 솔더 범프(131, 132)가 형성될 영역의 주변을 소정 깊이(d3)로 식각하는데, 식각된 부분의 측면은 평면에 대해 대략 54.7도의 각을 이루도록 한다. 여기에서 d1은 솔더 범프(131,132)의 한 변의 길이이고, d2는 솔더 간의 피치 간격이며, d3은 기판(100)이 식각되는 깊이로 d1, d2, 솔더 범프(131, 132)의 구성 재료 등에 의해 결정된다.
다음 공정은 상기 기판(100) 위에 Ni 및 Cu로 이루어진 금속막을 0.5~10㎛의 두께로 증착하는 공정이다(도 4b).
다음은 솔더 범프(131,132)가 형성될 영역(111b, 112b)과 이 영역에 인접한 함몰영역의 경사면(111a, 111c, 112a, 112c)을 제외한 영역을 식각하여 UBM(111, 112)를 형성하는 공정이다(도 4c). 이때, 솔더 범프(131,132)가 형성될 영역(111b, 112b)과 이 영역에 인접한 함몰영역의 경사면(111a, 111c, 112a, 112c)의 경계부분도 식각하여 금속막을 제거하는 것이 바람직하다. 왜냐하면, 본딩시 솔더의 일부분이 기판에 흡착되도록 하기 위함이다.
다음은, 상기 기판(100) 위에 소정 두께로 포토레지스트막을 증착하고 노광에 의해 솔더 범프(131,132)가 배치될 영역 이외의 포토레지스트막은 제거하고 나머지 포토레지스트막(121, 122, 123)은 남겨 둔다(도 4d).
다음은, 솔더 범프를 증착한 후 포토레지스트막(121, 122, 123)을 제거하는 공정이다(도 4e, 도 4f). 솔더의 성분은 일반적으로 세라믹 기판의 경우에는 95%Pb-5%Sn(Tm=315도)을 사용하고 PCB등의 기판에서는 37%Pn-63%Sn(Tm=183도)을 사용한다. 이에 한정하지 않고, 다른 조성 비율의 Pb-Sn, Au-Sn, Ag-Cu 등을 사용할 수 있다. 그리고 솔더 범프(131, 132)의 크기는 솔더의 피치 간격 등에 의해 결정된다.
다음은, 솔더 범프(131,132)에 소정의 열을 가하는 리플로우(reflow) 공정으로 솔더볼(131a, 132a)을 형성하는 단계이다(도 4g). 솔더볼(131a, 132a)을 형성하는 공정은 상기한 바와 같이 도금한 후 열처리 하는 방법 뿐만아니라, 일반적으로 사용되는 솔더볼을 붙이는 방법을 사용할 수 있다.
마지막 공정으로 기판(100) 위에 반도체 칩 패드(200)을 접합 부분을 맞추어 본딩하는 단계이다(도 4i). 여기에서 본딩 전에 반도체 칩 패드(200)의 접속부위에 금속막으로 구성되는 UBM(211, 212)을 형성하는 공정을 거친다. 이때, 기판(100)과 반도체 칩 패드(200)에 의한 압력으로 솔더볼(131a, 132a)은 shear stress를 받아 함몰부의 측면에 형성된 UBM(111a, 111c, 112a, 112c)에 접착됨에 따라 좌우 방향으로 미치는 힘이 UBM(111a, 111c, 112a, 112c)가 형성된 측면으로 분산됨에 따라 솔더볼(131a, 132a)이 퍼지는 현상을 감소 시킬 수 있다.
상기한 바와 같이 본 발명에 의하면, 프립칩 패키지에 있어서 UBM를 양각 패턴 구조로 구성함으로서 미세 솔더볼 구현할 수 있을 뿐만아니라 패키지의 신뢰성을 높일 수 있다.
이상에서는 본 발명의 특정의 바람직한 실시예에 대하여 도시하고 설명하였다. 그러나, 본 발명은 상술한 실시예에 한정되지 아니하며, 특허청구의 범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변형 실시가 가능할 것이다.

Claims (8)

  1. 제1 기판 및 제2 기판 상에 형성된 대응되는 적어도 하나 이상의 제1 및 제2 전극단자를 플립칩 본딩시 이용되는 미세 솔더볼 구현을 위한 UBM(Under Bump Metal)에 있어서,
    상기 제1 전극단자 및 상기 솔더볼 사이에 배치되어 전기적으로 연결되며, 돌출부의 주변에 측면이 소정 경사를 이루는 함몰부를 구비하는 상기 제1 기판의 상기 돌출부에 형성되는 금속막; 및 상기 돌출부에 접하는 상기 경사 측면 위에 형성된 금속막;을 포함하는 것을 특징으로 하는 미세 솔더볼 구현을 위한 UBM.
  2. 제 1항에 있어서,
    상기 돌출부에 형성되는 금속막과 상기 경사 측면에 형성되는 금속막은 소정 간격으로 분리되는 것을 특징으로 하는 미세 솔더볼 구현을 위한 UBM.
  3. 제 2항에 있어서,
    상기 제2 전극단자와 연결되는 돌출부의 주변에 측면이 소정 경사를 이루는 함몰부를 구비하는 상기 제2 기판의 상기 돌출부에 형성되는 금속막; 및 상기 돌출부에 접하는 상기 경사 측면 위에 금속막;을 포함하는 것을 특징으로 하는 미세 솔더볼 구현을 위한 UBM.
  4. 제1 기판의 적어도 하나 이상의 제1 영역 주변에 측면이 소정 경사를 이루는 함몰부가 형성되도록 상기 기판을 식각하는 단계;
    상기 함몰부가 형성된 제1 기판 위에 제1 금속막을 형성하는 단계;
    상기 제1 영역 및 상기 제1 영역에 접하는 경사면 이외에 형성된 제1 금속막을 제거하여 상기 제1 기판의 전극단자와 연결되는 제1 UBM을 형성하는 단계;
    상기 제1 영역에 형성된 제1 UBM 위에 도전성의 솔더볼을 형성하는 단계;
    상기 제1 영역에 대응하는 제2 기판의 제2 영역 위에 도전물질을 증착하여 상기 제2 기판의 전극단자와 연결되는 제2 UBM을 형성하는 단계; 및
    상기 제1 UBM 및 상기 솔더볼이 형성된 상기 제1 기판과 상기 제2 UBM이 형성된 제2 기판을 접합하는 단계;를 포함하는 것을 특징으로 하는 미세 솔더볼 구현을 위한 UBM을 이용한 플립칩 패키지 방법.
  5. 제 4항에 있어서,
    상기 솔더볼을 형성하는 단계는,
    상기 제1 UBM이 형성된 제1 영역 이외의 영역에 포토레지스트막을 형성하는 단계;
    상기 제1 UBM이 형성된 제1 영역에 제2 금속막을 형성하는 단계;
    상기 포토레지스트층을 제거하는 단계; 및
    상기 제2 금속막을 소정 온도로 가열하여 솔더볼을 형성하는 단계;를 포함하는 것을 특징으로 하는 미세 솔더볼 구현을 위한 UBM을 이용한 플립칩 패키지 방법.
  6. 제 4항에 있어서,
    상기 솔더볼을 형성하는 단계는,
    상기 제1 UBM이 형성된 제1 영역 위에 소정온도의 솔더볼을 스포이딩하는 것을 특징으로 하는 미세 솔더볼 구현을 위한 UBM을 이용한 플립칩 패키지 방법.
  7. 제 4항에 있어서,
    상기 제1 영역의 금속막과 상기 경사면의 금속막은 소정 간격으로 분리되는 것을 특징으로 하는 미세 솔더볼 구현을 위한 UBM을 이용한 플립칩 패키지 방법.
  8. 제 7항에 있어서,
    제2 UBM은 상기 제1 UBM에 대응되는 패턴 구조로 형성되는 것을 특징으로 하는 미세 솔더볼 구현을 위한 UBM을 이용한 플립칩 패키지 방법.
KR1020030093209A 2003-12-18 2003-12-18 미세 솔더볼 구현을 위한 ｕｂｍ 및 이를 이용한 플립칩패키지 방법 KR100555706B1 (ko)

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EP04029916A EP1544916A1 (en) 2003-12-18 2004-12-16 Raised solder pad and method using the same
US11/012,294 US7309924B2 (en) 2003-12-18 2004-12-16 UBM for fine pitch solder ball and flip-chip packaging method using the same
JP2004367236A JP4105150B2 (ja) 2003-12-18 2004-12-20 微細ソルダ・ボール具現のためのｕｂｍ及びこれを利用したフリップチップ・パッケージ方法

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EP1544916A1 (en) 2005-06-22
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US20050151269A1 (en) 2005-07-14
JP4105150B2 (ja) 2008-06-25
JP2005183992A (ja) 2005-07-07

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