CN103904024A - 形成半导体器件的双镶嵌结构的方法以及由其制造的半导体器件 - Google Patents

形成半导体器件的双镶嵌结构的方法以及由其制造的半导体器件 Download PDF

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CN103904024A
CN103904024A CN201310516715.8A CN201310516715A CN103904024A CN 103904024 A CN103904024 A CN 103904024A CN 201310516715 A CN201310516715 A CN 201310516715A CN 103904024 A CN103904024 A CN 103904024A
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文俊怜
赵娟振
李圣宰
朴惟廷
尹龙云
李哲虎
李忠宪
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Cheil Industries Inc
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Abstract

本发明公开了形成半导体器件的双镶嵌结构的方法以及由其制造的半导体器件。该方法包括:(a)在衬底上形成第一和第二绝缘层;(b)形成具有在第二绝缘层上形成通孔的图案的抗蚀剂掩模;(c)形成向下至第一绝缘层下端的通孔;(d)以旋涂法在通孔中和第二绝缘层上形成硬掩模层;(e)形成具有在硬掩模层上形成槽孔的图案的抗蚀剂掩模;(f)形成通过抗蚀剂掩模向下深入到第二绝缘层下端的第一槽孔;(g)去除通孔中和第二绝缘层上的硬掩模层的一部分;(h)通过去除通孔的顶角和第一槽孔的底角之间的第二绝缘层的一部分形成第二槽孔;(i)去除保留在通孔中和第二绝缘层上的硬掩模层;(j)通过用导电材料填充通孔和第二槽孔形成上部导线。

Description

形成半导体器件的双镶嵌结构的方法以及由其制造的半导体器件
相关申请的引用
本申请要求于2012年12月26日提交于韩国知识产权局的韩国专利申请号10-2012-0153753的优先权和权益,其全部内容包括在此以供参考。
技术领域
在制造半导体器件的方法中,本发明公开了为铜线形成双镶嵌结构的方法。
背景技术
随着出现对半导体器件整合的需求,采用铜(Cu)线工艺替代传统的铝(Al)线工艺,以及采用使用低介电常数(低k)材料层替代传统氧化层作为绝缘层的双镶嵌工艺来提高半导体器件的特性,例如运行速度、电阻等等。
双镶嵌工艺被划分为首先蚀刻通孔(via hole)然后形成槽孔(trenchhole)的先通孔双镶嵌工艺(via-first dual damascene)(VFDD)以及首先蚀刻槽孔然后形成通孔的先槽孔双镶嵌工艺(trench-first dual damascene)(TFDD)。当在蚀刻通孔然后用硬掩模组合物填充之后蚀刻槽孔时,通过调节通孔顶角(via top corner)和槽孔底角(trench bottom corner)之间的角度,先通孔双镶嵌工艺对形成导线的后续工艺中提高效率具有重要影响。
发明内容
本发明的一个实施方式提供了通过旋转涂布硬掩模组合物来形成半导体器件的双镶嵌结构的方法,从而易于控制通孔顶角和槽孔底角之间的剖面。
另一个实施方式提供了根据形成双镶嵌结构的方法制造的半导体器件。
根据一个实施方式,提供了形成半导体器件的双镶嵌结构的方法,包括:(a)依次在衬底上形成第一绝缘层和第二绝缘层;(b)形成具有用于在第二绝缘层上形成通孔的图案的抗蚀剂掩模;(c)形成向下至第一绝缘层下端的通孔:(d)以旋转涂布法在通孔中和第二绝缘层上形成硬掩模层;(e)形成具有用于在硬掩模层上形成槽孔的图案的抗蚀剂掩模;(f)形成通过抗蚀剂掩模向下至第二绝缘层下端的第一槽孔;(g)分别去除通孔中和第二绝缘层上的硬掩模层的一部分;(h)通过去除通孔的顶角(top corner)和第一槽孔的底角(bottom corner)之间的第二绝缘层的一部分来形成第二槽孔;(i)去除保留在通孔中和第二绝缘层上的硬掩模层;以及(j)通过用导电材料填充通孔和槽孔来形成上部导线。
第二槽孔的下端可以具有弯曲形状。
硬掩模层的形成(d)可以包括在约200℃至约500℃下的热处理。
另外,在抗蚀剂掩模的形成(e)之前,可以进一步在硬掩模层上形成包含硅的辅助层。
另外,在硬掩模层的形成(d)之前,可形成底部抗反射涂层(BARC)。
在(d)中,硬掩模层可以具有约至约
Figure BDA0000403504480000022
的厚度。
在(f)中,当深度总和为100%时,第一槽孔可以具有第一绝缘层和第二绝缘层的深度总和约40%至约80%的深度。
在(g)中,保留在通孔中和第二绝缘层上的硬掩模层可以分别具有约
Figure BDA0000403504480000031
至约
Figure BDA0000403504480000032
的高度以及约至约
Figure BDA0000403504480000034
的高度。
根据另一个实施方式,提供了以形成双镶嵌结构的方法制造的包含多种图案的半导体器件。
本发明通过以旋转涂布法使用硬掩模组合物设计出了通孔顶角和槽孔底角的结构,这对于后续工艺是有利的。
附图说明
图1示出流程图,说明根据本发明的一个实施方式形成半导体器件的双镶嵌结构的方法。
具体实施方式
下面参考附图更全面地描述本公开,其中示出本公开的示例性实施方式。然而,本公开能够以多种不同形式实施,而不应认为限于在此给出的示例性实施方式。
应该理解的是,当元件,例如层、膜、区域或者衬底被提到“在”其他元件“上”时,它可以直接在其他元件上或者还可以存在插入元件。相反,当元件被提到“直接在”其他元件“上”时,则不存在插入元件。
在下文中,参考图1示出根据本发明的一个实施方式形成半导体器件的双镶嵌结构的方法。
图1是流程图,说明了根据本发明的一个实施方式形成半导体器件的双镶嵌结构的方法。
根据形成半导体器件的双镶嵌结构的方法,第一绝缘层3和第二绝缘层7依次形成于衬底1上。
衬底1具有金属线(未示出)或者下部结构,如半导体器件等等。另外,可在第一绝缘层3和衬底1之间形成蚀刻终止层(未示出)。
第一绝缘层3和第二绝缘层7可由在半导体器件的双镶嵌工艺中使用的传统绝缘材料形成,例如TEOS(原硅酸四乙酯)。
接着,在第二绝缘层7上形成具有用于形成通孔的图案的抗蚀剂掩模10。抗蚀剂掩模10可用化学气相沉积法或者旋转涂布法形成。
然后,利用抗蚀剂掩模10的图案来蚀刻通孔(V)。
在此,深入向下至第一绝缘层3的下端形成通孔(V)。当通孔(V)完成时,去除第二绝缘层7上的抗蚀剂掩模10。
然后,在通孔(V)中和第二绝缘层7上形成硬掩模层20。硬掩模层20作为通过选择性蚀刻工艺将抗蚀剂掩模10的精细图案传递给材料层的中间层(interlayer)起作用。
以旋转涂布法形成硬掩模层20。
以旋转涂布法形成的硬掩模层20比以化学气相沉积法形成的硬掩模层具有好得多的间隙填充(gap-filling)特性。因此,尽管随着半导体图案变得更精细,图案的纵横比增加,以旋转涂布法形成的硬掩模层20可填充通孔而没有空隙。以旋转涂布法形成的硬掩模层20使得有能够设计器件的不同结构,并且因此与以化学气相沉积法形成的硬掩模层相比,改善了器件可靠性。
通过在通孔(V)中和第二绝缘层7上涂布硬掩模组合物,形成硬掩模层20从而在第二绝缘层7上具有预定的高度。
硬掩模层20可以具有约
Figure BDA0000403504480000051
至约
Figure BDA0000403504480000052
的厚度。在此,参考第二绝缘层7的上端来测量硬掩模层20的厚度。当硬掩模层20具有所述范围内的厚度时,其可易于传输图案并且同时保证足够的耐蚀刻性。
硬掩模层20的形成可进一步包括在约200℃至约500℃下的热处理。热处理可在该范围内的约350℃至约400℃的范围内进行。在该温度范围内的热处理可保证硬掩模组合物的充分交联和间隙填充特性,并且提高后续槽孔形成工艺的效率。该热处理可在空气中或者在氮气氛下进行。
在形成硬掩模层20之前,可进一步形成底部抗反射涂层(BARC)(未示出)。
可在硬掩模层20上形成包含硅的辅助层(未示出)。该辅助层连同硬掩模层20一起可起到提供耐蚀刻性的作用。
下一步,具有用于形成槽孔的图案的抗蚀剂掩模30在硬掩模层20上形成,然后用于形成第一槽孔T1。深入向下至第二绝缘层7的下端形成第一槽孔T1。当第一槽孔T1完成时,去除抗蚀剂掩模30。
当深度总和为100%时,第一槽孔T1可以被图案化以具有第一绝缘层3和第二绝缘层7的深度总和的约40%至80%的深度。例如当使用TEOS9K作为沉积材料时,第一槽孔T1可具有约
Figure BDA0000403504480000053
Figure BDA0000403504480000054
的深度。当第一槽孔T1具有所述范围内的深度时,可保证在后续工艺中调节通孔顶角和槽孔底角结构的余量(裕度,margin)。在干法蚀刻均化过程中,该余量可形成负载/微负载(loading/micro-loading)的精细图案和较宽图案之间的蚀刻速率差异。
然后,在通孔(V)中和第二绝缘层7上形成的硬掩模层20被部分地去除。在部分去除硬掩模层20后,保留在通孔(V)中和第二绝缘层7上的硬掩模层20分别具有约
Figure BDA0000403504480000061
至约
Figure BDA0000403504480000062
的高度以及约至约
Figure BDA0000403504480000064
的高度。参照作为沉积材料的TEOS9K,获得保留的硬掩模层20的高度。
然后,在通孔(V)中的硬掩模层20被去除且保持在所述范围内,使得可以容易地设计通孔顶角和槽孔底角的结构,以形成精细图案。
另外,在第二绝缘层7上的硬掩模层20被去除并保持在所述范围内,使得在形成第二槽孔T2的后续工艺中保留的硬掩模层20可作为耐蚀刻层起作用。
在此,在通孔(V)中和第二绝缘层7上的硬掩模层20的部分去除可在以下条件下进行:腔室压力在约5毫托至约10毫托的范围内;高频(60M)RF电功率在约100W至约500W的范围内;低频(2M)RF电功率在约1000W至约2000W的范围内;且氧气流速在约20SCCM至约50SCCM的范围内,持续约5秒至约10秒。
在部分去除通孔(V)中和第二绝缘层7上的硬掩模层20后,通过部分去除通孔的顶角(V)(通孔顶角)和第一槽孔T1的底角(槽孔底角)之间的第一绝缘层3来形成第二槽孔T2。
在此,第二槽孔T2的下端可以具有弯曲形状。换句话说,在半导体图案的横切面上,通孔(V)的通孔顶角和第一槽孔T1的槽孔底角以曲线连接。当第二槽孔T2的下端平滑弯曲时,沉积导电材料的后续工艺的效率被提高。
当第二槽孔T2形成时,去除通孔(V)中和第二绝缘层7上保留的硬掩模层20。去除保留在通孔(V)中的硬掩模层20还可以包括去除暴露在通孔(V)下端的蚀刻终止层(未示出)。
然后,用导电材料填充通孔(V)和第二槽孔T2,从而形成上部导线。导电材料可以是铜(Cu)。填充可用沉积法进行。
根据本发明的另一实施方式,还提供了包括以形成双镶嵌结构的方法制造多种图案的半导体器件。
虽然与目前认为是实用的示例性实施方式的那些相结合描述了本发明,应当理解的是本发明不限于所公开的实施方式,而是相反地,旨在涵盖包括在所附权利要求的精神和保护范围内的各种修改和等效安排。
<符号说明>
1:衬底                         3:第一绝缘层
7:第二绝缘层                   10、30:抗蚀剂掩模
20:硬掩模层                    V:通孔
T1:第一槽孔                    T2:第二槽孔。

Claims (9)

1.一种形成半导体器件的双镶嵌结构的方法,包括:
(a)在衬底上依次形成第一绝缘层和第二绝缘层;
(b)形成具有用于在所述第二绝缘层上形成通孔的图案的抗蚀剂掩模;
(c)形成向下至所述第一绝缘层下端的通孔;
(d)以旋转涂布法在所述通孔中和所述第二绝缘层上形成硬掩模层;
(e)形成具有用于在所述硬掩模层上形成槽孔的图案的抗蚀剂掩模;
(f)形成通过所述抗蚀剂掩模向下深入到所述第二绝缘层下端的第一槽孔;
(g)分别去除所述通孔中和所述第二绝缘层上的所述硬掩模层的一部分;
(h)通过去除在所述通孔的顶角,即通孔顶角,和所述第一槽孔的底角,即槽孔底角,之间的所述第二绝缘层的一部分来形成第二槽孔;
(i)去除保留在所述通孔中和所述第二绝缘层上的所述硬掩模层;以及
(j)通过用导电材料填充所述通孔和所述第二槽孔来形成上部导线。
2.根据权利要求1所述的方法,其中所述第二槽孔具有弯曲形状。
3.根据权利要求1所述的方法,其中所述硬掩模层的形成(d)包括在温度为200℃至500℃下的热处理。
4.根据权利要求1所述的方法,其中在所述抗蚀剂掩模的形成(e)之前,在所述硬掩模层上形成包含硅的辅助层。
5.根据权利要求1所述的方法,还包括在所述硬掩模层的形成(d)之前形成底部抗反射涂层(BARC)。
6.根据权利要求1所述的方法,其中在所述硬掩模层的形成(d)过程中,所述硬掩模层的厚度为
Figure FDA0000403504470000022
7.根据权利要求1所述的方法,其中在(f)中形成的所述第一槽孔具有基于100%的所述第一绝缘层和所述第二绝缘层的深度总和40%至80%的深度。
8.根据权利要求1所述的方法,其中在去除(g)中的所述硬掩模层的一部分后,保留在所述通孔中和所述第二绝缘层上的所述硬掩模层分别为
Figure FDA0000403504470000023
Figure FDA0000403504470000024
以及
Figure FDA0000403504470000025
Figure FDA0000403504470000026
的厚度。
9.一种包括多个图案的半导体器件,所述半导体器件是根据权利要求1-8任一项所述的形成半导体器件的双镶嵌结构的方法制造的。
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