KR100909177B1 - 듀얼 다마신 패턴 형성 방법 - Google Patents
듀얼 다마신 패턴 형성 방법 Download PDFInfo
- Publication number
- KR100909177B1 KR100909177B1 KR1020020085479A KR20020085479A KR100909177B1 KR 100909177 B1 KR100909177 B1 KR 100909177B1 KR 1020020085479 A KR1020020085479 A KR 1020020085479A KR 20020085479 A KR20020085479 A KR 20020085479A KR 100909177 B1 KR100909177 B1 KR 100909177B1
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- South Korea
- Prior art keywords
- via hole
- interlayer insulating
- trench
- photoresist pattern
- forming
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Abstract
Description
Claims (5)
- 배선이 형성된 기판 상에 확산 방지막, 층간 절연막 및 캡핑층을 형성하고, 상기 캡핑층 상에 비아홀용 포토레지스트 패턴을 형성하는 단계;상기 비아홀용 포토레지스트 패턴을 이용한 식각 공정으로 상기 캡핑층, 상기 층간 절연막 및 상기 확산 방지막을 식각하여 상기 배선이 노출된 비아홀을 형성하는 단계;상기 비아홀용 포토레지스트 패턴을 제거하는 단계;상기 비아홀을 광흡수막으로 매립하는 단계;상기 광흡수막 상에 트렌치용 포토레지스트 패턴을 형성한 후, 상기 광흡수막, 상기 층간 절연막 및 상기 캡핑층을 일정 깊이 식각하여 트렌치를 형성하는 단계;상기 트렌치용 포토레지스트 패턴을 제거하는 단계; 및상기 비아홀에 남아있는 상기 광흡수막을 제거하는 단계를 포함하고,상기 광흡수막은 상기 층간 절연막과 식각 선택비가 유사한 실록산 계열의 물질이며,상기 트렌치를 형성하는 단계는 C4F8 가스, O2 가스, N2 가스 및 Ar 가스를 활성화시킨 플라즈마를 이용한 상기 층간 절연막과 상기 광흡수막의 비선택적 식각으로 수행되는 것을 특징으로 하는 듀얼 다마신 패턴 형성 방법.
- 제 1 항에 있어서,상기 비아홀용 포토레지스트 패턴은 H2/N2 가스를 이용하여 제거하는 것을 특 징으로 하는 듀얼 다마신 패턴 형성 방법.
- 삭제
- 삭제
- 제 1 항에 있어서,상기 남아있는 광흡수막은 희석된 HF 용액으로 제거하는 것을 특징으로 하는 듀얼 다마신 패턴 형성 방법.
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Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020085479A KR100909177B1 (ko) | 2002-12-27 | 2002-12-27 | 듀얼 다마신 패턴 형성 방법 |
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KR1020020085479A KR100909177B1 (ko) | 2002-12-27 | 2002-12-27 | 듀얼 다마신 패턴 형성 방법 |
Publications (2)
Publication Number | Publication Date |
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KR20040058959A KR20040058959A (ko) | 2004-07-05 |
KR100909177B1 true KR100909177B1 (ko) | 2009-07-22 |
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KR1020020085479A KR100909177B1 (ko) | 2002-12-27 | 2002-12-27 | 듀얼 다마신 패턴 형성 방법 |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20060065184A (ko) * | 2004-12-10 | 2006-06-14 | 매그나칩 반도체 유한회사 | 반도체 소자의 금속 배선 형성 방법 |
KR100652303B1 (ko) * | 2004-12-29 | 2006-11-30 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 배선 형성 방법 |
KR100691105B1 (ko) * | 2005-09-28 | 2007-03-09 | 동부일렉트로닉스 주식회사 | 듀얼 다마신 공정을 이용한 구리 배선 형성 방법 |
KR20140083696A (ko) * | 2012-12-26 | 2014-07-04 | 제일모직주식회사 | 반도체 소자의 듀얼 다마신 구조 형성 방법 및 그에 따른 반도체 소자 디바이스 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6323123B1 (en) * | 2000-09-06 | 2001-11-27 | United Microelectronics Corp. | Low-K dual damascene integration process |
KR20020052479A (ko) * | 2000-12-26 | 2002-07-04 | 박종섭 | 반도체소자의 캐패시터 형성방법 |
KR20020058288A (ko) * | 2000-12-29 | 2002-07-12 | 박종섭 | 반도체소자의 제조방법 |
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- 2002-12-27 KR KR1020020085479A patent/KR100909177B1/ko active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6323123B1 (en) * | 2000-09-06 | 2001-11-27 | United Microelectronics Corp. | Low-K dual damascene integration process |
KR20020052479A (ko) * | 2000-12-26 | 2002-07-04 | 박종섭 | 반도체소자의 캐패시터 형성방법 |
KR20020058288A (ko) * | 2000-12-29 | 2002-07-12 | 박종섭 | 반도체소자의 제조방법 |
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