US8900997B2 - Method for forming a dual damascene structure of a semiconductor device, and a semiconductor device therewith - Google Patents

Method for forming a dual damascene structure of a semiconductor device, and a semiconductor device therewith Download PDF

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US8900997B2
US8900997B2 US14/072,881 US201314072881A US8900997B2 US 8900997 B2 US8900997 B2 US 8900997B2 US 201314072881 A US201314072881 A US 201314072881A US 8900997 B2 US8900997 B2 US 8900997B2
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forming
layer
insulation layer
via hole
hole
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US20140175669A1 (en
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Joon-Young MOON
Youn-Jin Cho
Sung-Jae Lee
You-Jung PARK
Yong-Woon YOON
Chul-ho Lee
Chung-Heon Lee
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Cheil Industries Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Korean Patent Application No. 10-2012-0153753 filed on Dec. 26, 2012, in the Korean Intellectual Property Office, and entitled: “A Method for Forming a Dual Damascene Structure of a Semiconductor Device, and a Semiconductor Device Therewith,” is incorporated by reference herein in its entirety.
  • Embodiments relate to a method for forming a dual damascene structure of a semiconductor device, and a semiconductor device therewith.
  • a copper (Cu) wire process may be used instead of an aluminum (Al) wire process
  • a low dielectric constant (low k) material layer may be used instead of an oxidation layer as an insulating layer.
  • Embodiments are directed to a method of forming a dual damascene structure of a semiconductor device, the method including sequentially forming a first insulation layer and a second insulation layer on a substrate, forming a resist mask having a pattern for forming a via hole on the second insulation layer, forming a via hole down to a lower end of the first insulation layer, forming a hardmask layer in the via hole and on the second insulation layer using a spin-coating method, forming a resist mask having a pattern for forming a trench hole on the hardmask layer, forming a first trench hole through the resist mask having the pattern for forming the trench hole, the first trench hole being formed down to a lower end of the second insulation layer, respectively removing a part of the hardmask layer in the via hole and a part of the hardmask layer on the second insulation layer, forming a second trench hole by removing a part of the first insulation layer between a top corner of the hardmask layer remaining in the via hole and a bottom corner of the first
  • the second trench hole may have a curved shape in cross-section.
  • Forming the hardmask layer may include performing a heat treatment at a temperature ranging from about 200° C. to about 500° C.
  • the method may further include forming an auxiliary layer including silicon on the hardmask layer before the forming of the resist mask having the pattern for forming the trench hole.
  • the method may further include forming a bottom antireflective coating before the forming of the hardmask layer.
  • the hardmask layer may be formed to be about 2000 ⁇ to about 3800 ⁇ thick, measured with reference to the upper end of the second insulation layer.
  • the first trench hole may be formed to have a depth of about 40% to about 80% of a combined thickness the first insulation layer and the second insulation layer.
  • the hardmask layer remaining in the via hole and the hard mask layer remaining on the second insulation layer may be respectively about 9500 ⁇ to about 10,000 ⁇ and about 500 ⁇ to about 1000 ⁇ thick.
  • Embodiments are also directed to a semiconductor device including a plurality of patterns, which is fabricated according to the method as claimed in claim 1 .
  • FIG. 1 illustrates stages in a method of forming a dual damascene structure of a semiconductor device according to an example embodiment.
  • FIG. 1 a method of forming a dual damascene structure of a semiconductor device according to an embodiment is illustrated referring to FIG. 1 .
  • FIG. 1 illustrates stages in a method of forming a dual damascene structure of a semiconductor device according to an example embodiment.
  • a first insulation layer 3 and a second insulation layer 7 are sequentially formed on a substrate 1 .
  • the substrate 1 may have a metal wire (not shown) or lower structure, e.g. a semiconductor device and the like.
  • an etch-stop layer (not shown) may be formed between the first insulation layer 3 and the substrate 1 .
  • the first insulation layer 3 and the second insulation layer 7 may be formed of a general insulating material used in the dual damascene process for a semiconductor device, e.g., TEOS (tetraethyl orthosilicate).
  • TEOS tetraethyl orthosilicate
  • a resist mask 10 having a pattern for forming a via hole is formed on the second insulation layer 7 .
  • the resist mask 10 may be formed using, e.g., a chemical vapor deposition or spin-coating method.
  • a via hole (V) is etched using the pattern of the resist mask 10 .
  • the via hole (V) is formed down to the lower end of the first insulation layer 3 , e.g., the via hole (V) is formed through the second insulation layer 7 and the first insulation layer 3 so as to expose the substrate 1 .
  • the resist mask 10 on the second insulation layer 7 may be removed.
  • a hardmask layer 20 is formed in the via hole (V) and on the second insulation layer 7 .
  • the hardmask layer 20 may fill the via hole (V) and cover the second insulation layer 7 adjacent to the via hole (V).
  • the hardmask layer 20 works as an interlayer transmitting the fine pattern of the resist to the material layer through a selective etching process.
  • the hardmask layer 20 is formed using a spin-coating method.
  • the hardmask layer 20 formed using the spin-coating method may provide an excellent gap-filling characteristic, and may provide a better gap-filling characteristic than a hardmask layer formed using a chemical vapor deposition method. Accordingly, the hardmask layer 20 formed using the spin-coating method may fill the via hole without a void despite increases in the aspect ratio of the pattern as the pattern becomes finer.
  • the hardmask layer 20 formed using the spin-coating method may make it possible to design various structures of a device and improve reliability of the device compared with the hardmask layer formed in the chemical vapor deposition method.
  • the hardmask layer 20 is formed to have a predetermined height on the second insulation layer 7 by coating a hardmask composition in the via hole (V) and on the second insulation layer 7 .
  • the hardmask layer 20 may be about 2000 ⁇ to about 3800 ⁇ thick.
  • the thickness of the hardmask layer 20 is measured with reference to the upperend of the second insulation layer 7 .
  • the formation of the hardmask layer 20 may further include a heat-treatment at about 200° C. to about 500° C.
  • the heat treatment may be performed in a range of about 350° C. to about 400° C.
  • the heat treatment within the temperature range may secure sufficient cross-linking and gap-filling characteristics of the hardmask composition, and improve efficiency in a subsequent trench formation process.
  • the heat treatment may be performed in the air or under a nitrogen atmosphere.
  • a bottom antireflective coating (BARC) layer (not shown) may be further formed.
  • An auxiliary layer (not shown) including silicon may be formed on the hardmask layer 20 .
  • the auxiliary layer along with the hardmask layer 20 may play a role of providing etching resistance.
  • a resist mask 30 having a pattern for forming a trench hole is formed on the hardmask layer 20 .
  • the resist mask 30 is used to form a first trench hole T 1 .
  • the first trench hole T 1 is formed down to the lower end of the second insulation layer 7 .
  • the resist mask 30 is removed.
  • the first trench hole T 1 may be patterned to have a depth of about 40% to 80% of the thickness sum of the first insulation layer 3 and the second insulation layer 7 when the thickness sum is 100%.
  • the first trench hole T 1 may be about 3200 ⁇ to 7200 ⁇ deep when TEOS 9K, for example, is used as a deposition material.
  • a margin regulating a structure of a via top corner and a trench bottom corner in a subsequent process may be secured.
  • the margin may make an etching rate difference between a fine pattern of loading/micro-loading and a wide pattern during dry etching uniform.
  • the hardmask layer 20 formed in the via hole (V) and on the second insulation layer 7 is partially removed.
  • portions of the hardmask layer 20 remaining in the via hole (V) and on the second insulation layer 7 after partially removing the hardmask layer 20 are respectively about 9500 ⁇ to about 10,000 ⁇ thick and about 500 ⁇ to about 1000 ⁇ thick.
  • the thickness of the remaining hardmask layer 20 is obtained with reference to TEOS 9K as a deposition material.
  • the hardmask layer 20 in the via hole (V) is partially removed and left within the range, so that the structure of a via top corner and a trench bottom corner may be easily designed, forming a fine pattern.
  • the hardmask layer 20 on the second insulation layer 7 is partially removed and left within the range, so that the remaining hardmask layer 20 may work as an etch resistance layer in a subsequent process of forming a second trench hole T 2 .
  • the partial removal of the hardmask layer 20 in the via hole (V) and the second insulation layer 7 may be performed under a chamber pressure ranging from about 5 mTorr to about 10 mTorr, a high frequency (60 M) RF electric power ranging from about 100 W to about 500 W, a low frequency (2 M) RF electric power ranging from about 1000 W to about 2000 W, and an O 2 gas flow rate ranging from about 20 SCCM to about 50 SCCM for about 5 seconds to about 10 seconds.
  • a chamber pressure ranging from about 5 mTorr to about 10 mTorr
  • a high frequency (60 M) RF electric power ranging from about 100 W to about 500 W
  • a low frequency (2 M) RF electric power ranging from about 1000 W to about 2000 W
  • an O 2 gas flow rate ranging from about 20 SCCM to about 50 SCCM for about 5 seconds to about 10 seconds.
  • the second trench hole T 2 is formed by partially removing the first insulation layer 3 between the top corner of the via hole (V) (via top corner) and the bottom corner of the first trench hole T 1 (trench bottom corner).
  • the lower end of the second trench hole T 2 may have a curved shape.
  • the via top corner of the via hole (V) and the trench bottom corner of the first trench hole T 1 may be connected with a curved line in the cross-section of a semiconductor pattern.
  • efficiency in a subsequent process of depositing a conductive material may be increased.
  • the hardmask layer 20 remaining in the via hole (V) and on the second insulation layer 7 is removed.
  • the removal of the hardmask layer 20 remaining in the via hole (V) may also include removing an etch-stop layer (not shown) exposed at the lower end of the via hole (V).
  • the via hole (V) and the second trench hole T 2 are filled with a conductive material to form an upper wire.
  • the conductive material may be, e.g., copper (Cu).
  • the filling may be performed with a deposition method.
  • a semiconductor device including a plurality of patterns fabricated in the method of forming a dual damascene structure is provided.
  • the dual damascene process may be classified as a via-first dual damascene (VFDD) process of first etching a via hole and then forming a trench hole, and a trench-first dual damascene (TFDD) process of first etching a trench hole and then forming a via hole.
  • the via-first dual damascene process may contribute to increasing efficiency in a subsequent process of forming a wire by regulating an angle between a via top corner and a trench bottom corner, when the trench hole is etched after etching the via hole, and then charging it with a hardmask composition.
  • example embodiments may provide a method of manufacturing a semiconductor device, and a method of forming a dual damascene structure for a copper wire.
  • An example embodiment may provide a method of forming a dual damascene structure of a semiconductor device by spin-coating a hardmask composition to help control a profile between a via top corner and a trench bottom corner.
  • Another example embodiment may provide a semiconductor device fabricated according to the method of forming a dual damascene structure.
  • An example embodiment may provide a structure of a via top corner and a trench bottom corner, which is advantageous for a subsequent process, by applying a hardmask composition in a spin-coating method.

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Abstract

Forming a dual damascene structure includes forming a first insulation layer and a second insulation layer, forming a resist mask, forming a via hole down to a lower end of the first insulation layer, forming a hardmask layer in the via hole and on the second insulation layer using a spin-coating method, forming a resist mask, forming a first trench hole down to a lower end of the second insulation layer, respectively removing a part of the hardmask layer in the via hole and a part of the hardmask layer on the second insulation layer, forming a second trench hole by removing a part of the first insulation layer between a top corner of the hardmask layer remaining in the via hole and a bottom corner of the first trench hole, removing the hardmask layer, and filling the via hole and the second trench hole with a conductive material.

Description

CROSS-REFERENCE TO RELATED APPLICATION
Korean Patent Application No. 10-2012-0153753, filed on Dec. 26, 2012, in the Korean Intellectual Property Office, and entitled: “A Method for Forming a Dual Damascene Structure of a Semiconductor Device, and a Semiconductor Device Therewith,” is incorporated by reference herein in its entirety.
BACKGROUND
1. Field
Embodiments relate to a method for forming a dual damascene structure of a semiconductor device, and a semiconductor device therewith.
2. Description of the Related Art
As demand for integration of semiconductor devices has increased, characteristics of the semiconductor device, such as operation speed, resistance, and the like have been improved. For example, a copper (Cu) wire process may be used instead of an aluminum (Al) wire process, and a low dielectric constant (low k) material layer may be used instead of an oxidation layer as an insulating layer.
SUMMARY
Embodiments are directed to a method of forming a dual damascene structure of a semiconductor device, the method including sequentially forming a first insulation layer and a second insulation layer on a substrate, forming a resist mask having a pattern for forming a via hole on the second insulation layer, forming a via hole down to a lower end of the first insulation layer, forming a hardmask layer in the via hole and on the second insulation layer using a spin-coating method, forming a resist mask having a pattern for forming a trench hole on the hardmask layer, forming a first trench hole through the resist mask having the pattern for forming the trench hole, the first trench hole being formed down to a lower end of the second insulation layer, respectively removing a part of the hardmask layer in the via hole and a part of the hardmask layer on the second insulation layer, forming a second trench hole by removing a part of the first insulation layer between a top corner of the hardmask layer remaining in the via hole and a bottom corner of the first trench hole, removing the hardmask layer remaining in the via hole and on the second insulation layer, and forming an upper wire by filling the via hole and the second trench hole with a conductive material.
The second trench hole may have a curved shape in cross-section.
Forming the hardmask layer may include performing a heat treatment at a temperature ranging from about 200° C. to about 500° C.
The method may further include forming an auxiliary layer including silicon on the hardmask layer before the forming of the resist mask having the pattern for forming the trench hole.
The method may further include forming a bottom antireflective coating before the forming of the hardmask layer.
In the forming of the hardmask layer, the hardmask layer may be formed to be about 2000 Å to about 3800 Å thick, measured with reference to the upper end of the second insulation layer.
The first trench hole may be formed to have a depth of about 40% to about 80% of a combined thickness the first insulation layer and the second insulation layer.
After respectively removing the part of the hardmask layer in the via hole and the part of the hardmask layer on the second insulation layer, the hardmask layer remaining in the via hole and the hard mask layer remaining on the second insulation layer may be respectively about 9500 Å to about 10,000 Å and about 500 Å to about 1000 Å thick.
Embodiments are also directed to a semiconductor device including a plurality of patterns, which is fabricated according to the method as claimed in claim 1.
BRIEF DESCRIPTION OF THE DRAWING
Features will become apparent to those of skill in the art by describing in detail example embodiments with reference to the attached drawing, in which:
FIG. 1 illustrates stages in a method of forming a dual damascene structure of a semiconductor device according to an example embodiment.
 DETAILED DESCRIPTION
Example embodiments will now be described more fully hereinafter with reference to the accompanying drawing; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art. In the drawing FIGURE, the dimensions of layers and regions may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
Hereinafter, a method of forming a dual damascene structure of a semiconductor device according to an embodiment is illustrated referring to FIG. 1.
FIG. 1 illustrates stages in a method of forming a dual damascene structure of a semiconductor device according to an example embodiment.
Referring to illustration 1 a in FIG. 1, according to the present example embodiment, a first insulation layer 3 and a second insulation layer 7 are sequentially formed on a substrate 1.
The substrate 1 may have a metal wire (not shown) or lower structure, e.g. a semiconductor device and the like. In addition, an etch-stop layer (not shown) may be formed between the first insulation layer 3 and the substrate 1.
The first insulation layer 3 and the second insulation layer 7 may be formed of a general insulating material used in the dual damascene process for a semiconductor device, e.g., TEOS (tetraethyl orthosilicate).
Next, referring to illustration 1 b in FIG. 1, a resist mask 10 having a pattern for forming a via hole is formed on the second insulation layer 7. The resist mask 10 may be formed using, e.g., a chemical vapor deposition or spin-coating method.
Then, referring to illustration 1 c in FIG. 1, a via hole (V) is etched using the pattern of the resist mask 10. In the present example embodiment, the via hole (V) is formed down to the lower end of the first insulation layer 3, e.g., the via hole (V) is formed through the second insulation layer 7 and the first insulation layer 3 so as to expose the substrate 1. As shown in illustration 1 c of FIG. 1, when the via hole (V) is complete, the resist mask 10 on the second insulation layer 7 may be removed.
Then, referring to illustration 1 d in FIG. 1, a hardmask layer 20 is formed in the via hole (V) and on the second insulation layer 7. As shown in illustration 1 d in FIG. 1, the hardmask layer 20 may fill the via hole (V) and cover the second insulation layer 7 adjacent to the via hole (V). The hardmask layer 20 works as an interlayer transmitting the fine pattern of the resist to the material layer through a selective etching process. In the present example embodiment, the hardmask layer 20 is formed using a spin-coating method.
The hardmask layer 20 formed using the spin-coating method may provide an excellent gap-filling characteristic, and may provide a better gap-filling characteristic than a hardmask layer formed using a chemical vapor deposition method. Accordingly, the hardmask layer 20 formed using the spin-coating method may fill the via hole without a void despite increases in the aspect ratio of the pattern as the pattern becomes finer. The hardmask layer 20 formed using the spin-coating method may make it possible to design various structures of a device and improve reliability of the device compared with the hardmask layer formed in the chemical vapor deposition method.
The hardmask layer 20 is formed to have a predetermined height on the second insulation layer 7 by coating a hardmask composition in the via hole (V) and on the second insulation layer 7. For example, the hardmask layer 20 may be about 2000 Å to about 3800 Å thick. Herein, the thickness of the hardmask layer 20 is measured with reference to the upperend of the second insulation layer 7. When the hardmask layer 20 has a thickness within the range it may easily transmit a pattern and simultaneously secure sufficient etching resistance.
The formation of the hardmask layer 20 may further include a heat-treatment at about 200° C. to about 500° C. For example, the heat treatment may be performed in a range of about 350° C. to about 400° C. The heat treatment within the temperature range may secure sufficient cross-linking and gap-filling characteristics of the hardmask composition, and improve efficiency in a subsequent trench formation process. The heat treatment may be performed in the air or under a nitrogen atmosphere.
Before forming the hardmask layer 20, a bottom antireflective coating (BARC) layer (not shown) may be further formed. An auxiliary layer (not shown) including silicon may be formed on the hardmask layer 20. The auxiliary layer along with the hardmask layer 20 may play a role of providing etching resistance.
Next, referring to illustration 1 e in FIG. 1, a resist mask 30 having a pattern for forming a trench hole is formed on the hardmask layer 20.
Next, referring to illustration 1 f in FIG. 1, the resist mask 30 is used to form a first trench hole T1. The first trench hole T1 is formed down to the lower end of the second insulation layer 7. When the first trench hole T1 is complete, the resist mask 30 is removed.
The first trench hole T1 may be patterned to have a depth of about 40% to 80% of the thickness sum of the first insulation layer 3 and the second insulation layer 7 when the thickness sum is 100%. The first trench hole T1 may be about 3200 Å to 7200 Å deep when TEOS 9K, for example, is used as a deposition material. When the first trench hole T1 has a depth within the stated range, a margin regulating a structure of a via top corner and a trench bottom corner in a subsequent process may be secured. The margin may make an etching rate difference between a fine pattern of loading/micro-loading and a wide pattern during dry etching uniform.
Then, referring to illustration 1 g in FIG. 1, the hardmask layer 20 formed in the via hole (V) and on the second insulation layer 7 is partially removed. In an implementation, portions of the hardmask layer 20 remaining in the via hole (V) and on the second insulation layer 7 after partially removing the hardmask layer 20 are respectively about 9500 Å to about 10,000 Å thick and about 500 Å to about 1000 Å thick. The thickness of the remaining hardmask layer 20 is obtained with reference to TEOS 9K as a deposition material. The hardmask layer 20 in the via hole (V) is partially removed and left within the range, so that the structure of a via top corner and a trench bottom corner may be easily designed, forming a fine pattern. In addition, the hardmask layer 20 on the second insulation layer 7 is partially removed and left within the range, so that the remaining hardmask layer 20 may work as an etch resistance layer in a subsequent process of forming a second trench hole T2.
Herein, the partial removal of the hardmask layer 20 in the via hole (V) and the second insulation layer 7 may be performed under a chamber pressure ranging from about 5 mTorr to about 10 mTorr, a high frequency (60 M) RF electric power ranging from about 100 W to about 500 W, a low frequency (2 M) RF electric power ranging from about 1000 W to about 2000 W, and an O2 gas flow rate ranging from about 20 SCCM to about 50 SCCM for about 5 seconds to about 10 seconds.
Referring to illustration 1 h in FIG. 1, after Partially removing the hardmask layer 20 in the via hole (V) and the second insulation layer 7, the second trench hole T2 is formed by partially removing the first insulation layer 3 between the top corner of the via hole (V) (via top corner) and the bottom corner of the first trench hole T1 (trench bottom corner).
According to the present example embodiment, the lower end of the second trench hole T2 may have a curved shape. Thus, the via top corner of the via hole (V) and the trench bottom corner of the first trench hole T1 may be connected with a curved line in the cross-section of a semiconductor pattern. When the lower end of the second trench hole T2 is smoothly curved, efficiency in a subsequent process of depositing a conductive material may be increased.
Referring to illustration 1 i in FIG. 1, when the second trench hole T2 is formed, the hardmask layer 20 remaining in the via hole (V) and on the second insulation layer 7 is removed. The removal of the hardmask layer 20 remaining in the via hole (V) may also include removing an etch-stop layer (not shown) exposed at the lower end of the via hole (V).
Then, referring to illustration 1 j in FIG. 1, the via hole (V) and the second trench hole T2 are filled with a conductive material to form an upper wire. The conductive material may be, e.g., copper (Cu). The filling may be performed with a deposition method.
According to another example embodiment, a semiconductor device including a plurality of patterns fabricated in the method of forming a dual damascene structure is provided.
By way of summation and review, using a copper (Cu) wire process instead of an aluminum (Al) wire process, and using a dual damascene process using a low dielectric constant (low k) material layer instead of an oxidation layer as an insulating layer may improve characteristics of the semiconductor device such as operation speed, resistance, and the like have been adopted.
The dual damascene process may be classified as a via-first dual damascene (VFDD) process of first etching a via hole and then forming a trench hole, and a trench-first dual damascene (TFDD) process of first etching a trench hole and then forming a via hole. The via-first dual damascene process may contribute to increasing efficiency in a subsequent process of forming a wire by regulating an angle between a via top corner and a trench bottom corner, when the trench hole is etched after etching the via hole, and then charging it with a hardmask composition.
As described above, example embodiments may provide a method of manufacturing a semiconductor device, and a method of forming a dual damascene structure for a copper wire. An example embodiment may provide a method of forming a dual damascene structure of a semiconductor device by spin-coating a hardmask composition to help control a profile between a via top corner and a trench bottom corner. Another example embodiment may provide a semiconductor device fabricated according to the method of forming a dual damascene structure. An example embodiment may provide a structure of a via top corner and a trench bottom corner, which is advantageous for a subsequent process, by applying a hardmask composition in a spin-coating method.
<Description of Symbols>
1: substrate 3: first insulation layer
7: second insulation layer 10, 30: resist mask
20: hardmask layer V: via hole
T1: first trench hole T2: second trench hole
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.

Claims (8)

What is claimed is:
1. A method of forming a dual damascene structure of a semiconductor device, the method comprising:
sequentially forming a first insulation layer and a second insulation layer on a substrate;
forming a resist mask having a pattern for forming a via hole on the second insulation layer;
forming a via hole down to a lower end of the first insulation layer;
forming a hardmask layer in the via hole and on the second insulation layer using a spin-coating method;
forming a resist mask having a pattern for forming a trench hole on the hardmask layer;
forming a first trench hole through the resist mask having the pattern for forming the trench hole, the first trench hole being formed down to a lower end of the second insulation layer;
respectively removing a part of the hardmask layer in the via hole and a part of the hardmask layer on the second insulation layer;
forming a second trench hole by removing a part of the first insulation layer between a top corner of the hardmask layer remaining in the via hole and a bottom corner of the first trench hole;
removing the hardmask layer remaining in the via hole and on the second insulation layer; and
forming an upper wire by filling the via hole and the second trench hole with a conductive material.
2. The method as claimed in claim 1, wherein the second trench hole has a curved shape in cross-section.
3. The method as claimed in claim 1, wherein forming the hardmask layer includes performing a heat treatment at a temperature ranging from about 200° C. to about 500° C.
4. The method as claimed in claim 1, further comprising forming an auxiliary layer including silicon on the hardmask layer before the forming of the resist mask having the pattern for forming the trench hole.
5. The method as claimed in claim 1, wherein, in the forming of the hardmask layer, the hardmask layer is formed to be about 2000 Å to about 3800 Å thick, measured with reference to the upper end of the second insulation layer.
6. The method as claimed in claim 1, wherein the first trench hole is formed to have a depth of about 40% to about 80% of a combined thickness the first insulation layer and the second insulation layer.
7. The method as claimed in claim 1, wherein, after respectively removing the part of the hardmask layer in the via hole and the part of the hardmask layer on the second insulation layer, the hardmask layer remaining in the via hole and the hard mask layer remaining on the second insulation layer are respectively about 9500 Å to about 10,000 Å and about 500 Å to about 1000 Å thick.
8. A semiconductor device comprising a plurality of patterns, which is fabricated according to the method as claimed in claim 1.
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106711082B (en) * 2015-07-28 2019-07-30 中芯国际集成电路制造(上海)有限公司 The manufacturing method of semiconductor devices
CN107170708A (en) * 2017-05-08 2017-09-15 上海华力微电子有限公司 Beneficial to the via-hole fabrication process of filling
TWI833228B (en) * 2022-03-31 2024-02-21 南亞科技股份有限公司 Method for fabricating semiconductor device

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010006848A1 (en) 1999-04-19 2001-07-05 National Semiconductor Corporation Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration
US6319815B1 (en) * 1998-10-21 2001-11-20 Tokyo Ohka Kogyo Co., Ltd. Electric wiring forming method with use of embedding material
US6426298B1 (en) * 2000-08-11 2002-07-30 United Microelectronics Corp. Method of patterning a dual damascene
KR20020070630A (en) 2001-02-28 2002-09-10 인터내셔널 비지네스 머신즈 코포레이션 Method for dual-damascene patterning of low-k interconnects using spin-on distributed hardmask
KR20020070631A (en) 2001-02-28 2002-09-10 인터내셔널 비지네스 머신즈 코포레이션 Interconnect structure with precise conductor resistance and method to form same
US6514856B2 (en) * 2000-02-15 2003-02-04 Nec Corporation Method for forming multi-layered interconnect structure
US20030170978A1 (en) 2002-03-05 2003-09-11 Shyh-Dar Lee Method of fabricating a dual damascene structure on a semiconductor substrate
KR20030079994A (en) 2001-02-28 2003-10-10 인터내셔널 비지네스 머신즈 코포레이션 HYBRID LOW-k INTERCONNECT STRUCTURE COMPRISED OF 2 SPIN-ON DIELECTRIC MATERIALS
KR20040031695A (en) 2001-02-28 2004-04-13 인터내셔널 비지네스 머신즈 코포레이션 Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics
KR20040058959A (en) * 2002-12-27 2004-07-05 주식회사 하이닉스반도체 Method of forming a dual damascene pattern
KR20080076235A (en) 2007-02-15 2008-08-20 주식회사 하이닉스반도체 Method of forming a dual damascene pattern in a semiconductor device
US7611986B2 (en) * 2005-04-11 2009-11-03 Imec Dual damascene patterning method
US20120129337A1 (en) 2010-11-22 2012-05-24 Shin-Chi Chen Dual damascene process

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW454301B (en) * 2000-03-21 2001-09-11 Winbond Electronics Corp Manufacturing method of dual metal damascene structure
KR100696760B1 (en) * 2000-12-29 2007-03-19 주식회사 하이닉스반도체 Manufacturing method for semiconductor device
JP3914493B2 (en) * 2002-11-27 2007-05-16 東京応化工業株式会社 Underlayer film forming material for multilayer resist process and wiring forming method using the same
KR100541012B1 (en) * 2003-08-23 2006-01-11 동부아남반도체 주식회사 Method For Manufacturing Semiconductor Devices
KR100802226B1 (en) * 2006-12-21 2008-02-11 주식회사 하이닉스반도체 Method for forming dual damascene pattern
CN101587855B (en) * 2008-05-20 2010-12-22 中芯国际集成电路制造(上海)有限公司 Method for manufacturing via hole and metal valley
CN102800626A (en) * 2012-08-16 2012-11-28 上海华力微电子有限公司 Method for preparing dielectric film on dual damascene structure through etching forming process

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6319815B1 (en) * 1998-10-21 2001-11-20 Tokyo Ohka Kogyo Co., Ltd. Electric wiring forming method with use of embedding material
US20010006848A1 (en) 1999-04-19 2001-07-05 National Semiconductor Corporation Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration
US6514856B2 (en) * 2000-02-15 2003-02-04 Nec Corporation Method for forming multi-layered interconnect structure
US6426298B1 (en) * 2000-08-11 2002-07-30 United Microelectronics Corp. Method of patterning a dual damascene
KR20040031695A (en) 2001-02-28 2004-04-13 인터내셔널 비지네스 머신즈 코포레이션 Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics
KR20020070630A (en) 2001-02-28 2002-09-10 인터내셔널 비지네스 머신즈 코포레이션 Method for dual-damascene patterning of low-k interconnects using spin-on distributed hardmask
KR20020070631A (en) 2001-02-28 2002-09-10 인터내셔널 비지네스 머신즈 코포레이션 Interconnect structure with precise conductor resistance and method to form same
KR20030079994A (en) 2001-02-28 2003-10-10 인터내셔널 비지네스 머신즈 코포레이션 HYBRID LOW-k INTERCONNECT STRUCTURE COMPRISED OF 2 SPIN-ON DIELECTRIC MATERIALS
US20030170978A1 (en) 2002-03-05 2003-09-11 Shyh-Dar Lee Method of fabricating a dual damascene structure on a semiconductor substrate
KR20040058959A (en) * 2002-12-27 2004-07-05 주식회사 하이닉스반도체 Method of forming a dual damascene pattern
US7611986B2 (en) * 2005-04-11 2009-11-03 Imec Dual damascene patterning method
KR20080076235A (en) 2007-02-15 2008-08-20 주식회사 하이닉스반도체 Method of forming a dual damascene pattern in a semiconductor device
US20120129337A1 (en) 2010-11-22 2012-05-24 Shin-Chi Chen Dual damascene process

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