US20010006848A1 - Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration - Google Patents

Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration Download PDF

Info

Publication number
US20010006848A1
US20010006848A1 US09/738,589 US73858900A US2001006848A1 US 20010006848 A1 US20010006848 A1 US 20010006848A1 US 73858900 A US73858900 A US 73858900A US 2001006848 A1 US2001006848 A1 US 2001006848A1
Authority
US
United States
Prior art keywords
dielectric
hardmask
interlayer dielectric
hardmasks
polymeric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/738,589
Other versions
US6440853B2 (en
Inventor
Sudhakar Allada
Chris Foster
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Priority to US09/738,589 priority Critical patent/US6440853B2/en
Publication of US20010006848A1 publication Critical patent/US20010006848A1/en
Application granted granted Critical
Publication of US6440853B2 publication Critical patent/US6440853B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
    • H01L21/3122—Layers comprising organo-silicon compounds layers comprising polysiloxane compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body

Definitions

  • the present invention relates to interconnect integration technology. More specifically, the present invention relates to methylated oxide-type hardmasks for patterning interlayer dielectrics in integrated circuit device fabrication.
  • interconnect capacitance is much larger than transistor capacitance.
  • a reduction of the interconnect capacitance decreases RC and in turn, delay, thereby increasing device speed.
  • Efforts to improve device performance include reducing the dielectric constant of interlayer dielectrics and the electrical resistance of interconnects, thereby reducing the wiring delay.
  • the polymeric dielectric (Allied Signal's FLARETM) was spin coated on undoped silicon glass (USG). The polymeric dielectric was then patterned through an overlying USG hardmask. Copper lines were formed by sputtering and CMP. Ikeda, et al.
  • a method according to the present invention includes a step of forming a methylated oxide-type hardmask on an interlayer dielectric, wherein the interlayer dielectric includes a polymeric dielectric material.
  • the hardmasks preferred for the invention are those having dielectric constants of less than 3 and more preferably 2.7 or less. Methods according to the present invention can produce integrated circuit devices having lower effective dielectric constants, which enhances device performance and speed.
  • both the hardmask and the interlayer dielectric can be spincoated.
  • the hardmask can be prepared by CVD techniques.
  • FIGS. 1 and 2 schematically illustrate cross sections of an interconnect stack formed according to the present invention.
  • the present invention relates to methods of interconnect integration in semiconductor fabrication techniques by eliminating need for removal of the wafer after formation of a polymeric interlayer dielectric to equipment for forming conventional oxide hardmasks on interlayer dielectrics.
  • the present invention increases device speed by reducing the effective dielectric constant in the stack, and the structures created thereby.
  • the present invention utilizes methylated oxide-type materials as hardmasks for the interlayer dielectric.
  • methods according to the present invention benefit from increased compatibility and improved adhesion between the hardmask and interlayer polymeric dielectric and ease of subsequent wafer processing, especially chemical mechanical polishing steps.
  • Methylated oxide-type dielectrics contemplated for hardmasks also have similar etching characteristics to conventional oxide hardmasks so that known processing regimes used successfully for SiO 2 and Cu metallization can be utilized.
  • An interlayer dielectric in accordance with the present invention is suitably a polymeric semiconductor dielectric resin, such as Dow Chemical's SiLKTM material.
  • a polymeric semiconductor dielectric resin such as Dow Chemical's SiLKTM material.
  • this material is reported to have a dielectric constant of 2.65, compatible with aluminum/tungsten interconnects and stable to 490° C., and may be processed by conventional spin coating techniques and equipment. The inventors have found that this material is also compatible with copper metallization in dual damascene interconnect structures as well.
  • the inventors also have found that significant advantage can be achieved by forming a hardmask from a methylated oxide-type dielectric such as Allied Signal's HOSPTM material by spin coating techniques, since the hardmask may be formed the same equipment immediately following spin-coating of the interlayer dielectric from a polymeric dielectric resin, as described above.
  • a methylated oxide-type dielectric such as Allied Signal's HOSPTM material
  • spin coating techniques since the hardmask may be formed the same equipment immediately following spin-coating of the interlayer dielectric from a polymeric dielectric resin, as described above.
  • the present invention also contemplates formation of methylated oxide-type dielectric by conventional CVD techniques, as an alternative to a spin coated dielectric material.
  • CVD techniques as an alternative to a spin coated dielectric material.
  • the advantage of spincoated materials compared to CVD deposited materials is reduced cycle time for fabrication since all dielectric layers of the stack can be deposited in the same spin track operation on the same tool. In contrast, the CVD deposited materials require additional process steps and additional tools.
  • the methylated oxide-type hardmask and the polymeric dielectric material for the interlayer dielectric can significantly reduce the effective dielectric constant, and therefore the capacitance between metal lines, improving device speed, depending on device architecture.
  • FIGS. 1 and 2 illustrate exemplary interconnect stacks prepared according to the present invention.
  • a single damascene structure 10 may be fabricated.
  • a silicon nitride diffusion barrier 12 is deposited on a bare silicon substrate 14 .
  • a polymeric interlayer dielectric 16 is spun on diffusion barrier 12 , followed by a methylated hardmask 18 .
  • Dielectric layer 16 is etched and then electroplated with copper to produce the single damascene structure 10 with a copper line 20 .
  • dual damascene structure 22 can be formed by spinning four alternating layers of polymeric interlayer dielectric 24 , 26 and hardmask 28 , 30 followed by etch and copper electroplating to form copper line 32 .
  • Table 1 lists typical dimensions of the layers in a stack such as illustrated in FIGS. 1 and 2.
  • the thickness of the methylated oxide-type hardmask is consistent with conventional oxide (e.g., USG) hardmask materials. Thickness of the hardmask will depend on the thickness of the underlying dielectric layer and device architecture.

Abstract

Disclosed are multilevel interconnects for integrated circuit devices, especially copper/dual damascene devices, and methods of fabrication. Methylated-oxide type hardmasks are formed over polymeric interlayer dielectric materials. Preferably the hardmasks are materials having a dielectric constant of less than 3 and more preferably 2.7 or less. Advantageously, both the hardmask and the interlayer dielectric can be spincoated.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to interconnect integration technology. More specifically, the present invention relates to methylated oxide-type hardmasks for patterning interlayer dielectrics in integrated circuit device fabrication. [0002]
  • 2. Description of the Related Art [0003]
  • Integration of multilevel interconnects becomes increasingly important with ever increasing demands for device miniaturization and speed. In fact, with sub-0.25 μm geometries, interconnect capacitance is much larger than transistor capacitance. A reduction of the interconnect capacitance decreases RC and in turn, delay, thereby increasing device speed. [0004]
  • Efforts to improve device performance include reducing the dielectric constant of interlayer dielectrics and the electrical resistance of interconnects, thereby reducing the wiring delay. Ikeda, et al., [0005] I.E.E.E. Inter. Interconnect Technology Conf. (1998) p. 131, describe a low k polymeric dielectric with a Cu-damascene structure. The polymeric dielectric (Allied Signal's FLARE™) was spin coated on undoped silicon glass (USG). The polymeric dielectric was then patterned through an overlying USG hardmask. Copper lines were formed by sputtering and CMP. Ikeda, et al. reported advantageous use of USG in achieving simultaneous resist ashing and etching of the polymeric dielectric as well as anisotropic O2 RIE etching. In addition, Ikeda, et al. reported relatively decreased wiring resistance of copper metallization formed in the polymeric dielectric with increasing metallization width.
  • However, certain disadvantages attend. As those of skill in the art will appreciate, conventional processing to put a USG hardmask on a polymeric dielectric requires removal of the wafer from spin track equipment after formation of a polymeric dielectric to a different machine in order to create the hardmask. In addition, conventional USG hardmasks do not adhere well to a polymeric interlayer dielectric, which affects subsequent wafer processing. [0006]
    • SUMMARY OF THE INVENTION
  • The present invention addresses these and other problems in the prior art by providing a method of fabricating multilevel interconnects for integrated circuit devices, preferably for copper/dual damascene interconnect structures in integrated circuit devices. In one embodiment, a method according to the present invention includes a step of forming a methylated oxide-type hardmask on an interlayer dielectric, wherein the interlayer dielectric includes a polymeric dielectric material. The hardmasks preferred for the invention are those having dielectric constants of less than 3 and more preferably 2.7 or less. Methods according to the present invention can produce integrated circuit devices having lower effective dielectric constants, which enhances device performance and speed. [0007]
  • In the present invention, both the hardmask and the interlayer dielectric can be spincoated. Alternatively, the hardmask can be prepared by CVD techniques. [0008]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will be better understood by reference to the figures of the drawings, in which like reference numerals represent like elements and in which [0009]
  • FIGS. 1 and 2 schematically illustrate cross sections of an interconnect stack formed according to the present invention. [0010]
    • DESCRIPTION OF PREFERRED EMBODIMENTS
  • The present invention relates to methods of interconnect integration in semiconductor fabrication techniques by eliminating need for removal of the wafer after formation of a polymeric interlayer dielectric to equipment for forming conventional oxide hardmasks on interlayer dielectrics. The present invention increases device speed by reducing the effective dielectric constant in the stack, and the structures created thereby. Instead of a conventional oxide hardmask, the present invention utilizes methylated oxide-type materials as hardmasks for the interlayer dielectric. As a result, methods according to the present invention benefit from increased compatibility and improved adhesion between the hardmask and interlayer polymeric dielectric and ease of subsequent wafer processing, especially chemical mechanical polishing steps. Methylated oxide-type dielectrics contemplated for hardmasks also have similar etching characteristics to conventional oxide hardmasks so that known processing regimes used successfully for SiO[0011] 2 and Cu metallization can be utilized.
  • An interlayer dielectric in accordance with the present invention is suitably a polymeric semiconductor dielectric resin, such as Dow Chemical's SiLK™ material. Advantageously, this material is reported to have a dielectric constant of 2.65, compatible with aluminum/tungsten interconnects and stable to 490° C., and may be processed by conventional spin coating techniques and equipment. The inventors have found that this material is also compatible with copper metallization in dual damascene interconnect structures as well. [0012]
  • Methylated oxide-type dielectrics useful in the present invention are materials exhibiting relatively low dielectric constant (k) of less than 3 and preferably less than about 2.7. These methylated oxide-type dielectrics have k much lower than conventional hardmask materials such as silicon dioxide (k=4) and silicon nitride (k=8), but similar etch and chemical contrast characteristics. Therefore, conventional hardmask thicknesses, etching techniques and chemistries can be used. Exemplary methylated oxide-type dielectrics suitable for the hardmasks prepared in accordance with the present invention include Allied Signal's HOSP™ proprietary materials. [0013]
  • The inventors also have found that significant advantage can be achieved by forming a hardmask from a methylated oxide-type dielectric such as Allied Signal's HOSP™ material by spin coating techniques, since the hardmask may be formed the same equipment immediately following spin-coating of the interlayer dielectric from a polymeric dielectric resin, as described above. In addition, it is contemplated that as many as four layers can be spin coated over the layer adjacent to the wafer without sacrificing performance or processing ease. [0014]
  • The present invention also contemplates formation of methylated oxide-type dielectric by conventional CVD techniques, as an alternative to a spin coated dielectric material. The advantage of spincoated materials compared to CVD deposited materials is reduced cycle time for fabrication since all dielectric layers of the stack can be deposited in the same spin track operation on the same tool. In contrast, the CVD deposited materials require additional process steps and additional tools. [0015]
  • Together, the methylated oxide-type hardmask and the polymeric dielectric material for the interlayer dielectric can significantly reduce the effective dielectric constant, and therefore the capacitance between metal lines, improving device speed, depending on device architecture. [0016]
  • FIGS. 1 and 2 illustrate exemplary interconnect stacks prepared according to the present invention. [0017]
  • As shown in FIGS. 1[0018] a and 1 b, a single damascene structure 10 may be fabricated. A silicon nitride diffusion barrier 12 is deposited on a bare silicon substrate 14. A polymeric interlayer dielectric 16 is spun on diffusion barrier 12, followed by a methylated hardmask 18. Dielectric layer 16 is etched and then electroplated with copper to produce the single damascene structure 10 with a copper line 20.
  • Likewise, as shown in FIGS. 2[0019] a and 2 b, dual damascene structure 22 can be formed by spinning four alternating layers of polymeric interlayer dielectric 24, 26 and hardmask 28, 30 followed by etch and copper electroplating to form copper line 32.
  • Table 1 lists typical dimensions of the layers in a stack such as illustrated in FIGS. 1 and 2. As can be appreciated, the thickness of the methylated oxide-type hardmask is consistent with conventional oxide (e.g., USG) hardmask materials. Thickness of the hardmask will depend on the thickness of the underlying dielectric layer and device architecture. [0020]
    TABLE 1
    interlayer diffusion
    layer dielectric1 hardmask2 barrier3
    thickness 7 1 1
    (KÅ)
  • While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative, rather than limiting sense. It is contemplated that many modifications within the scope and spirit of the invention will readily occur to those skilled in the art and the appended claims are intended to cover such variations. [0021]

Claims (10)

We claim:
1. A method of fabricating multilevel interconnects for integrated circuit devices, comprising:
forming a methylated oxide-type hardmask on an interlayer dielectric, wherein the interlayer dielectric includes a polymeric dielectric material.
2. A method according to
claim 1
, wherein the hardmask is spincoated on the-interlayer dielectric.
3. A method according to
claim 1
, wherein the hardmask has a dielectric constant of about 2.7 or less.
4. A method according to
claim 1
, further comprising the step of forming copper metallization lines in the interlayer dielectric.
5. An integrated circuit device fabricated according to the method of
claim 1
.
6. A method of reducing the effective dielectric constant of integrated circuit devices, comprising:
forming a methylated oxide-type hardmask on an interlayer dielectric, wherein the interlayer dielectric includes a polymeric dielectric material.
7. A method according to
claim 6
, wherein the hardmask is spincoated on the interlayer dielectric.
8. A method according to
claim 6
, wherein the hardmask has a dielectric constant of about 2.7 or less.
9. A method according to
claim 6
, further comprising the step of forming copper metallization lines in the interlayer dielectric.
10. An integrated circuit device formed according to the method of
claim 6
.
US09/738,589 1999-04-19 2000-12-15 Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low k, dual damascene interconnect integration Expired - Lifetime US6440853B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/738,589 US6440853B2 (en) 1999-04-19 2000-12-15 Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low k, dual damascene interconnect integration

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/294,914 US6218317B1 (en) 1999-04-19 1999-04-19 Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration
US09/738,589 US6440853B2 (en) 1999-04-19 2000-12-15 Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low k, dual damascene interconnect integration

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/294,914 Division US6218317B1 (en) 1999-04-19 1999-04-19 Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration

Publications (2)

Publication Number Publication Date
US20010006848A1 true US20010006848A1 (en) 2001-07-05
US6440853B2 US6440853B2 (en) 2002-08-27

Family

ID=23135477

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/294,914 Expired - Lifetime US6218317B1 (en) 1999-04-19 1999-04-19 Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration
US09/738,589 Expired - Lifetime US6440853B2 (en) 1999-04-19 2000-12-15 Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low k, dual damascene interconnect integration

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/294,914 Expired - Lifetime US6218317B1 (en) 1999-04-19 1999-04-19 Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration

Country Status (1)

Country Link
US (2) US6218317B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521533B1 (en) * 1999-09-14 2003-02-18 Commissariat A L'energie Atomique Method for producing a copper connection
US20060038296A1 (en) * 2004-08-19 2006-02-23 King Sean W Integrated low-k hard mask
US8900997B2 (en) 2012-12-26 2014-12-02 Cheil Industries, Inc. Method for forming a dual damascene structure of a semiconductor device, and a semiconductor device therewith

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3305251B2 (en) * 1998-02-26 2002-07-22 松下電器産業株式会社 Method of forming wiring structure
US6509259B1 (en) 1999-06-09 2003-01-21 Alliedsignal Inc. Process of using siloxane dielectric films in the integration of organic dielectric films in electronic devices
JP4368498B2 (en) * 2000-05-16 2009-11-18 Ｎｅｃエレクトロニクス株式会社 Semiconductor device, semiconductor wafer and manufacturing method thereof
US7115531B2 (en) * 2000-08-21 2006-10-03 Dow Global Technologies Inc. Organosilicate resins as hardmasks for organic polymer dielectrics in fabrication of microelectronic devices
US6656532B2 (en) 2001-05-17 2003-12-02 Honeywell International Inc. Layered hard mask and dielectric materials and methods therefor
US6620727B2 (en) * 2001-08-23 2003-09-16 Texas Instruments Incorporated Aluminum hardmask for dielectric etch
US6605549B2 (en) 2001-09-29 2003-08-12 Intel Corporation Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics
US20030096090A1 (en) * 2001-10-22 2003-05-22 Boisvert Ronald Paul Etch-stop resins
JP4546094B2 (en) * 2002-04-02 2010-09-15 ダウ グローバル テクノロジーズ インコーポレイティド Three-layer masking architecture for patterning dual damascene interconnects
JP2004146798A (en) * 2002-09-30 2004-05-20 Sanyo Electric Co Ltd Semiconductor device and manufacturing method therefor
TW200505966A (en) * 2003-04-02 2005-02-16 Dow Global Technologies Inc Organosilicate resin formulation for use in microelectronic devices
JP2008516361A (en) * 2004-10-05 2008-05-15 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Recovery of defocused track focusing on optical disks
CN104347478B (en) * 2013-07-24 2017-05-17 中芯国际集成电路制造(上海)有限公司 Semiconductor structure formation method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4522681A (en) * 1984-04-23 1985-06-11 General Electric Company Method for tapered dry etching
US5924005A (en) 1997-02-18 1999-07-13 Motorola, Inc. Process for forming a semiconductor device
US6218302B1 (en) * 1998-07-21 2001-04-17 Motorola Inc. Method for forming a semiconductor device
US6100195A (en) * 1998-12-28 2000-08-08 Chartered Semiconductor Manu. Ltd. Passivation of copper interconnect surfaces with a passivating metal layer
US6136511A (en) 1999-01-20 2000-10-24 Micron Technology, Inc. Method of patterning substrates using multilayer resist processing
US6028015A (en) * 1999-03-29 2000-02-22 Lsi Logic Corporation Process for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521533B1 (en) * 1999-09-14 2003-02-18 Commissariat A L'energie Atomique Method for producing a copper connection
US20060038296A1 (en) * 2004-08-19 2006-02-23 King Sean W Integrated low-k hard mask
WO2006023255A1 (en) * 2004-08-19 2006-03-02 Intel Corporation Integrated low-k hard mask
US7199473B2 (en) 2004-08-19 2007-04-03 Intel Corporation Integrated low-k hard mask
GB2430803A (en) * 2004-08-19 2007-04-04 Intel Corp Low-k hard mask
KR100888881B1 (en) * 2004-08-19 2009-03-17 인텔 코포레이션 Integrated low-k hard mask
GB2430803B (en) * 2004-08-19 2009-11-25 Intel Corp Integrated low-k hard mask
CN101006576B (en) * 2004-08-19 2010-08-18 英特尔公司 Integrated low-K hard mask
US8900997B2 (en) 2012-12-26 2014-12-02 Cheil Industries, Inc. Method for forming a dual damascene structure of a semiconductor device, and a semiconductor device therewith

Also Published As

Publication number Publication date
US6218317B1 (en) 2001-04-17
US6440853B2 (en) 2002-08-27

Similar Documents

Publication Publication Date Title
US6756297B2 (en) Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer
US7768130B2 (en) BEOL interconnect structures with simultaneous high-k and low-k dielectric regions
US6440853B2 (en) Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low k, dual damascene interconnect integration
KR100670227B1 (en) Method of fabricating copper interconnections in semiconductor devices
US6143641A (en) Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures
US7132363B2 (en) Stabilizing fluorine etching of low-k materials
US6406994B1 (en) Triple-layered low dielectric constant dielectric dual damascene approach
US6383913B1 (en) Method for improving surface wettability of low k material
US7241681B2 (en) Bilayered metal hardmasks for use in dual damascene etch schemes
US20010051420A1 (en) Dielectric formation to seal porosity of low dielectic constant (low k) materials after etch
US6486557B1 (en) Hybrid dielectric structure for improving the stiffness of back end of the line structures
US6620727B2 (en) Aluminum hardmask for dielectric etch
US7586142B2 (en) Semiconductor device having metal-insulator-metal capacitor and method of fabricating the same
US6680542B1 (en) Damascene structure having a metal-oxide-metal capacitor associated therewith
US6501180B1 (en) Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures
US6284642B1 (en) Integrated method of damascene and borderless via process
EP1330842B1 (en) Low temperature hillock suppression method in integrated circuit interconnects
US6689684B1 (en) Cu damascene interconnections using barrier/capping layer
US6803314B2 (en) Double-layered low dielectric constant dielectric dual damascene method
US6288448B1 (en) Semiconductor interconnect barrier of boron silicon nitride and manufacturing method therefor
US6548901B1 (en) Cu/low-k BEOL with nonconcurrent hybrid dielectric interface
US7041574B2 (en) Composite intermetal dielectric structure including low-k dielectric material
US6346474B1 (en) Dual damascene process
US6204096B1 (en) Method for reducing critical dimension of dual damascene process using spin-on-glass process
US20010018273A1 (en) Method of fabricating copper interconnecting line

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12