CN103681640B - 叠层型半导体装置及其制造方法 - Google Patents

叠层型半导体装置及其制造方法 Download PDF

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Publication number
CN103681640B
CN103681640B CN201310058066.1A CN201310058066A CN103681640B CN 103681640 B CN103681640 B CN 103681640B CN 201310058066 A CN201310058066 A CN 201310058066A CN 103681640 B CN103681640 B CN 103681640B
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semiconductor chip
circuit substrate
thickness
semiconductor
adhesive linkage
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CN103681640A (zh
Inventor
谷本亮
井本孝志
安藤善康
野田真史
岩政直树
宫下浩
宫下浩一
川户雅敏
岩本正次
田中润
堂前佑辅
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Japanese Businessman Panjaya Co ltd
Kioxia Corp
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Toshiba Corp
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Abstract

本发明涉及叠层型半导体装置。提供可以消除当在半导体芯片的粘接剂层内埋入比其小型的半导体芯片时产生的缺点的叠层型半导体装置。实施方式的叠层型半导体装置（1）具备配置于电路基板（2）上的第1半导体芯片（6）、使第1半导体芯片（6）粘合于电路基板（2）的粘接层（7）和具有比第1半导体芯片（6）小的外形的第2半导体芯片（10）。第2半导体芯片（10）至少一部分埋入于粘接层（7）内。粘接层（7）具有95μm以上且150μm以下的范围的厚度，并且包括当埋入第2半导体芯片（10）时的热时粘度为500Pa·s以上且5000Pa·s以下的范围的热固化性树脂。

Description

叠层型半导体装置及其制造方法
关联申请
本申请要求以日本专利申请2012—198367号（申请日：2012年9月10日）为基础申请的优先权。本申请通过参照该基础申请而包括基础申请的全部的内容。
技术领域
本发明的实施方式涉及叠层型半导体装置及其制造方法。
背景技术
为了实现半导体装置的小型化、高速化、高性能化等，在1个封装内层叠多个半导体芯片并进行了密封的SiP（System in Package，封装内系统）结构的半导体装置正在实用化。SiP结构的半导体器件例如具备布线基板、搭载于布线基板上的存储器芯片和／或控制器芯片等的半导体芯片和将这些半导体芯片统一进行密封的密封树脂层。外形比存储器芯片小的控制器芯片等的系统LSI芯片一般配置于将存储器芯片多级层叠的芯片叠层体上。该情况下，因为从布线基板到系统LSI芯片的布线长度变长，所以担心信号传送速度的下降等。
相对于如此之点，提出在将存储器芯片粘接于布线基板的粘接剂层内埋入系统LSI芯片。根据如此的结构，能够谋求半导体装置的小型化，并且缩短从布线基板到系统LSI芯片的布线长度。从而，可以提供小型而对应于高速器件的半导体装置。可是，当将系统LSI芯片埋入于存储器芯片的粘接剂层时，担心各种不良状况的产生。例如，有可能在将系统LSI芯片埋入于粘接剂层内时存储器芯片变形为凸状，或起因于系统LSI芯片的埋入不足而产生空隙。存储器芯片的变形成为工作不良的原因。并且，在系统LSI芯片的周围产生的空隙成为裂纹等的产生原因。
发明内容
本发明要解决的问题在于提供可以消除当在半导体芯片的粘接剂层内埋入比其小型的半导体芯片时产生的缺点的叠层型半导体装置及其制造方法。
实施方式的叠层型半导体装置具备：电路基板；配置于电路基板上的第1半导体芯片；使第1半导体芯片粘合于电路基板的粘接层；至少一部分埋入于粘接层内并具有比第1半导体芯片小的外形的第2半导体芯片；对电路基板和第1半导体芯片进行电连接的第1连接构件；对电路基板和第2半导体芯片进行电连接的第2连接构件；和设置于电路基板上用于将第1及第2半导体芯片与第1及第2连接构件一起进行密封的密封树脂层。第2半导体芯片具有75μm以下的厚度。粘接层具有95μm以上且150μm以下的范围的厚度，并且包括当埋入第2半导体芯片时的热时粘度为500Pa·s以上且5000Pa·s以下的范围的热固化性树脂。
附图说明
图1是表示实施方式涉及的叠层型半导体装置的剖视图。
图2是表示示于图1的叠层型半导体装置的第1变形例的剖视图。
图3是表示示于图1的叠层型半导体装置的第2变形例的剖视图。
图4是基于第1半导体芯片上的密封树脂层的厚度表示实施方式涉及的叠层型半导体装置的温度和翘曲量的关系的图。
图5是表示示于图1的叠层型半导体装置的制造方法的剖视图。
图6是表示在示于图5的叠层型半导体装置的制造方法中所使用的第1半导体芯片的制作工序的剖视图。
图7是表示示于图6的第1半导体芯片的制作工序中的第1刀片的晶片切留量和刀片磨损量及选取不良率的关系的图。
符号说明
1…叠层型半导体装置，2…布线基板，3…外部电极，5…内部电极，6、6A～6D…第1半导体芯片，7…第1粘接层，8A～8C…第2粘接层，9…第1接合线，10…第2半导体芯片，11…第3粘接层，12…第2接合线，13…密封树脂层，14…粘接剂层，21…半导体晶片，22…粘接剂层，23…划片带，24…第1刀片，25…第2刀片。
具体实施方式
以下，关于实施方式的叠层型半导体装置及其制造方法，参照附图进行说明。图1是表示实施方式涉及的叠层型半导体装置的剖视图。示于图1的叠层型半导体装置1作为电路基板具备布线基板2。布线基板2例如在绝缘树脂基板和／或陶瓷基板等的表面和／或内部设置有布线网（未图示），具体地可举出使用了如玻璃环氧树脂的绝缘树脂的印刷布线板。作为电路基板，也可以代替布线基板（中介层基板）2，使用硅中介层等。布线基板2具有成为外部端子的形成面的第1面2a和成为半导体芯片的搭载面的第2面2b。
布线基板2的第1面2a具有外部电极3。在外部电极3上形成外部端子4。在使用叠层型半导体装置1作为BGA封装的情况下，外部端子4以采用了焊球和／或镀焊等的突起端子构成。在使用叠层型半导体装置1作为LGA封装的情况下，作为外部端子4应用采用了镀金等的金属地。成为半导体芯片的搭载面的布线基板2的第2面2b具有内部电极5。内部电极5的至少一部分介由布线基板2的布线网及外部电极3与外部端子4电连接。
在布线基板2的第2面2b上，配置多个第1半导体芯片6（6A～6D）。第1半导体芯片6A～6D各自的电极垫露出地叠层为阶梯状。作为第1半导体芯片6的具体例，虽然可举出如NAND型闪存的半导体存储器芯片，但是并不限于此。虽然图1示出叠层有4个第1半导体芯片6A～6D的结构，但是第1半导体芯片6的相对于布线基板2的搭载数量并非限定于此。第1半导体芯片6的搭载数量也可以为1个或多个的任一。多个第1半导体芯片6的厚度虽然根据其制造工序等也不相同，但是例如可以为90μm以上。并且，也可以相应于配置位置应用不同的厚度的半导体芯片6。
多个第1半导体芯片6A～6D之中，位于最下层的第1半导体芯片6A介由第1粘接层7粘合于布线基板2的第2面2b。第1粘接层7介于布线基板2的第2面2b和第1半导体芯片6A之间，粘接于布线基板2的第2面2b。在位于最下层的第1半导体芯片6A上，介由第2粘接层8A～8C依次粘接从第2层～第4层的第1半导体芯片6B～6D。第1半导体芯片6A～6D的电极垫通过将它们阶梯状地错开进行叠层，分别朝向上方露出。
第1半导体芯片6A～6D的电极垫与布线基板2的内部电极5介由第1接合线9电连接。关于电特性和／或信号特性等同的电极垫，能够对布线基板2的内部电极5和第1半导体芯片6A～6D的电极垫以第1接合线9按顺序进行连接。作为第1接合线9，可采用一般的Au线和／或Cu线等的金属线。关于后述的第2接合线也相同。第1接合线9作为对第1半导体芯片6A～6D的电极垫和布线基板2的内部电极5进行电连接的第1连接构件而起作用。
第1连接构件并不限于接合线，也可以为以喷墨印刷等形成的布线层（导体层）等。并且，多个第1半导体芯片6间的电连接也可以介由设置于第1半导体芯片6的内部的贯通电极和突起电极而进行。该情况下，将多个第1半导体芯片6间介由贯通电极及突起电极进行机械及电连接。而且，将任一个第1半导体芯片6、例如位于最上层的第1半导体芯片6和布线基板2的内部电极5介由接合线进行电连接。
在布线基板2的第2面2b上，具有比第1半导体芯片6小的外形（尺寸）的第2半导体芯片10进一步配置为，位于第1半导体芯片6的下侧。即，第2半导体芯片10介由第3粘接层11粘接于布线基板2的第2面2b，进而埋入于使位于最下层的第1半导体芯片6A粘合于布线基板2的第1粘接层7内。第2半导体芯片10的电极垫与布线基板2的内部电极5介由第2接合线12电连接。对第2半导体芯片10和布线基板2进行电连接的第2连接构件并不限于接合线12，也可以为突起电极等。
作为第2半导体芯片10，虽然可举出在作为第1半导体芯片6的存储器芯片和外部设备之间发送接收数字信号的控制器芯片和／或接口芯片、逻辑芯片、RF芯片等的系统LSI芯片，但是并非限定于此。通过将第2半导体芯片直接搭载于布线基板2的第2面2b上，能够缩短从系统LSI芯片等的第2半导体芯片10到布线基板2的布线长度，并且能够使基板布线最优化。由此，可以应对叠层型半导体装置1的高速化。而且，因为第2半导体芯片10埋入于第1粘接层7内，所以也不会使第1半导体芯片6A～6D相对于布线基板2的搭载性下降，并且妨碍装置尺寸的小型化等。从而，能够提供小型且对应于高速器件的叠层型半导体装置1。
在布线基板2的第2面2b上，例如模塑成型采用了环氧树脂等的绝缘树脂的密封树脂层13，用于将第1半导体芯片6和第2半导体芯片10与接合线9、12一起进行密封。通过这些构成要素，构成实施方式的叠层型半导体装置1。还有，虽然图1示出将第2半导体芯片10的整体埋入于第1粘接层7内的结构，但是第2半导体芯片10的向第1粘接层7内埋入的结构并不限于此。如示于图2地，也可以应用将第2半导体芯片10的一部分埋入于第1粘接层7内的结构。由此，也能够实现布线长度的缩短和／或装置尺寸的小型化等。第2半导体芯片10只要其至少一部分埋入于第1粘接层7内即可。
第2半导体芯片10并不限于直接配置于布线基板2的第2面2b上的结构，在从第2半导体芯片10到布线基板2的布线长度不会对信号传送速度产生恶劣影响的范围，也可以配置于其他的半导体芯片上。图3示出在布线基板2的第2面2b上配置第1层的第1半导体芯片6A并在其上配置第2半导体芯片10的结构。第2半导体芯片10埋入于使第2层的第1半导体芯片6B粘合于布线基板2的粘接层7内。第2半导体芯片10只要埋入于使第1半导体芯片6粘合于布线基板2的粘接层7内即可，并不限于将第1半导体芯片6直接粘接于布线基板2的粘接层7，也可以埋入于将第1半导体芯片6介由其他的半导体芯片粘接于布线基板2的粘接层7内。
当将第2半导体芯片10埋入于粘接层7内时，第2半导体芯片10具有75μm以下的厚度。若第2半导体芯片10的厚度超过75μm，则即使对构成粘接层7的粘接剂的特性等进行改良，也无法将第2半导体芯片10良好地埋入于粘接层7内。第2半导体芯片10的厚度的下限值虽然并非特别限定，但是一般为20μm以上。而且，为了将厚度为75μm以下的第2半导体芯片10良好地埋入，粘接层7要具有95μm以上的厚度。若粘接层7的厚度不足95μm，则对第2半导体芯片10和布线基板2进行电连接的接合线12会与第1半导体芯片6相接触，并且第2半导体芯片10和第1半导体芯片6之间的耐绝缘性等会下降。
若换言之，则通过应用厚度为95μm以上的粘接层7，能够一边维持第2半导体芯片10的工作和／或可靠性一边埋入于粘接层7内。在仅考虑将第2半导体芯片10埋入于粘接层7内的情况下，通过使粘接层7的厚度进一步变厚，第2半导体芯片10的埋入性会提高。可是，若使粘接层7的厚度过于变厚，则会妨碍叠层型半导体装置1的小型化和／或薄型化。因此，粘接层7的厚度为150μm以下。在实施方式的叠层型半导体装置1中，应用厚度为95μm以上且150μm以下的范围的粘接层7，由此能够提高第2半导体芯片10的埋入性。
可是，若应用厚度为95μm以上地厚的粘接层7，则在形成粘接层7的粘接剂内由于第2半导体芯片10的埋入时的硬度等，第1半导体芯片6会膨胀为凸状地变形，并且有可能在第2半导体芯片10的周围产生空隙。因此，作为在该实施方式中成为粘接层7的形成材料的粘接剂，应用当埋入第2半导体芯片10时的热时粘度为500Pa·s以上且5000Pa·s以下的范围的热固化性树脂。在此，所谓热时粘度表示当对半固化状态的热固化性树脂时进行了加热时软化或溶融而呈现粘接性的温度的粘度。热固化性树脂软化或溶融的温度通过构成粘接剂的热固化性树脂的材料特性和／或粘接剂层的形成条件、例如使液状（A阶段）的树脂组成物成为半固化状态（B阶段）时的干燥温度和／或干燥时间等决定。
根据采用了热时粘度为5000Pa·s以下的热固化性树脂的粘接剂，能够提高埋入第2半导体芯片10时的粘接剂的流动性。从而，因为粘接剂在第2半导体芯片10的上部良好地流动而扩展，所以能够对起因于粘接剂的硬度的第1半导体芯片6的凸状的变形和／或基于此的工作不良的产生等进行抑制。而且，由于粘接剂良好地流动，粘接剂充分地绕经第2半导体芯片10的周围。从而，能够对在第2半导体芯片10周围产生的空隙和／或起因于其的裂纹等进行抑制。但是，因为若粘接剂的热时粘度过低，则第1半导体芯片6相对于电路基板2的平行性会下降，并且有可能无法维持第1半导体芯片6和第2半导体芯片10的间隔，所以粘接剂的热时粘度为500Pa·s以上。
作为用于粘接剂的热固化性树脂，可举出环氧树脂、聚酰亚胺树脂、丙烯酸树脂、酚醛树脂等。作为粘接剂，与一般的热固化性粘接剂同样地，能够采用包括固化剂、固化促进剂、无机填充材料、各种添加剂、溶剂等的热固化性树脂组成物。通过对如此的热固化性树脂组成物中的粘度调整剂的种类和／或添加量、成为B阶段时的干燥条件、具有流动性的低分子成分的添加量等进行调整，能够使粘接剂的热时粘度成为500～5000Pa·s的范围。后述的粘接剂的加热固化时的流动粘度除了所述的成分调整和／或条件调整之外，还能够通过对热固化性树脂组成物中的效果促进剂的添加量等进行调整，成为预期的范围。粘接层7包括如此的粘接剂的固化物。
如此地，通过采用热时粘度为500Pa·s以上且5000Pa·s以下的粘接剂，能够提高第2半导体芯片10向粘接剂层内的埋入性。因而，可以对起因于第2半导体芯片10的埋入不足的不良的产生进行抑制。粘接层7通过使热时粘度为500～5000Pa·s的热固化性树脂固化而形成。从而，根据包括热时粘度为500～5000Pa·s的范围的热固化性树脂的粘接层7，能够提供对起因于第2半导体芯片10向粘接层7内的埋入不足的不良的产生即第1半导体芯片6的变形和／或粘接层7的空隙的产生进行了抑制的叠层型半导体装置1。
并且，在应用了厚度为95μm以上地厚的粘接层7的情况下，当使叠层型半导体装置1从常温（25℃）升温到2次安装温度（例如270℃）时，叠层型半导体装置1的翘曲量容易增大。因此，在该实施方式的叠层型半导体装置1中，使第1半导体芯片6（具体地，位于最上层的第1半导体芯片6D）上的密封树脂层13的厚度为190μm以上。通过使第1半导体芯片6上的密封树脂层13的厚度为190μm以上，能够对升温时的叠层型半导体装置1的翘曲进行抑制。并且，因为即使密封树脂层13的厚度过厚，升温时的叠层型半导体装置1的翘曲也会增大，所以第1半导体芯片6上的密封树脂层13的厚度为440μm以下。
在图4基于第1半导体芯片6上的密封树脂层13的厚度表示叠层型半导体装置1的温度和翘曲量的关系。叠层型半导体装置1的翘曲量按照根据JEITA标准规定的“由于升温引起的封装的翘曲的测定方法和最大容许量（ED—7306）”进行了测定。叠层型半导体装置1的尺寸设为12mm×17mm。第1半导体芯片6上的密封树脂层13的厚度定义为从密封树脂层13的整体厚度除去第1粘接层7的厚度和第1半导体芯片6A～6D的厚度和第2粘接层8A～8C的厚度的厚度。如示于图4地，在埋入第2半导体芯片10的粘接层7的厚度为95～150μm的情况下，通过使第1半导体芯片6上的密封树脂层13的厚度为190μm以上且440μm以下的范围，能够使叠层型半导体装置1的翘曲量为容许范围的70μm以下。
布线基板2的厚度和／或特性、密封树脂层13的整体厚度和／或特性等也影响升温时的叠层型半导体装置1的翘曲量。因为如此之点，所以优选布线基板2的厚度为100～160μm的范围。密封树脂层13的整体厚度虽然也取决于第1半导体芯片6的搭载数量但是优选为750～810μm的范围。而且，在设粘接层7的热膨胀系数为70～470ppm／℃、设常温弹性率（固化后）为2～3GPa的情况下，优选布线基板2的芯材的热膨胀系数为8～10ppm／℃的范围、常温弹性率为30～40GPa的范围，优选密封树脂层13的热膨胀系数为8～10ppm／℃的范围、常温弹性率（固化后）为1～30GPa的范围。由此，可再现性高地抑制升温时的叠层型半导体装置1的翘曲。
实施方式的叠层型半导体装置1例如如以下地制作。关于叠层型半导体装置1的制造工序，参照图5进行说明。如示于图5（a）地，在布线基板2的第2面2b上介由粘接层11粘接第2半导体芯片10。对第2半导体芯片10实施线接合，并对布线基板2的内部电极5和第2半导体芯片10的电极垫介由第2接合线12进行电连接。接下来，如示于图5（b）地，准备在背面（非电路面）形成有粘接剂层14的第1半导体芯片6A。粘接剂层14层使采用了热时粘度为500～5000Pa·s的范围的热固化性树脂的粘接剂形成为层状，成为半固化状态。关于粘接剂层14的形成方法等后述。
虽然在图5（b）中将图示进行了省略，但是电路基板2载置于载物台上，第1半导体芯片6A例如由吸附头保持。第1半导体芯片6A及粘接剂层14例如通过内置于吸附头内的加热机构加热为预定的温度。电路基板2也相应于需要通过内置于载物台的加热机构加热。将加热软化或溶融的粘接剂层14压向电路基板2的第2面2b。此时，粘接剂层14压接于电路基板2以取进第2半导体芯片10。如示于图5（c）地，第2半导体芯片10埋入于粘接剂层14内。因为构成粘接剂层14的粘接剂的热时粘度为500～5000Pa·s的范围，所以能够将第2半导体芯片10良好地埋入于粘接剂层14内。
接下来，如示于图5（d）地，在第1半导体芯片6A上依次层叠第1半导体芯片6B～6D。第1半导体芯片6B～6D介由具有通常的厚度（例如55μm程度）的粘接剂层（面接触接膜（DAF）和／或面接触膏（DAP））15A～15C依次叠层。此后，对粘接剂层14、15A～15C进行固化处理，使得粘接剂层14、15A～15C具有充分的硬度。在采用了热固化性树脂的粘接剂层14、15A～15C的固化处理中，粘接剂在暂时软化或溶融而呈现流动性之后进行固化反应，并由此成为包括具有预定的硬度的热固化性树脂的粘接层7、8A～8C。
此时，若粘接剂层14、15A～15C的加热固化时的流动粘度即软化或溶融而呈现流动性时的粘度过低，则尤其由于粘接剂层14的变形量增大，第1半导体芯片6的翘曲量增加。第1半导体芯片6的翘曲与所述的凸状的变形同样地成为工作不良等的产生原因。因此，在该实施方式中将加热固化时的流动粘度为1000Pa·s以上的粘接剂应用于粘接剂层14。只要粘接剂的加热固化时的流动粘度为1000Pa·s以上，则能够对粘接剂层14的变形乃至第1半导体芯片6的翘曲进行抑制。在加热固化时粘接剂呈现流动性的温度范围例如为60～120℃的范围。
此后，对第1半导体芯片6A～6D实施线接合，并将布线基板2的内部电极5和第1半导体芯片6A～6D的电极垫介由第1接合线9进行电连接。进而，通过在布线基板2的第2面2b上形成将半导体芯片6、10与接合线9、12一起进行密封的密封树脂层13，制作实施方式的叠层型半导体装置1。当对第1半导体芯片6A～6D实施线接合时，若厚度厚的第1粘接层7的固化后的弹性率过低，则接合线9相对于第1半导体芯片6A的连接性会下降。因此，优选第1粘接层7的固化后的弹性率为20MPa以上。
因为在线接合时一般也加热，所以优选第1粘接层7的固化后的弹性率为焊接时的温度例如220～260℃时的热时弹性率。通过使第1粘接层7的热时弹性率成为20MPa以上，能够提高相对于第1半导体芯片6的线接合性。第1粘接层7的热时弹性率例如通过对所述的热固化性树脂组成物中的无机填充材料的含有量等进行调整，能够成为20MPa以上。
接下来，关于具有粘接剂层14的第1半导体芯片6的制作工序，参照图6进行说明。如示于图6（a）地，在具有相当于第1半导体芯片6的多个元件区域X的半导体晶片21的背面（非电路面），通过贴附半固化状态的粘接剂片（面接触膜等）、或者在以喷墨法和／或溅射法涂敷了液状的粘接剂树脂（面接触膏等）之后使之半固化，在单片化后形成成为第1半导体芯片6的粘接剂层14的粘接剂层22。粘接剂层22具有95～150μm的范围的厚度。在粘接剂层22贴附划片带23。即，在半导体晶片21的背面依次层叠粘接剂层22和划片带23。
接下来，通过将半导体晶片21与粘接剂层22一起沿着设置于元件区域X间的划片区域D进行切断，制作单片化的具有粘接剂层14的第1半导体芯片6。半导体晶片21的切断例如采用2轴结构的刀片划片装置即安装于2个旋转轴的2个刀片按同一轨迹行进地构成的刀片划片装置而实施。先行的第1刀片24仅对半导体晶片21的厚度T的一部分进行切削，以后方的第2刀片25对半导体晶片21的残部的厚度和粘接剂层22的厚度整体进行切削。
如示于图6（a）地，以第1刀片24仅对半导体晶片21的厚度T的一部分进行切削。即，第1刀片24仅对半导体晶片21的厚度t1进行切削。在通过第1刀片24进行的切削工序中，半导体晶片21并未完全切断，其一部分（厚度t2部分）在未切削状态下残存。接着，如示于图6（b）地，以第2刀片25将半导体晶片21的残部的厚度t2和粘接剂层22的厚度整体与划片带23的一部分一起进行切削。在第2刀片25，采用刃宽比第1刀片24窄的刀片。
通过以第1刀片24仅对半导体晶片21的一部分的厚度t1进行切削，并以刃宽窄的第2刀片25将半导体晶片21的残部的厚度t2与粘接剂层22一起进行切削，将半导体晶片21与粘接剂层22一起进行切断而单片化。通过应用如此的切断工序（分步骤切断），如示于图6（b）地在半导体晶片21的切断面产生阶差。由此，可抑制碎片的产生。但是，若通过第2刀片25进行的半导体晶片21的切削量不充分，则厚度为95～150μm厚的粘接剂层22的切断性有可能下降。若粘接剂层22的切断不充分，则当从划片带23选取单片化后的半导体芯片6时会产生不良。这是因为第2刀片25的磨损量少，在切削时附着的粘接剂层22的切削屑会过度残留于第2刀片25。
因此，在实施方式中使以第2刀片25进行切削的半导体晶片21的厚度t2若换言之则为以第1刀片24进行了切削之后的半导体晶片21的残部的厚度t2为85μm以上。因为由于使通过第2刀片25进行的半导体晶片21的切削量为85μm以上，第2刀片25在半导体晶片21中适度地磨损，所以能够提高厚度为95～150μm厚的粘接剂层22的切断性。即，为了将包括热固化性树脂组成物的半固化物的粘接剂层22良好地进行切断，需要使第2刀片25在半导体晶片21中适度地磨损。通过使半导体晶片21的残部的厚度t2为85μm以上，第2刀片25的磨损量例如成为0.3μm／m以上，粘接剂层22的切断性提高。
图7是表示通过第1刀片24引起的半导体晶片21的切留量和刀片磨损量及选取不良率的关系的图。由于使通过第1刀片24引起的半导体晶片21的切留量（t2）为85μm以上，刀片磨损量成为0.3μm／m以上。由此，可以防止具有粘接剂层14的半导体芯片6的选取不良的产生。并且，在得到通过分步骤切断带来的碎片的抑制效果的基础上，优选通过第1刀片24进行的半导体晶片21的切削量（t1）为5μm以上。从而，优选实施分步骤切断的半导体晶片21的厚度T为90μm以上，若考虑各公差等则更优选为100μm以上，进一步优选为110μm以上。
此后，采用吸附夹具等从划片带选取单片化的第1半导体芯片6。在第1半导体芯片6的背面，形成有单片化的粘接剂层14。因为粘接剂层22因所述的分步骤切断可靠地单片化，所以能够对基于粘接剂层22的切断不良的选取不良的产生进行抑制。而且，通过应用分步骤切断，能够对碎片的产生进行抑制。即，可以一边对碎片的产生进行抑制，一边对第1半导体芯片6的选取不良的产生进行抑制。具有粘接剂层14的第1半导体芯片6在示于图5（b）的半导体芯片6A的粘接工序中被使用，一边在粘接剂层14内埋入第2半导体芯片10一边粘接于电路基板2。
还有，虽然对本发明的几个实施方式进行了说明，但是，这些实施方式出示为例，并非意图对发明的范围进行限定。这些实施方式能够在其他的各种方式下实施，在不脱离发明的要旨的范围，能够进行各种省略、替换、变更。这些实施方式和／或其变形包括于发明的范围和／或要旨，并包括于记载于权利要求的范围的发明及其等同的范围。

Claims (5)

1.一种叠层型半导体装置，其特征在于，具备：
电路基板，
配置于所述电路基板上的第1半导体芯片，
使所述第1半导体芯片粘合于所述电路基板的粘接层，
至少一部分埋入于所述粘接层内并具有比所述第1半导体芯片小的外形的第2半导体芯片，
对所述电路基板和所述第1半导体芯片进行电连接的第1连接构件，
对所述电路基板和所述第2半导体芯片进行电连接的第2连接构件，和
设置于所述电路基板上用于将所述第1及第2半导体芯片与所述第1及第2连接构件一起进行密封的密封树脂层；
所述第1半导体芯片具有90μm以上的厚度；
所述第2半导体芯片具有75μm以下的厚度；
所述粘接层具有95μm以上且150μm以下的范围的厚度，并且包括当埋入所述第2半导体芯片时的热时粘度为500Pa·s以上且5000Pa·s以下的范围的热固化性树脂；
所述第1半导体芯片上的所述密封树脂层的厚度为190μm以上且440μm以下的范围。
2.一种叠层型半导体装置，其特征在于，具备：
电路基板，
配置于所述电路基板上的第1半导体芯片，
使所述第1半导体芯片粘合于所述电路基板的粘接层，
至少一部分埋入于所述粘接层内并具有比所述第1半导体芯片小的外形的第2半导体芯片，
对所述电路基板和所述第1半导体芯片进行电连接的第1连接构件，
对所述电路基板和所述第2半导体芯片进行电连接的第2连接构件，和
设置于所述电路基板上用于将所述第1及第2半导体芯片与所述第1及第2连接构件一起进行密封的密封树脂层；
所述第2半导体芯片具有75μm以下的厚度；
所述粘接层具有95μm以上且150μm以下的范围的厚度，并且包括当埋入所述第2半导体芯片时的热时粘度为500Pa·s以上且5000Pa·s以下的范围的热固化性树脂。
3.一种叠层型半导体装置的制造方法，其特征在于，包括以下工序：
准备电路基板的工序；
准备第1半导体芯片和具有比所述第1半导体芯片小的外形的第2半导体芯片的工序；
在所述电路基板上搭载所述第2半导体芯片的工序；
介由第1连接构件对所述电路基板和所述第2半导体芯片进行电连接的工序；
边使所述第2半导体芯片的至少一部分埋入于粘接剂内，边以所述粘接剂使所述第1半导体芯片粘合于所述电路基板的工序；
介由第2连接构件对所述电路基板和所述第1半导体芯片进行电连接的工序；和
在所述电路基板上形成将所述第1及第2半导体芯片与所述第1及第2连接构件一起进行密封的密封树脂层的工序；
所述第2半导体芯片具有75μm以下的厚度，并且通过所述粘接剂形成的粘接层具有95μm以上且150μm以下的范围的厚度；
将当埋入所述第2半导体芯片时的热时粘度为500Pa·s以上且5000Pa·s以下的范围的热固化性树脂用作所述粘接剂。
4.根据权利要求3所述的叠层型半导体装置的制造方法，其特征在于：
所述粘接剂在埋入所述第2半导体芯片之后被固化处理；
所述热固化性树脂在加热固化时的流动粘度为1000Pa·s以上。
5.根据权利要求3或4所述的叠层型半导体装置的制造方法，其特征在于，包括以下工序：
准备所述第1半导体芯片的工序；
在半导体晶片的背面依次层叠所述粘接剂层和划片带的工序；
采用第1刀片，仅对所述半导体晶片的厚度的一部分进行切削的工序；
采用刃宽比所述第1刀片窄的第2刀片，对所述半导体晶片的残部的厚度和所述粘接剂层的厚度整体进行切削，并形成具有所述粘接剂层的所述第1半导体芯片的工序；和
从所述划片带选取具有所述粘接剂层的所述第1半导体芯片的工序；
以所述第1刀片进行了切削之后的所述半导体晶片的残部的厚度为85μm以上。
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