CN103380480A - 用于器件集成的硅的低温选择性外延生长 - Google Patents

用于器件集成的硅的低温选择性外延生长 Download PDF

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CN103380480A
CN103380480A CN2012800094652A CN201280009465A CN103380480A CN 103380480 A CN103380480 A CN 103380480A CN 2012800094652 A CN2012800094652 A CN 2012800094652A CN 201280009465 A CN201280009465 A CN 201280009465A CN 103380480 A CN103380480 A CN 103380480A
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silicon
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B·海克麦特朔-塔巴里
A·卡基菲鲁兹
A·雷茨尼采克
D·K·萨达那
G·G·沙希迪
D·沙赫莉亚迪
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Abstract

一种外延方法包括提供（402）衬底材料的暴露的晶体区域。在低温工艺中将硅外延沉积（404）在所述衬底材料上，其中沉积温度低于500摄氏度。用稀释气体稀释（408）源气体，其中稀释气体与源气体的气体比小于1000。

Description

用于器件集成的硅的低温选择性外延生长
技术领域
本发明涉及半导体加工，更具体地涉及低温外延生长工艺。
背景技术
重掺杂的硅的选择性外延生长（SEG）适合应用于提升的（raised）源极/漏极（S/D）区中以减小与浅掺杂的S/D区相关联的寄生串联电阻。然而，用于硅的SEG的常规方法需要高温处理。典型的处理温度大于600°C。
高温要求限制了能够利用用于Si的SEG的常规方法的工艺和应用。此外，用于硅的外延生长的常规高温沉积（超过600摄氏度）缺乏Si在预定区域上的选择性生长，所述预定区域例如是c-Si的暴露区域。
发明内容
一种外延方法包括提供衬底材料的暴露的晶体区域。在低温工艺中在所述衬底材料上外延沉积硅，其中沉积温度低于500摄氏度。用稀释气体稀释源气体，其中稀释气体与源气体的气体比小于1000。
另一种外延方法包括：提供晶体衬底材料；在所述衬底材料上生长绝缘体；对所述绝缘体开口以形成所述衬底材料的暴露区域；在低温工艺中在所述衬底材料的所述暴露区域上沉积硅以在所述暴露区域上形成外延硅并且在非暴露区域上形成非外延硅，其中沉积温度低于500摄氏度；以及使用等离子体蚀刻所述非外延硅，以在所述暴露区域之上进一步外延沉积硅。
另一种外延方法包括：提供衬底材料的暴露的晶体区域，以及通过用H2稀释硅烷，在低温工艺中在所述衬底材料上选择性地外延沉积硅，其中沉积温度低于500摄氏度，稀释气体与源气体的气体比小于1000。
通过下文中对其示例性实施例的详细描述，这些和其它特征及优点将变得显而易见，所述详细描述要结合附图阅读。
附图说明
本公开将参考以下附图在优选实施例的以下描述中提供细节，在附图中：
图1是根据一个实施例使用选择性外延生长形成的具有提升的源极/漏极区的示例性半导体器件的横截面视图；
图2A是示出了根据一个实施例的薄层电阻（sheet resistance）与[PH3]/[SiH4]的气体比之间的关系的图，示出了三个示例性样品；
图2B是示出图2A的三个样品的原子浓度与深度之间的关系的图，并且该图还示出了根据一个实例的P浓度和PH3流量之间的线性关系；
图3A是根据一个实施例具有在低温工艺中与非外延层一起形成的选择性外延层的器件的横截面视图；
图3B是根据一个实施例的、使非外延层被蚀刻以进一步形成选择性外延层的图3A中的器件的横截面视图；
图3C是根据一个实施例的、在非外延层已经被完全蚀刻之后的图3B中的器件的横截面视图；
图4是示出根据本发明原理用于选择性外延生长的示例性方法的框图/流程图；以及
图5是示出根据本发明原理使用蚀刻进行选择性外延生长的另一示例性方法的框图/流程图。
具体实施方式
根据本发明原理，公开了在低温下进行重掺杂硅的选择性外延生长的方法。在特别有用的实施例中，使用等离子体增强化学气相沉积（PECVD）实现了低至150°C的生长温度。通过增加和优化[H2]/[SiH4]的气体比，获得该外延生长。在另一个实施例中，通过例如使用PH3气体来包含磷，生长N+掺杂的硅。
例如大于1×1020cm-3的高度掺杂剂激活可以在150°C下获得。通过在H2等离子体中蚀刻在晶体-Si（c-Si）未暴露的区域上的沉积的硅，提供选择性生长。因此，本实施例提供了Si的不中断的选择性外延生长（SEG），其中非外延Si的外延生长和等离子体蚀刻在同一反应器中发生。使用本方法，掺硼的Si或其它掺杂剂的选择性外延生长也是可能的。
根据本发明原理的低温工艺开启了诸如下述应用的很多应用的可能性：器件的三维（3D）集成；在绝缘体上极薄半导体（ETSOI）、部分耗尽的SOI（PDSOI）、体硅衬底等上制造的晶体管的提升的源极/漏极（S/D）区；以及其它应用。
等离子体增强化学气相沉积（PECVD）也可以被用于非晶、微晶、多晶的低温沉积以及在低于300°C的温度下在c-Si衬底上的硅的外延生长。
附图中的流程图和框图示出了本发明各种实施例的可能实施方式的架构、功能和操作。应当注意，在一些备选实施方式中，框中标注的功能可以不按图中示出的顺序发生。例如，连续示出的两个框实际上可以基本上同时被执行，或者这些框有时可以以相反的顺序被执行，这取决于所涉及的功能。还应当注意，框图和/或流程示例中的每一个框，以及框图和/或流程示例中框的组合，可以由执行特定功能或动作的专用的基于硬件的系统或者由专用硬件与指令的组合实现。
应当理解，将就使用硅的给定示例性构造来描述本发明；然而，其它构造、结构、衬底材料以及工艺特征和步骤可以在本发明的范围内变化。
此处描述的器件可以是集成电路芯片设计的一部分。芯片设计可以在图形计算机编程语言中产生，并且被存储在计算机存储介质（例如盘、带、物理硬盘驱动器、或诸如存储访问网络（Storage Access Network）的虚拟硬盘驱动器）中。如果设计者不制造芯片或者用于制造芯片的光刻掩模，则设计者可以直接或间接将所产生的设计通过物理手段（例如，通过提供一份存储有该设计的存储介质）或电子地（例如通过互联网）传送到这种实体。然后，所存储的设计可以被转换成适当的格式（例如，GDSII），以制造光刻掩模，光刻掩模典型地包含要形成在晶片上的多份所讨论的芯片设计。光刻掩模可用于限定晶片（和/或其上的层）的要蚀刻的或者要处理的区域。
此处描述的方法可以用于制造集成电路芯片。所得到的集成电路芯片可以以原始晶片的形式（即，作为具有多个未封装的芯片的单个晶片）、作为裸管芯或者以封装的形式由制造商分配。在后一种情况下，芯片被安装在单芯片封装体（例如塑料载体，具有固定到母板或其它更高级别的载体上的引线）中或者被安装在多芯片封装体（例如，具有表面互连或掩埋互连、或者具有表面互连和掩埋互连二者的陶瓷载体）中。在任何一种情况下，所述芯片然后可以作为（a）诸如母板的中间产品或（b）最终产品的一部分，与其它芯片、分立电路元件和/或其它信号处理装置集成。所述最终产品可以是包括集成电路芯片的任何产品，范围从玩具和其它低端应用到具有显示器、键盘或其它输入装置以及中央处理器的高级计算机产品。
现在参考其中相似的附图标记代表相同或相似的要素的附图并且首先参考图1，器件或晶片100包括衬底102，其中将应用根据本发明原理的方法。衬底102可以包括例如体单晶硅衬底、绝缘体上半导体（SOI）、极薄SOI（ETSOI）衬底、部分耗尽的SOI（PDSOI）衬底或其它衬底。其它衬底可以包括Ge、III-V衬底（例如GaAs）等。在本实施例中，硅是优选的用于外延生长的衬底材料；然而，根据本发明原理，也可以采用其它晶体衬底材料。
器件100可以被用于三维（3D）集成应用中或者需要外延生长来形成部件层的其它应用中。在特别有用的实施例中，采用外延生长来形成晶体管的提升的源极/漏极（S/D）区。本实施例将示例性地描述形成提升的S/D区，但本发明原理也适用于任何外延生长和蚀刻应用。
形成包括栅极绝缘体108（例如氧化物）、栅极导体110（例如，掺杂的多晶硅）和隔离物（spacer）112（例如，氮化物）的栅极结构106。也可以采用其它栅极结构和材料。图1示例性地示出了有刻面的（faceted）S/D区120，但S/D区120不必是有刻面的。通过外延生长形成S/D区120。该外延生长可以包括在硅衬底102的预定区域上的在低至150摄氏度的温度下的重掺杂或未掺杂的硅。在晶体硅（c-Si）暴露的地方这是优选的，因此选择性外延生长。
在一个实施例中，使用等离子体增强化学气相沉积工艺（PEVCD）在氢气稀释的硅烷环境中进行硅的选择性外延生长。在150摄氏度下氢气与硅烷气体的气体比（[H2]/[SiH4]）优选为0至约1000。在特别有用的实施例中，硅的外延生长在约5-10的气体比下开始。通过将氢气稀释度增加到例如5或更大，改善外延Si的质量。
可以使用各种气体源，例如，硅烷(SiH4)、二氯甲硅烷（DCS）、SiF4、SiCl4等，来生长外延硅。使用这些或其它气体，通过增加氢气的稀释度，改善外延硅的质量。对于更高的氢气稀释度，产生更平滑的界面（外延硅到晶体硅）并且观察到更少的堆垛层错和其它缺陷。
射频（RF）或直流（DC）等离子体增强化学气相沉积（CVD）优选在从约室温到约500摄氏度的沉积温度范围下进行，并且优选在从约150摄氏度到约250摄氏度的沉积温度范围下进行。等离子体功率密度的范围可以为约2mW/cm2到约2000mW/cm2。沉积压力范围可以为约10mtorr到约5torr。
在一个实施例中，高度掺杂剂激活可以在低至150摄氏度的温度下获得。这使得本发明的方法对于3D集成和提升的S/D制造中的应用有吸引力。外延Si可以包含例如碳、锗、磷、砷、硼等。低温外延Si可以生长在诸如Si、Ge和III-V的不同的衬底上。例如，本发明人根据本发明原理在约200摄氏度下将外延硅层生长在GaAs上。
参考图2A，示出了对于各种PH3气体流量，掺磷的外延硅（epi-Si）的薄层电阻率。对于各种PH3气体流量掺杂的～40-50nm厚的epi-Si的薄层电阻率表明硅中的高度掺杂剂激活。氢气与硅烷气体的比率为14。对被标记为1、2和3的样品进行二次离子质谱法（SIMS）。
图2B示出了样品1、2和3的P浓度（原子/cm3）与深度（nm）的关系。P浓度与PH3呈线性比例关系（见插图210）。从样品1和2的薄层电阻率测量得到的电活性掺杂剂的对应水平与由SIMS数据给出的实际掺杂剂浓度一致。然而，对于样品3，电活性的掺杂剂的浓度远低于总的所包含的掺杂剂，这从图2B的SIMS分析显而易见。对于样品3，通过增加[PH3]/[SiH4]，硅的外延生长被打断，并且硅的非外延相开始生长。对于包含硼的情况，获得了类似的结果。应当理解，如果期望，则掺杂剂气体浓度应当保持为低于阈值气体比，以避免非晶体硅相或者提供非外延相。关于图2B，该阈值似乎大约是约5-8的[PH3]/[SiH4]的气体比。其它气体/掺杂剂工艺具有其它阈值。
参考图3A-3C，在另一个实施例中，可以通过在H2等离子体308中原位蚀刻非外延硅来获得衬底304的预定区域上的外延硅302的选择性生长。采用非晶硅的蚀刻工艺来在暴露的晶体硅区域上同时形成外延硅。应当理解，外延生长和蚀刻可以根据需要顺序地或同时地执行。在图3A中，在形成于衬底304上的绝缘体（例如，氧化硅（SiO2））层306中打开窗口312。在例如500mTorr、[H2]/[SiH4]=14并且功率密度为4mW/cm2的情况下，沉积硅302。结果，硅302在窗口区域312中外延，其中在窗口区域312，硅302暴露于衬底304的c-Si。绝缘体（例如氧化物）306上硅形成为非外延（例如非晶）硅310。
在图3B中，在900mtorr在150摄氏度下进行H2等离子体蚀刻308，得到c-Si304相对于a-Si:H310的近似1:3的蚀刻选择率。图3C示出了选择性外延硅302并且非外延（在这种情况下，非晶）Si310被去除。应当理解，可以使用诸如例如H2、HCl、Cl2、Ar等的气体来蚀刻生长在绝缘体306上的非外延部分（非晶Si310）。外延沉积和H2等离子体蚀刻可以在同一腔内顺序地或同时地进行。可以通过使负责外延生长的气体脉冲（例如，硅烷和掺杂剂物类（species））和蚀刻（等离子体蚀刻剂，例如H2、HCl等）或者通过使所有气体同时流动，来实现选择性外延生长。
参考图4，示例性地示出了用于选择性外延生长的方法。在框402中，提供衬底材料的暴露的晶体区域。这可以包括在电介质层中打开窗口或者对衬底上的层进行构图。衬底材料可以包括Si、Ge、III-V材料等。
在框404中，在低温工艺中将硅外延沉积在衬底材料上，其中沉积温度低于500摄氏度，并且优选地低于250摄氏度。该工艺对于衬底的暴露区域是选择性的。该工艺优选包括射频或直流等离子体增强化学气相沉积工艺。
在框408中，用包含H2、HCl、Cl2和Ar中的至少一种的稀释气体稀释源气体，其中稀释气体与源气体的气体比小于1000。源气体可以包括SiH4、二氯甲硅烷（DCS）、SiF4或SiCl4中的一种。在一个特别有用的实施例中，与H2一起使用SiH4，其中气体比[H2]/[SiH4]大于5。
在框410中，可以用提供掺杂的外延硅的气体比引入一个或多个掺杂剂物类。掺杂的外延硅可以包含碳、锗、磷、砷或硼中的至少一种。
参考图5，示例性地示出了用于选择性外延生长的另一种方法，该方法采用例如RF或DC等离子体增强化学气相沉积工艺。在框502中，提供晶体衬底材料。衬底材料可以包括Si、Ge、III-V材料等。在框504中，在衬底材料上生长氧化物或绝缘体。在框506中，绝缘体（例如，氧化物）被开口或被构图，以形成衬底材料的暴露区域。
在框512中，在低温工艺（例如，沉积温度低于500摄氏度，并且更优选地，低于250摄氏度）中在衬底材料的暴露区域上沉积硅以在暴露区域上形成外延硅并且在非暴露区上形成非外延硅。在框514中，硅沉积包括用包括H2、HCl、Cl2和Ar中的至少一种的稀释气体稀释源气体，其中稀释气体与源气体的气体比小于1000，其中源气体包括SiH4、二氯甲硅烷（DCS）、SiF4或SiCl4中的一种。
在框516中，使用等离子体选择性地蚀刻非外延（例如非晶或多晶）硅，并且在暴露区域之上进行硅的进一步外延沉积。等离子体可以包括H2、HCl、Cl2或Ar中的至少一种。
在框518中，可以用提供掺杂的外延硅的气体比引入一个或多个掺杂剂类。掺杂的外延硅可以包括碳、锗、磷、砷或硼中的至少一种。在框520中，通过使沉积和蚀刻步骤交替，或者同时进行沉积和蚀刻，提供选择性的外延生长。
已经描述了用于器件集成的硅的超低温选择性外延生长的优选实施例（这些优选实施例旨在为示例性的而非限制性的），应注意，本领域技术人员可以根据上述教导作出修改和改变。因此，应理解，可以在由所附权利要求书限定的本发明的范围内对所公开的特定实施例作出改变。已经由此以由专利法要求的详细说明和细节描述了本发明的各方面，所要求保护以及期望专利证书予以保护的内容在所附权利要求书中进行了阐述。

Claims (25)

1.一种外延方法，包括：
提供衬底材料的暴露的晶体区域；以及
通过用包括H2、HCl、Cl2和Ar中的至少一种的稀释气体稀释源气体，在低温工艺中在所述衬底材料上外延沉积硅，其中沉积温度低于500摄氏度，稀释气体与源气体的气体比小于1000。
2.根据权利要求1所述的方法，其中所述外延沉积硅包括射频或直流等离子体增强化学气相沉积工艺。
3.根据权利要求1所述的方法，其中所述源气体包括SiH4、二氯甲硅烷（DCS）、SiF4或SiCl4中的一种。
4.根据权利要求1所述的方法，其中所述沉积温度低于250摄氏度。
5.根据权利要求1所述的方法，其中所述衬底材料包括Si、Ge和III-V材料中的一种。
6.根据权利要求1所述的方法，其中稀释包括以大于5的气体比用H2稀释SiH4。
7.根据权利要求1所述的方法，还包括以提供掺杂的外延硅的气体比引入掺杂剂。
8.根据权利要求7所述的方法，其中所述掺杂的外延硅包括碳、锗、磷、砷或硼中的至少一种。
9.一种外延方法，包括：
提供晶体衬底材料；
在所述衬底材料上生长绝缘体；
对所述绝缘体开口以形成所述衬底材料的暴露区域；
在低温工艺中在所述衬底材料的所述暴露区域上沉积硅以在所述暴露区域上形成外延硅并且在非暴露区域上形成非外延硅，其中沉积温度低于500摄氏度；以及
使用等离子体蚀刻所述非外延硅，以在所述暴露区域之上进一步外延沉积硅。
10.根据权利要求9所述的方法，其中沉积硅包括射频或直流等离子体增强化学气相沉积工艺。
11.根据权利要求9所述的方法，其中沉积硅包括用包括H2、HCl、Cl2和Ar中的至少一种的稀释气体稀释源气体，其中稀释气体与源气体的气体比小于1000，其中所述源气体包括SiH4、二氯甲硅烷（DCS）、SiF4或SiCl4中的一种。
12.根据权利要求11所述的方法，其中稀释包括以大于5的气体比用H2中的至少一种稀释SiH4。
13.根据权利要求9所述的方法，其中所述沉积温度低于250摄氏度。
14.根据权利要求9所述的方法，其中所述衬底材料包括Si、Ge和III-V材料中的一种。
15.根据权利要求9所述的方法，还包括以提供掺杂的外延硅的气体比引入掺杂剂。
16.根据权利要求15所述的方法，其中所述掺杂的外延硅包括碳、锗、磷、砷或硼中的至少一种。
17.根据权利要求9所述的方法，其中所述等离子体包括H2、HCl、Cl2或Ar中的至少一种。
18.根据权利要求9所述的方法，其中通过使所述沉积和蚀刻步骤交替来提供选择性外延生长。
19.根据权利要求9所述的方法，其中沉积和蚀刻的步骤同时进行。
20.一种外延方法，包括：
提供衬底材料的暴露的晶体区域；以及
通过用H2稀释硅烷，在低温工艺中在所述衬底材料上选择性地外延沉积硅，其中沉积温度低于500摄氏度，稀释气体与源气体的气体比小于1000。
21.根据权利要求20所述的方法，其中所述外延沉积硅包括射频或直流等离子体增强化学气相沉积工艺。
22.根据权利要求20所述的方法，其中所述衬底材料包括Si、Ge和III-V材料中的一种。
23.根据权利要求20所述的方法，还包括以提供掺杂的外延硅的气体比引入掺杂剂。
24.根据权利要求23所述的方法，其中所述掺杂的外延硅包括碳、锗、磷、砷或硼中的至少一种。
25.根据权利要求20所述的方法，其中所述沉积温度低于150度。
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