TW200947725A - Improved HIT solar cell structure - Google Patents

Abstract

The present invention relates to improved HIT type or polysilicon emitter solar cells. According to certain aspects, the invention includes forming a masking oxide layer on the front and back of the cell and then patterning holes in the masking oxide. A HIT cell structure or polysilicon emitter solar cell structure is then formed over the patterned oxide, creating the cell junction only in the areas where holes have been cut. Benefits of the invention include that it provides a controlled interface for the HIT cell through insertion of a thin tunnel oxide. Moreover, the tunnel oxide prevents epitaxial growth of amorphous silicon, allowing it to remain amorphous for the optimum band structure. Still further, it provides a layer to protect the surface from plasma damage during deposition of the a-Si layer. Further, it may be used in conjunction with a point contact structure to further increase efficiency.

Description

200947725 VI. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to photovoltaic devices, and more particularly to methods and apparatus for providing improved structures for providing or employing polycrystalline solar cells. [Prior Art] The HIT type solar cell is a highly efficient device having a relatively simple structure.曰 Ben Sanyo has proposed a laboratory efficiency of 215 〇 / 〇, and a manufacturing efficiency of medium 19 . /. Within the scope. There are many other teams that have also studied this device, but still have not seen it to be efficient. A typical HIT solar cell structure is illustrated in Figures 1A and 1B. The apparatus is symmetrical, and the front and back of the n-type substrate 106 are coated with respective coatings 102, 110 and respective metal grid lines 1〇4, 1〇8. ❹ As shown in the exploded view in Figure 1, the coating 1〇2 on the front is composed of two layers of amorphous germanium (a p-type layer 124 and the underlying layer 126). thick. On the back, the amorphous tantalum layer consists of an n-type layer and one of the underlying layers (i) below it. As shown in Figure 1, the coating 102 also includes a layer of transparent conductive oxide (TCO) 122. A thin alpha-Si layer is used to protect the surface and provide a heterojunction to a wide bandgap window layer to enhance the turn-on circuit voltage, as shown in Figure 1C. More specifically, the ic diagram illustrates the energy band structure of such a device. As shown in Figure ic, 200947725, 'has a large energy level at the front surface, resulting in a junction that is very similar to the junction between the p-type and the type of dopant. However, because this junction is It is formed by a deposited-amorphous layer, so it is very incoherent and almost imaginary. Despite its advantages, these amorphous germanium layers can also produce considerable complexity in the manufacture of HIT cells. For example, these The layer must be formed on a carefully prepared surface, the details of which are not disclosed. 〇 & external ' ^ must not be crystallized, but this will occur when the crystalline enamel substrate is seeded with amorphous germanium, and This eliminates the advantageous protection and heterojunction effects. Therefore, there is a need for an improved interface that can be well controlled and understood, and that is easy to manufacture, and that does not grow crystallize. [Invention] The present invention relates to an improved HIT type or polysilicon. Emitter solar power © cell. According to a particular aspect, the invention includes forming a masking oxide layer on the front and back of the cell, and then patterning the hole in the masking oxide, and then Forming a Hit cell structure or a polysilicon emitter solar cell structure on the cased oxide, creating a cell junction only in the region where the hole has been cut. Advantages of the invention include that it is provided by thin insertion of oxides A controlled interface of the HIT battery. In addition, the tunneling oxide prevents the epitaxial growth of the amorphous germanium, keeping it amorphous for the best energy band structure. Moreover, it provides a layer for 5 200947725 Amorphous tantalum layer (α-Si) protects the surface from plasma damage during deposition. In addition, the use of point contact structures can be combined to further improve efficiency. Further, in these and other aspects, According to an embodiment of the present invention, a solar cell includes an amorphous semiconductor layer formed on a substrate, and a dielectric layer 'interposed between the substrate and the amorphous semiconductor layer> wherein the dielectric The layer is sufficiently thin to support tunneling current through one of the layers. Further, in these and other aspects, a method for fabricating a solar cell according to an embodiment of the present invention includes a substrate Forming a dielectric layer on the plate, wherein the dielectric layer is sufficiently thin to support a tunneling current through one of the dielectric layers; and forming an amorphous semiconductor layer on the dielectric layer. [Embodiment] Reference will be made to the following drawings. The present invention is described in detail to illustrate the embodiments of the invention, and the embodiments of the invention are The embodiments, but by the replacement of some or all of the description elements, also make other embodiments possible. Furthermore, the specific elements of the invention may be implemented partially or completely with conventional components, only those of which are described herein. The detailed description and other parts of the conventional components are omitted to avoid obscuring the present invention. In the specification, the description of a single component embodiment should not be considered as a limitation. Conversely, the invention is intended to cover other embodiments (including vice versa) including a plurality of identical components, unless otherwise indicated. In the meantime, any terms used by the applicant in the specification or the scope of the patent application are not uncommon or special meanings unless otherwise indicated. Furthermore, the present invention encompasses both existing and future equivalents equivalent to the conventional components described. In general, the present invention recognizes that a thin tunneling oxide layer can be used in solar cells; for example, some of the MIS cells can be fabricated by tunneling the aluminum on the oxide. The present invention also recognizes that a tunneling oxide can be used between a heavily doped or polycrystalline tantalum insulating layer and a crystalline germanium substrate to form a polycrystalline germanium emitter solar cell. This solar cell has an energy band structure similar to that of a tantalum battery which is essentially a polycrystalline germanium substituted for the TC〇 and a_Si layers. However, due to the high band gap of a_Si, this battery does not provide the advantage of a heterojunction and its high battery voltage. An example solar cell structure and its associated © energy band structure are shown in Figures 2A and 2B, respectively, in accordance with an embodiment of the present invention. As shown in Fig. 2A, a portion of the front surface of a HIT-type solar cell similar to that shown in the first circle, 'a thin dielectric & 228 (e.g., an oxide with an oxide) is provided in the core layer of the HIT cell. Between the 224 226 and the η substrate 206. The dielectric layer is preferably as thin as 8 ΐ 5 , to support the tunneling current between the substrate and the a-Si layer. As will be described in more detail below, the method can be used to form a layer in a certain two conditions, such as rapid thermal oxidation, furnace tube oxidation or mox treatment (formed in ozonated H2〇2 bath). It can be formed by nitriding or by using other materials such as nitriding 7 200947725 or nitrous oxide. As shown in Figure 2B, the additional dielectric layer at the interface provides a band gap with a larger band gap of the conductor, and the carrier cannot cross the energy barrier 'but when the layer is thin enough (<15A) ), the carrier will tunnel through it. The oxides and nitrides have a barrier height of *Sha, so the layer shown is not specifically representative of any material. The barrier height of the nitride is approximately symmetrical, and the barrier height of the oxide is asymmetrical (lower for electrons). 介 The advantages provided by the dielectric layer 228 are several. For example, it is formed by a conventional surface cleaning and preparation method for generating a MOS gate of an integrated circuit; therefore, this surface preparation method is widely known and understood, and can be manufactured in a high-volume manner. Habitually implemented. At the same time, since it is an amorphous layer, it separates the subsequent α-Si layer from the substrate, thereby avoiding epitaxial seed crystal growth in the α-Si layer. In addition, it provides an intervening layer to protect the surface of the crystalline crucible from ruthenium plasma during the deposition of the alpha-Si layer. It should be noted that although the advantages of the present invention are obtained by the "-Si layer formed on the crystalline germanium substrate, it is not limited, and the present invention is also applicable to other types of substrates and thin semiconductor layers. It is further understood that many solar cells use heterojunctions, so that, for example, the invention can also be used with thin tantalum solar cells having amorphous germanium on the microcrystalline germanium. The invention is also applicable to CdTe, CIGS or A1/GaAs/GaAs batteries, all using a heterojunction. That is, it should be further noted that the amorphous germanium above the crucible is known to provide excellent protection properties of 8 200947725, which virtually eliminates surface recombination. This is because the high energy band at the surface bends to repel the carrier. Therefore, this is an advantage of using an amorphous germanium on the crucible. Ο

Figure 3 is an exemplary flow chart for forming the structure of the second figure. First, the front surface of the n-type substrate is 'textured' in step S302. It can be done using conventional etching, such as isopropyl alcohol and KOH. Next, in step S304, the surface is subjected to standard m〇S clean to remove natural oxides, ionic contaminants and organic matter. In an embodiment, a rapid thermal oxidation treatment is then employed in step S306 to form a thin tunneling oxide on the front surface, which is typically 12 people thick. In another embodiment of the invention, the oxide is formed simultaneously on the front and back. Next, an a-Si layer is deposited on the front surface. In one embodiment, the 'a-Si layer is formed as a two-layer stack on the front surface, one of which is a 20-50 A thick intrinsic a-Si layer first formed in step S308, which is enhanced by, for example, plasma Chemical vapor deposition (PE-C VD ) is usually formed in the presence of gas, and plasma enhanced chemical vapor deposition is the decomposition of decane in electricity. These procedures are fully known from the literature. Boron may be added to provide P-type doping, and phosphorus may be added to provide n-type doping. Next, in step S312, 20-50 A thick p-type ?-Si is formed on top of the essential a_si layer by, for example, the same pE_CVD procedure. In another embodiment, only in step S310, a doped p-type layer is formed on the front surface without forming a type 1 layer. A TCO is deposited in step S304, which may be a quarter wave thick layer of yttrium tin oxide. The wafer is then inverted&apos; as shown in step S316, and in the same manner, 9 200947725 replaces the p-type a-Si layer with an n-type a-Si layer to deposit a structure on the back side. As shown in the figure, depending on whether or not the oxide layer has been formed, the program returns to step S306 or step S308. It should be further understood that the process may also return to step S31 when the oxide layer has been formed. Finally, a contact is formed in step S3108 by, for example, a screen printing or sputtering process. In addition to the above-described procedures, a method of forming a point contact for forming a HIT or a polycrystalline erbium emitter solar cell as described in the co-pending application (N0.) _ II» ^ may also be incorporated herein by reference. Although the present invention has been described with reference to the preferred embodiments thereof, it will be apparent to those skilled in the art that the form and details may be modified and modified without departing from the spirit and scope of the invention. The scope of the patent application is intended to cover such variations and modifications. BRIEF DESCRIPTION OF THE DRAWINGS The above and other aspects and features of the present invention will become apparent to those skilled in the <RTIgt; A conventional HIT battery and its energy band structure; FIGS. 2A and 2B respectively illustrate an exemplary solar cell structure and its energy band structure of the present invention; and FIG. 3 is used to form the structure of FIG. 2 according to the aspect of the present invention. An example flow chart. [Main component symbol description] 200947725 102 coating 104 metal grid 106 n-type substrate 108 metal grid 11 0 coating 122 transparent conductive oxide (TCO) 124 p-type layer 126 essential layer 224 α-Si layer 226 a-Si Layer 228 Dielectric Layer S302-S318 Step 206 η-type Substrate ❹ ❿ 11

Claims (1)

200947725 VII. Patent application scope: 1. A solar cell comprising: an amorphous semiconductor layer formed on a substrate; and a dielectric layer interposed between the substrate and the amorphous semiconductor layer 'The dielectric layer is thin enough to support a tunneling current therethrough. 2. The solar cell of claim 1, wherein the substrate comprises ruthenium&apos; and the dielectric layer comprises ruthenium dioxide. 3. The solar cell of claim 1, wherein the substrate comprises germanium and the dielectric layer comprises nitrogen. 4. The solar cell of claim 1, wherein the non-crystalline semiconductor layer comprises a chip. 5. The solar cell of claim 1, wherein the non-crystalline semiconductor layer comprises a two-layer stack of an intrinsic amorphous germanium layer and a doped amorphous germanium layer. 6. The solar cell of claim 1, wherein the amorphous semiconductor layer is formed on a front surface of the substrate, wherein the solar cell further comprises: 12 200947725 another amorphous semiconductor layer, Formed on an opposite back side surface of the substrate; and another dielectric layer interposed between the substrate and the another amorphous conductor layer, wherein the other dielectric layer is sufficiently thin to support A tunneling current through it. The solar cell of claim 6, wherein the non-crystalline semiconductor layer and the other amorphous semiconductor layer comprise an intrinsic amorphous germanium layer and a doped amorphous germanium layer. A two-layer stack of layers. 8. A method of fabricating a solar cell, comprising: forming a dielectric layer on a substrate, wherein the dielectric layer is sufficiently thin to support a tunneling current therethrough; and forming an amorphous semiconductor layer On the dielectric layer. The method of claim 8, wherein the step of forming the amorphous semiconductor layer comprises forming a two-layer stack of an intrinsic amorphous germanium layer and a doped amorphous germanium layer. 10. The method of claim 8, further comprising: "texturing" a surface of the substrate before forming the dielectric layer. The method of claim 8 is as described in claim 8 The dielectric layer is formed using a fast 13 200947725 rapid thermal oxidation process. 12. The method of claim 1, wherein the essence and the doped amorphous germanium layer are both about 20-5 Å thick. 13. The method of claim 8, further comprising depositing a TCO layer on the amorphous semiconductor layer. 14. The method of claim 13, wherein the indium oxide is a quart layer of indium tin oxide. TCO thick 15. The method of claim 8, wherein the semiconductor layer is formed on a front surface of the substrate, wherein the amorphous material is more Φ Φ - έ * a . An electric layer is formed to be thin enough to support a % layer and to form a further amorphous semiconductor layer on the other dielectric layer by a tunneling current therebetween.