CN103076558B - 用于扫描链的动态时钟域旁路 - Google Patents

用于扫描链的动态时钟域旁路 Download PDF

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Publication number
CN103076558B
CN103076558B CN201210208775.9A CN201210208775A CN103076558B CN 103076558 B CN103076558 B CN 103076558B CN 201210208775 A CN201210208775 A CN 201210208775A CN 103076558 B CN103076558 B CN 103076558B
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China
Prior art keywords
bypass
subchain
scan
clock
clock zone
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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CN201210208775.9A
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English (en)
Chinese (zh)
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CN103076558A (zh
Inventor
R·C·泰库玛拉
P·库玛
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Avago Technologies International Sales Pte Ltd
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Avago Technologies Fiber IP Singapore Pte Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201210208775.9A 2011-10-25 2012-06-19 用于扫描链的动态时钟域旁路 Expired - Fee Related CN103076558B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/280,797 US8812921B2 (en) 2011-10-25 2011-10-25 Dynamic clock domain bypass for scan chains
US13/280,797 2011-10-25

Publications (2)

Publication Number Publication Date
CN103076558A CN103076558A (zh) 2013-05-01
CN103076558B true CN103076558B (zh) 2017-04-12

Family

ID=47263057

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210208775.9A Expired - Fee Related CN103076558B (zh) 2011-10-25 2012-06-19 用于扫描链的动态时钟域旁路

Country Status (6)

Country Link
US (1) US8812921B2 (https=)
EP (1) EP2587273A1 (https=)
JP (1) JP2013092517A (https=)
KR (1) KR20130045158A (https=)
CN (1) CN103076558B (https=)
TW (1) TW201317596A (https=)

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JP6130239B2 (ja) * 2013-06-20 2017-05-17 ラピスセミコンダクタ株式会社 半導体装置、表示装置、及び信号取込方法
GB2520506B (en) * 2013-11-21 2020-07-29 Advanced Risc Mach Ltd Partial Scan Cell
US20160061892A1 (en) * 2014-08-29 2016-03-03 Qualcomm Incorporated Scan programmable register controlled clock architecture for testing asynchronous domains
CN104749515B (zh) * 2015-03-31 2017-12-15 中国人民解放军国防科学技术大学 一种基于顺序等分分段式的低功耗扫描测试方法和装置
US10436837B2 (en) * 2015-10-19 2019-10-08 Globalfoundries Inc. Auto test grouping/clock sequencing for at-speed test
TWI646845B (zh) * 2016-05-19 2019-01-01 晨星半導體股份有限公司 條件式存取晶片、其內建自我測試電路及測試方法
US10048315B2 (en) * 2016-07-06 2018-08-14 Stmicroelectronics International N.V. Stuck-at fault detection on the clock tree buffers of a clock source
US10317464B2 (en) * 2017-05-08 2019-06-11 Xilinx, Inc. Dynamic scan chain reconfiguration in an integrated circuit
CN110514981B (zh) * 2018-05-22 2022-04-12 龙芯中科技术股份有限公司 集成电路的时钟控制方法、装置及集成电路
US11614487B2 (en) * 2019-01-30 2023-03-28 Siemens Industry Software Inc. Multi-capture at-speed scan test based on a slow clock signal
CN109857024B (zh) * 2019-02-01 2021-11-12 京微齐力(北京)科技有限公司 人工智能模块的单元性能测试方法和系统芯片
TWI689738B (zh) * 2019-02-21 2020-04-01 瑞昱半導體股份有限公司 測試系統
IT202000001636A1 (it) * 2020-01-28 2021-07-28 Stmicroelectronics Shenzhen R&D Co Ltd Circuito elettronico e corrispondente procedimento per testare circuiti elettronici
JP7305583B2 (ja) * 2020-03-05 2023-07-10 株式会社東芝 半導体集積回路
US11342914B2 (en) * 2020-06-19 2022-05-24 Juniper Networks, Inc. Integrated circuit having state machine-driven flops in wrapper chains for device testing
CN112183005B (zh) * 2020-09-29 2022-11-11 飞腾信息技术有限公司 集成电路测试模式下的dft电路构建方法及应用
CN112526328B (zh) * 2020-10-28 2022-11-01 深圳市紫光同创电子有限公司 边界扫描测试方法
US11454671B1 (en) * 2021-06-30 2022-09-27 Apple Inc. Data gating using scan enable pin
US11680982B2 (en) * 2021-10-26 2023-06-20 Stmicroelectronics International N.V. Automatic test pattern generation circuitry in multi power domain system on a chip
CN114091393B (zh) * 2021-11-26 2025-09-26 芯盟科技有限公司 一种执行工程变更指令的方法、装置、设备和存储介质
KR102670130B1 (ko) * 2021-12-29 2024-05-27 연세대학교 산학협력단 스캔 체인의 다중 고장 진단장치 및 방법
JP2024063970A (ja) * 2022-10-27 2024-05-14 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置のスキャンテスト方法
US12306246B2 (en) 2023-08-21 2025-05-20 Stmicroelectronics International N.V. Partial chain reconfiguration for test time reduction
US12493076B2 (en) * 2023-09-20 2025-12-09 Apple Inc. Scan data transfer circuits for multi-die chip testing
CN118332979B (zh) * 2024-06-11 2024-08-20 奇捷科技(深圳)有限公司 一种在ECO中使用Scan DEF文件的方法
CN120104412B (zh) * 2025-05-07 2025-07-11 上海韬润半导体有限公司 一种用于集成电路调试的系统

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US7406639B2 (en) * 2004-12-13 2008-07-29 Lsi Corporation Scan chain partition for reducing power in shift mode
CN101300500A (zh) * 2005-11-02 2008-11-05 Nxp股份有限公司 Ic测试方法及设备
US7831876B2 (en) * 2007-10-23 2010-11-09 Lsi Corporation Testing a circuit with compressed scan chain subsets

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JP2738351B2 (ja) * 1995-06-23 1998-04-08 日本電気株式会社 半導体集積論理回路
US6243665B1 (en) * 1995-12-27 2001-06-05 Duaxes Corporation Monitoring and control apparatus incorporating run-time fault detection by boundary scan logic testing
US5909451A (en) 1996-11-21 1999-06-01 Sun Microsystems, Inc. System and method for providing scan chain for digital electronic device having multiple clock domains
EP1826579A1 (en) 2001-02-15 2007-08-29 Syntest Technologies, Inc. Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan test
JP2003058273A (ja) * 2001-08-13 2003-02-28 Oki Electric Ind Co Ltd ホールドタイム測定回路
JP2004077356A (ja) * 2002-08-21 2004-03-11 Nec Micro Systems Ltd スキャンチェーン回路、スキャンチェーン構築方法およびそのプログラム
US7032202B2 (en) 2002-11-19 2006-04-18 Broadcom Corporation System and method for implementing a flexible top level scan architecture using a partitioning algorithm to balance the scan chains
JP2004170244A (ja) * 2002-11-20 2004-06-17 Matsushita Electric Ind Co Ltd 組み込み自己検査回路
US7373568B1 (en) * 2003-01-21 2008-05-13 Marvell Israel Ltd. Scan insertion
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US7134061B2 (en) * 2003-09-08 2006-11-07 Texas Instruments Incorporated At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform
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US7418640B2 (en) * 2004-05-28 2008-08-26 Synopsys, Inc. Dynamically reconfigurable shared scan-in test architecture
US7447961B2 (en) * 2004-07-29 2008-11-04 Marvell International Ltd. Inversion of scan clock for scan cells
DE602004023888D1 (de) 2004-12-13 2009-12-10 Infineon Technologies Ag Schaltung und verfahren für bei geschwindigkeit durchgeführten scan-test
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JP2008275480A (ja) 2007-04-27 2008-11-13 Nec Electronics Corp 半導体集積回路のテスト回路、テスト方法
JP4802139B2 (ja) * 2007-05-15 2011-10-26 株式会社東芝 半導体集積回路モジュール
US20090187801A1 (en) * 2008-01-17 2009-07-23 Kamlesh Pandey Method and system to perform at-speed testing
JP2009216619A (ja) * 2008-03-12 2009-09-24 Texas Instr Japan Ltd 半導体集積回路装置
JP5625249B2 (ja) * 2009-03-24 2014-11-19 富士通株式会社 回路モジュール、半導体集積回路、および検査装置
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US7406639B2 (en) * 2004-12-13 2008-07-29 Lsi Corporation Scan chain partition for reducing power in shift mode
CN101300500A (zh) * 2005-11-02 2008-11-05 Nxp股份有限公司 Ic测试方法及设备
US7831876B2 (en) * 2007-10-23 2010-11-09 Lsi Corporation Testing a circuit with compressed scan chain subsets

Also Published As

Publication number Publication date
CN103076558A (zh) 2013-05-01
US8812921B2 (en) 2014-08-19
US20130103994A1 (en) 2013-04-25
KR20130045158A (ko) 2013-05-03
TW201317596A (zh) 2013-05-01
JP2013092517A (ja) 2013-05-16
EP2587273A1 (en) 2013-05-01

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Effective date of registration: 20160721

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Applicant after: Avago Technologies General IP (Singapore) Pte. Ltd.

Address before: California, USA

Applicant before: LSI Corp.

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Effective date of registration: 20181018

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Patentee after: Avago Technologies General IP (Singapore) Pte. Ltd.

Address before: Singapore Singapore

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Granted publication date: 20170412

Termination date: 20190619

CF01 Termination of patent right due to non-payment of annual fee