DE602004023888D1 - Schaltung und verfahren für bei geschwindigkeit durchgeführten scan-test - Google Patents

Schaltung und verfahren für bei geschwindigkeit durchgeführten scan-test

Info

Publication number
DE602004023888D1
DE602004023888D1 DE602004023888T DE602004023888T DE602004023888D1 DE 602004023888 D1 DE602004023888 D1 DE 602004023888D1 DE 602004023888 T DE602004023888 T DE 602004023888T DE 602004023888 T DE602004023888 T DE 602004023888T DE 602004023888 D1 DE602004023888 D1 DE 602004023888D1
Authority
DE
Germany
Prior art keywords
procedure
speed
circuit
scan test
test performed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004023888T
Other languages
English (en)
Inventor
Zhen Song Li
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE602004023888D1 publication Critical patent/DE602004023888D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE602004023888T 2004-12-13 2004-12-13 Schaltung und verfahren für bei geschwindigkeit durchgeführten scan-test Active DE602004023888D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2004/004089 WO2006064300A1 (en) 2004-12-13 2004-12-13 Circuitry and method for an at-speed scan test

Publications (1)

Publication Number Publication Date
DE602004023888D1 true DE602004023888D1 (de) 2009-12-10

Family

ID=34959728

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004023888T Active DE602004023888D1 (de) 2004-12-13 2004-12-13 Schaltung und verfahren für bei geschwindigkeit durchgeführten scan-test

Country Status (5)

Country Link
US (2) US7710801B2 (de)
EP (1) EP1875257B1 (de)
CN (1) CN101120261B (de)
DE (1) DE602004023888D1 (de)
WO (1) WO2006064300A1 (de)

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JP2008122159A (ja) * 2006-11-09 2008-05-29 Toshiba Corp 半導体集積回路
US7779316B2 (en) * 2007-12-05 2010-08-17 Oracle America, Inc. Method of testing memory array at operational speed using scan
US8006151B2 (en) 2008-03-28 2011-08-23 Texas Instruments Incorporated TAP and shadow port operating on rising and falling TCK
JP5131025B2 (ja) * 2008-05-16 2013-01-30 大日本印刷株式会社 デジタル信号遅延測定回路、及びデジタル信号遅延測定方法
JP2010038733A (ja) * 2008-08-05 2010-02-18 Toshiba Corp 半導体集積回路
US20100138709A1 (en) * 2008-10-22 2010-06-03 Laung-Terng Wang Method and apparatus for delay fault coverage enhancement
US20110066906A1 (en) * 2009-09-14 2011-03-17 LSI Corporate Pulse Triggered Latches with Scan Functionality
CN102183721B (zh) * 2010-12-14 2014-05-14 青岛海信信芯科技有限公司 多时钟域测试方法及测试电路
US8423844B2 (en) * 2011-01-11 2013-04-16 International Business Machines Corporation Dense register array for enabling scan out observation of both L1 and L2 latches
US8639987B2 (en) * 2011-02-18 2014-01-28 Arm Limited Data processing apparatus and method using monitoring circuitry to control operating parameters
US8671320B2 (en) 2011-06-21 2014-03-11 Lsi Corporation Integrated circuit comprising scan test circuitry with controllable number of capture pulses
US8694843B2 (en) * 2011-08-04 2014-04-08 Texas Instruments Incorporated Clock control of pipelined memory for improved delay fault testing
US8375265B1 (en) * 2011-09-13 2013-02-12 Texas Instruments Incorporated Delay fault testing using distributed clock dividers
US8812921B2 (en) 2011-10-25 2014-08-19 Lsi Corporation Dynamic clock domain bypass for scan chains
US8645778B2 (en) 2011-12-31 2014-02-04 Lsi Corporation Scan test circuitry with delay defect bypass functionality
US8726108B2 (en) 2012-01-12 2014-05-13 Lsi Corporation Scan test circuitry configured for bypassing selected segments of a multi-segment scan chain
CN102780800A (zh) * 2012-07-25 2012-11-14 广东欧珀移动通信有限公司 一种用于手机测试的时间加速流逝的实现方法
CN102928766B (zh) * 2012-10-26 2015-01-21 福州瑞芯微电子有限公司 一种在芯片高速测试中配置参数的方法
US8924801B2 (en) 2013-02-14 2014-12-30 Lsi Corporation At-speed scan testing of interface functional logic of an embedded memory or other circuit core
US9377511B2 (en) * 2013-11-19 2016-06-28 Infineon Technologies Ag Coverage enhancement and power aware clock system for structural delay-fault test
US9500706B2 (en) 2014-01-22 2016-11-22 Nvidia Corporation Hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support
CN103884981B (zh) * 2014-04-16 2016-11-02 威盛电子股份有限公司 隔离电路
CN103913691B (zh) * 2014-04-18 2016-08-24 龙芯中科技术有限公司 跳变时延故障向量生成方法和装置
US9234938B2 (en) * 2014-05-06 2016-01-12 Stmicroelectronics International N.V. Monitoring on-chip clock control during integrated circuit testing
US10409922B2 (en) 2014-06-10 2019-09-10 Siemens Product Lifecycle Management Software Inc. Navigating and authoring configured product lifecycle data
TWI533615B (zh) * 2014-06-13 2016-05-11 瑞昱半導體股份有限公司 鎖相迴路狀態偵測電路與方法
KR102291505B1 (ko) * 2014-11-24 2021-08-23 삼성전자주식회사 스토리지 장치 및 스토리지 장치의 동작 방법
US10447461B2 (en) * 2015-12-01 2019-10-15 Infineon Technologies Austria Ag Accessing data via different clocks
CN106291324B (zh) * 2016-08-18 2018-10-02 北京航空航天大学 一种片上差分时延测量系统及回收集成电路识别方法
CN108153964B (zh) * 2017-12-21 2021-11-09 北京兆芯电子科技有限公司 片上时钟电路
US10459029B2 (en) 2018-01-08 2019-10-29 Seagate Technology Llc On-chip clock control monitoring
CN110346618A (zh) * 2019-07-29 2019-10-18 天津大学 一种针对于多时钟域at-speed测试的OCC电路
CN115542140B (zh) * 2022-11-29 2023-03-10 深圳市爱普特微电子有限公司 用于产生全速扫描测试时钟信号的方法及系统

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US5680543A (en) * 1995-10-20 1997-10-21 Lucent Technologies Inc. Method and apparatus for built-in self-test with multiple clock circuits
US5909451A (en) * 1996-11-21 1999-06-01 Sun Microsystems, Inc. System and method for providing scan chain for digital electronic device having multiple clock domains
US6058496A (en) * 1997-10-21 2000-05-02 International Business Machines Corporation Self-timed AC CIO wrap method and apparatus
US5978944A (en) * 1997-11-26 1999-11-02 Intel Corporation Method and apparatus for scan testing dynamic circuits
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US6195776B1 (en) * 1998-11-02 2001-02-27 Synopsys, Inc. Method and system for transforming scan-based sequential circuits with multiple skewed capture events into combinational circuits for more efficient automatic test pattern generation
US6286119B1 (en) * 1998-12-22 2001-09-04 Nortel Networks Limited Delay fault testing with IEEE 1149.1
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US6880137B1 (en) * 2001-08-03 2005-04-12 Inovys Dynamically reconfigurable precision signal delay test system for automatic test equipment
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US7155649B2 (en) * 2003-03-12 2006-12-26 Matsushita Electric Industrial Co., Ltd. Scan test control method and scan test circuit
US7134061B2 (en) * 2003-09-08 2006-11-07 Texas Instruments Incorporated At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform
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US7685542B2 (en) * 2007-02-09 2010-03-23 International Business Machines Corporation Method and apparatus for shutting off data capture across asynchronous clock domains during at-speed testing

Also Published As

Publication number Publication date
CN101120261A (zh) 2008-02-06
WO2006064300A1 (en) 2006-06-22
CN101120261B (zh) 2010-09-29
EP1875257B1 (de) 2009-10-28
US8271841B2 (en) 2012-09-18
US20080004831A1 (en) 2008-01-03
US20070245180A1 (en) 2007-10-18
EP1875257A1 (de) 2008-01-09
US7710801B2 (en) 2010-05-04

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