CN102820227A - 一种深沟槽超级pn结的形成方法 - Google Patents

一种深沟槽超级pn结的形成方法 Download PDF

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CN102820227A
CN102820227A CN2011101517844A CN201110151784A CN102820227A CN 102820227 A CN102820227 A CN 102820227A CN 2011101517844 A CN2011101517844 A CN 2011101517844A CN 201110151784 A CN201110151784 A CN 201110151784A CN 102820227 A CN102820227 A CN 102820227A
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deep trench
junction
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CN102820227B (zh
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吴宗宪
王根毅
袁雷兵
吴芃芃
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CSMC Technologies Corp
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Wuxi CSMC Semiconductor Co Ltd
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Priority to PCT/CN2012/076353 priority patent/WO2012167715A1/zh
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/3065—Plasma etching; Reactive-ion etching

Abstract

本发明涉及深沟槽超级PN结的形成方法。该方法包括：在衬底上沉积外延层的沉积步骤；在外延层上依次形成第一介质层、第二介质层；在外延层形成深沟槽；对深沟槽填充外延材料以充满整个深沟槽并且超过第二介质层；将流动性的第三介质填满包含第二介质层和外延材料例如Si的整个表面，形成规定高度的表面填充层；对表面填充层进行等离子回刻，直至第一介质层和外延材料的界面处；去除所述第一介质层、第二介质层和表面填充层以实现硅平坦化的去除步骤。利用本发明，能够使用与现有的工艺兼容的方法实现Si的平坦化，具有工艺简单、效率高、工艺成本低的优点，并能够有效避免利用CMP导致的Si器件参数不稳定的问题。

Description

一种深沟槽超级PN结的形成方法
技术领域
本发明涉及半导体制造技术，尤其涉及一种深沟槽超级PN结（Super Junction）的制造技术。
背景技术
在半导体领域中，用来提高功率MOS性能的超级PN结（Super Junction）技术在高压领域的作用非常显著。
传统的超级PN结的制造工艺中主要是采用深槽刻蚀、外延填充、硅CMP平坦化的方法来实现。
具体地，传统技术中形成超级PN结的方法，包括以下步骤：
步骤1：在N+衬底硅片上沉积单一的厚外延层（N型）；
步骤2：在该外延层中形成深沟槽，具体地，先生长热氧化层，然后沉积氮化硅层，再沉积等离子体增强氧化层，通过刻蚀以上三层直至硅衬底，然后去胶，并以所述三种膜作为硬掩模刻蚀成深沟槽，然后湿法去除氮化硅表面剩余的等离子体增强氧化层；
步骤3：在深沟槽中填充外延硅（P型）形成超级PN结；
步骤4：通过CMP法研磨到硅表面达到平坦化。
然而，在所述利用CMP的技术中，因为一般生产线的CMP设备都用在后道，与加工超级PN结的设备不能混用，因此，利用CMP平坦化制造超级PN结方法工艺必须采用专用CMP设备而导致工艺控制难度大，成本较高。
发明内容
本发明鉴于所述问题，旨在提供一种能够与常规工艺兼容、且工艺简单、效率高的超级PN结（Super Junction）的形成方法。
本发明的深沟槽超级PN结的形成方法，其特征在于，包括：
在衬底上沉积外延层的沉积步骤；
在所述外延层上依次形成第一介质层、第二介质层的介质形成步骤；
在所述外延层形成深沟槽的深沟槽形成步骤；
对所述深沟槽填充外延材料以充满整个深沟槽并且超过第二介质层的第一填充步骤；
将第三介质填满包含所述第二介质层和所述外延材料的整个表面，形成规定高度的表面填充层的第二填充步骤；
对所述表面填充层进行回刻直至第一介质层和外延材料的界面处的刻蚀步骤；
去除所述第一介质层、第二介质层和表面填充层以实现外延材料的平坦化的去除步骤。
优选地，可以在所述刻蚀步骤中，采用等离子刻蚀法。
优选地，在所述第二填充步骤中，使用辅料设备填充所述第三介质，所述第三介质是流动性的介质。
利用所述发明，替代现有技术中采用的CMP，而采用填充流动性介质材料和等离子回刻，因此，能够有效解决利用CMP进行平坦化所带来的工艺复杂、控制难度大，成本高的技术问题。
优选地，所述等离子刻蚀法可以是通过调整刻蚀的选择比以使得对所述外延材料和对所述第三介质的刻蚀速率为1：1。
优选地，所述表面填充层的高度至少比所述外延材料的最高点高。
优选地，在所述第二填充步骤中，使用所述辅料设备通过旋转、涂布将流动性的第三介质填满所述第二介质层和外延材料的整个表面。
优选地，在所述去除步骤中，采用湿法去除各层。
优选地，在所述第一填充步骤中，所述外延材料最低点超过所述第一介质与所述外延材料的界面。
优选地，所述第一介质是氧化物，所述第二介质是氮化物，所述外延材料是Si，所述第三介质是SOG。
优选地，所述第一介质的厚度形成为大于500A，所述第二介质的厚度形成为大于300A。
如上所述，通过采用填充流动性介质材料和等离子回刻，能够使用与现有的工艺兼容的方法实现硅的平坦化，而无需专用的CMP设备，因此具有工艺简单、效率高、工艺成本低的优点，而且能够有效避免利用CMP导致的Si器件参数不稳定的问题。
附图说明
图1是表示本发明一实施方式的超级PN结形成过程的整体流程图。
图2是表示本发明一实施方式的超级PN结形成过程的分解示意图。
图3是表示本发明一实施方式的超级PN结形成过程的分解示意图。
图4是表示本发明一实施方式的超级PN结形成过程的分解示意图。
图5是表示本发明一实施方式的超级PN结形成过程的分解示意图。
具体实施方式
下面介绍的是本发明的多个可能实施例中的一些，旨在提供对本发明的基本了解。并不旨在确认本发明的关键或决定性的要素或限定所要保护的范围。
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明作进一步的详细描述。
以下，参照图1～图5，对本发明一实施方式的深沟槽超级PN结的形成方法进行说明。
图1是表示本发明一实施方式的超级PN结形成过程的整体流程图。
首先，如图1所示，本发明的超级PN结形成方法主要包括：
步骤1：在衬底上沉积外延层的沉积步骤；
步骤2：在所述外延层上依次形成第一介质层、第二介质层的介质形成步骤；
步骤3：在所述外延层形成深沟槽的深沟槽形成步骤；
步骤4：对所述深沟槽填充外延材料以充满整个深沟槽并且超过第二介质层的第一填充步骤；
步骤5：将第三介质填满包含所述第二介质层和所述外延材料的整个表面，形成规定高度的表面填充层的第二填充步骤；
步骤6：对所述表面填充层进行回刻直至第一介质层和外延材料的界面处的刻蚀步骤；
步骤7：去除所述第一介质层、第二介质层和表面填充层以实现外延材料的平坦化的去除步骤。
图2～5是表示本发明一实施方式的超级PN结形成过程的分解示意图。
下面对于上述步骤1～7，参照图2～5进行具体说明。
如图2～图5所示，本发明一实施方式的深槽超级PN结的形成方法主要具备下述步骤：
步骤1：在衬底上沉积外延层100；
步骤2：在所述外延层100的上依次形成第一介质层200、第二介质层300的形成步骤；
步骤3：在所述外延层形成深沟槽400；
步骤4：如图2所示，对所述深沟槽400填充外延材料 500以充满整个深沟槽400并且超过第二介质层200。
步骤5：如图3所示，将第三介质600覆盖、填满包含所述第二介质层200和外延材料 500的整个表面，形成规定高度的表面填充层。
步骤6：如图4所示，对所述表面填充层进行回刻，直至第一介质层200和外延材料 500的界面处。
步骤7：去除所述表面介质层即第一介质层100、第二介质层200和所述表面填充层，实现外延材料的平坦化。
这样，替代现有技术中采用的CMP，通过采用填充第三介质材料和回刻的方法，能够有效解决利用CMP进行平坦化所带来的工艺复杂、控制难度大，成本高的技术问题。
下面，对于上述实施方式的几种变形例进行说明。
对于所述第三介质600，最好采用流动性的材料。例如，通常可以采用SOG。这样，在所述步骤5中，将流动的第三介质600例如SOG填充图2中的包含所述第二介质层200和外延材料 500的整个表面，形成规定高度的表面填充层
在填充第三介质600时，可以采用常用的辅料设备。在使用辅料设备填充流动的第三介质600时，辅料设备通过旋转、涂布将流动的第三介质600填满整个表面。
这里的所谓的“规定高度”是指至少比所述外延材料 500的最高点高。
在所述步骤6中，作为回刻的手段，较佳地是采用等离子刻蚀法。为了实现对外延材料500和第三介质600两者的平整刻蚀，在等离子刻蚀方法中，可以通过调整刻蚀的选择比，例如通过使得对外延材料 500和所述第三介质600的刻蚀选择比为1：1，由此，能够以相同的速率对外延材料 500和第三介质600进行刻蚀，能够将两者刻蚀平整，实现外延材料的平坦化。
这里，通常作为外延材料500，常用的是Si。
进一步，在所述步骤7中，作为去除第一介质层100、第二介质层200和所述表面填充层的方法，可以采用湿法。
另外，所述第一介质层100优选地可以是氧化物，所述第二介质层200优选地为氮化物。所述第一介质的厚度形成为大于500A，所述第二介质的厚度形成为大于300A。
综上所述，利用本发明，由于使用与现有的工艺兼容的方法实现外延材料（Si）的平坦化，工艺简单、效率高、无需专用的设备（即CMP的设备），因此，大大降低了工艺成本，并能够有效避免利用CMP导致的Si器件参数不稳定的问题。
以上例子主要说明了本发明的超级PN结的形成方法。尽管只对其中一些本发明的实施方式进行了描述，但是本领域普通技术人员应当了解，本发明可以在不偏离其主旨与范围内以许多其他的形式实施。因此，所展示的例子与实施方式被视为示意性的而非限制性的，在不脱离如所附各权利要求所定义的本发明精神及范围的情况下，本发明可能涵盖各种的修改与替换。

Claims (10)

1.一种深沟槽超级PN结的形成方法，其特征在于，包括：
在衬底上沉积外延层的沉积步骤；
在所述外延层上依次形成第一介质层、第二介质层的介质形成步骤；
在所述外延层形成深沟槽的深沟槽形成步骤；
对所述深沟槽填充外延材料以充满整个深沟槽并且超过第二介质层的第一填充步骤；
将第三介质填满包含所述第二介质层和所述外延材料的整个表面，形成规定高度的表面填充层的第二填充步骤；
对所述表面填充层进行回刻直至第一介质层和外延材料的界面处的刻蚀步骤；
去除所述第一介质层、第二介质层和表面填充层以实现外延材料的平坦化的去除步骤。
2.如权利要求1所述深沟槽超级PN结的形成方法，其特征在于，
在所述刻蚀步骤中，采用等离子刻蚀法。
3.如权利要求2所述深沟槽超级PN结的形成方法，其特征在于，
所述等离子刻蚀法是通过调整刻蚀的选择比以使得对所述外延材料和对所述第三介质的刻蚀速率为1：1。
4.如权利要求2所述深沟槽超级PN结的形成方法，其特征在于，
在所述第二填充步骤中，使用辅料设备填充所述第三介质，所述第三介质是流动性的介质。
5.如权利要求4所述深沟槽超级PN结的形成方法，其特征在于，
所述表面填充层的高度至少比所述外延材料的最高点高。
6.如权利要求4所述深沟槽超级PN结的形成方法，其特征在于，
在所述第二填充步骤中，使用所述辅料设备通过旋转、涂布将流动性的第三介质填满所述第二介质层和外延材料的整个表面。
7.如权利要求4所述深沟槽超级PN结的形成方法，其特征在于，
在所述去除步骤中，采用湿法去除各层。
8.如权利要求4所述深沟槽超级PN结的形成方法，其特征在于，
在所述第一填充步骤中，所述外延材料最低点超过所述第一介质与所述外延材料的界面。
9.如权利要求1～8任意一项所述的深沟槽超级PN结的形成方法，其特征在于，
所述第一介质是氧化物，所述第二介质是氮化物，所述外延材料是Si，所述第三介质是SOG。
10.如权利要求9所述深沟槽超级PN结的形成方法，其特征在于，
所述第一介质的厚度形成为大于500A，所述第二介质的厚度形成为大于300A。
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