JP5755803B2 - 深溝を有する新型pn接合の形成方法 - Google Patents
深溝を有する新型pn接合の形成方法 Download PDFInfo
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- JP5755803B2 JP5755803B2 JP2014513043A JP2014513043A JP5755803B2 JP 5755803 B2 JP5755803 B2 JP 5755803B2 JP 2014513043 A JP2014513043 A JP 2014513043A JP 2014513043 A JP2014513043 A JP 2014513043A JP 5755803 B2 JP5755803 B2 JP 5755803B2
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- 238000000034 method Methods 0.000 title claims description 65
- 239000000463 material Substances 0.000 claims description 47
- 238000005530 etching Methods 0.000 claims description 18
- 239000012530 fluid Substances 0.000 claims description 9
- 238000001020 plasma etching Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 3
- 150000004767 nitrides Chemical group 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Manufacturing & Machinery (AREA)
- Formation Of Insulating Films (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
Description
200 第一媒質層
300 第二媒質層
400 深溝
500 エピタキシャル材料
600 第三媒質
Claims (10)
- 深溝を有するPN接合の形成方法において、
基材上にエピタキシャル層(N型)を積層する積層ステップと、
前記エピタキシャル層上に順次に第一媒質層、第二媒質層を形成する媒質形成ステップと、
前記エピタキシャル層に深溝を形成する深溝形成ステップと、
深溝にエピタキシャル材料(P型)を充填して深溝を詰めるとともに、第二媒質層を超えるまでエピタキシャル材料を充填する第一充填ステップと、
前記第二媒質層と前記エピタキシャル材料を含む全表面に第三媒質を充填して、所定の高さを有する表面充填層を形成する第二充填ステップと、
第一媒質層とエピタキシャル材料が隣接する面まで、前記表面充填層とエピタキシャル材料をエッチングするエッチングステップと、
前記第一媒質層、第二媒質層及び表面充填層を除去して、エピタキシャル材料の平坦化を実現する除去ステップと、を含み、
前記PN接合は、前記N型と前記P型が接合して形成されることを特徴とする深溝を有するPN接合の形成方法。 - 前記エッチングステップにおいて、プラズマエッチング方法を採用することを特徴とする請求項1に記載の深溝を有するPN接合の形成方法。
- 前記プラズマエッチング方法は、エッチングの選択比率を調節することにより、前記エピタキシャル材料と前記第三媒質のエッチング速度比を1:1にすることを特徴とする請求項2に記載の深溝を有するPN接合の形成方法。
- 前記第二充填ステップにおいて、充填設備を採用して前記第三媒質を充填し、且つ前記第三媒質が流動性のある媒質であることを特徴とする請求項2に記載の深溝を有するPN接合の形成方法。
- 前記表面充填層の高さは、少なくとも前記エピタキシャル材料の最高点より高いことを特徴とする請求項4に記載の深溝を有するPN接合の形成方法。
- 前記第二充填ステップにおいて、前記充填設備を回転させながら塗布する方法により、流動性のある第三媒質を前記第二媒質層とエピタキシャル材料の全表面に充填することを特徴とする請求項4に記載の深溝を有するPN接合の形成方法。
- 前記除去ステップにおいて、ウェット方法を採用して各層を除去することを特徴とする請求項4に記載の深溝を有するPN接合の形成方法。
- 前記第一充填ステップにおいて、前記エピタキシャル材料における上部表面の最低部は前記第一媒質層より高いことを特徴とする請求項4に記載の深溝を有するPN接合の形成方法。
- 前記第一媒質層が酸化物であり、前記第二媒質層が窒化物であることを特徴とする請求項1ないし請求項8のいずれか1項に記載の深溝を有するPN接合の形成方法。
- 前記第一媒質層の厚さが500オングストロームより厚く、前記第二媒質層の厚さが300オングストロームより厚いことを特徴とする請求項9に記載の深溝を有するPN接合の形成方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110151784.4A CN102820227B (zh) | 2011-06-08 | 2011-06-08 | 一种深沟槽超级pn结的形成方法 |
CN201110151784.4 | 2011-06-08 | ||
PCT/CN2012/076353 WO2012167715A1 (zh) | 2011-06-08 | 2012-05-31 | 一种深沟槽超级pn结的形成方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2014522568A JP2014522568A (ja) | 2014-09-04 |
JP2014522568A5 JP2014522568A5 (ja) | 2015-05-14 |
JP5755803B2 true JP5755803B2 (ja) | 2015-07-29 |
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JP2014513043A Active JP5755803B2 (ja) | 2011-06-08 | 2012-05-31 | 深溝を有する新型pn接合の形成方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8927386B2 (ja) |
EP (1) | EP2709142B1 (ja) |
JP (1) | JP5755803B2 (ja) |
CN (1) | CN102820227B (ja) |
WO (1) | WO2012167715A1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US10461152B2 (en) | 2017-07-10 | 2019-10-29 | Globalfoundries Inc. | Radio frequency switches with air gap structures |
US10833153B2 (en) | 2017-09-13 | 2020-11-10 | Globalfoundries Inc. | Switch with local silicon on insulator (SOI) and deep trench isolation |
US10446643B2 (en) | 2018-01-22 | 2019-10-15 | Globalfoundries Inc. | Sealed cavity structures with a planar surface |
US10156676B1 (en) | 2018-02-26 | 2018-12-18 | Globalfoundries Inc. | Waveguides with multiple airgaps arranged in and over a silicon-on-insulator substrate |
US10393960B1 (en) | 2018-02-26 | 2019-08-27 | Globalfoundries Inc. | Waveguides with multiple-level airgaps |
US11410872B2 (en) | 2018-11-30 | 2022-08-09 | Globalfoundries U.S. Inc. | Oxidized cavity structures within and under semiconductor devices |
US10923577B2 (en) | 2019-01-07 | 2021-02-16 | Globalfoundries U.S. Inc. | Cavity structures under shallow trench isolation regions |
US11127816B2 (en) | 2020-02-14 | 2021-09-21 | Globalfoundries U.S. Inc. | Heterojunction bipolar transistors with one or more sealed airgap |
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JPH01108746A (ja) * | 1987-10-21 | 1989-04-26 | Toshiba Corp | 半導体装置の製造方法 |
JPH0513566A (ja) * | 1991-07-01 | 1993-01-22 | Toshiba Corp | 半導体装置の製造方法 |
US6399506B2 (en) * | 1999-04-07 | 2002-06-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for planarizing an oxide layer |
JP2001244328A (ja) * | 2000-02-29 | 2001-09-07 | Denso Corp | 半導体装置の製造方法 |
CN100565801C (zh) * | 2004-03-31 | 2009-12-02 | 株式会社电装 | 半导体器件的制造方法 |
US7811907B2 (en) * | 2005-09-29 | 2010-10-12 | Denso Corporation | Method for manufacturing semiconductor device and epitaxial growth equipment |
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JP5572924B2 (ja) * | 2008-06-23 | 2014-08-20 | 富士電機株式会社 | 半導体装置の製造方法 |
JP2010028018A (ja) * | 2008-07-24 | 2010-02-04 | Fuji Electric Device Technology Co Ltd | 半導体ウエハおよび半導体装置と半導体装置の製造方法 |
CN101752252A (zh) * | 2008-12-16 | 2010-06-23 | 上海华虹Nec电子有限公司 | CoolMOS结构中纵向P型区的形成方法 |
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JP2011096691A (ja) * | 2009-10-27 | 2011-05-12 | Toshiba Corp | 半導体装置の製造方法 |
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TWI463571B (zh) * | 2011-12-08 | 2014-12-01 | Vanguard Int Semiconduct Corp | 半導體裝置的製造方法 |
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2011
- 2011-06-08 CN CN201110151784.4A patent/CN102820227B/zh active Active
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- 2012-05-31 US US13/878,453 patent/US8927386B2/en active Active
- 2012-05-31 JP JP2014513043A patent/JP5755803B2/ja active Active
- 2012-05-31 EP EP12796409.6A patent/EP2709142B1/en active Active
- 2012-05-31 WO PCT/CN2012/076353 patent/WO2012167715A1/zh active Application Filing
Also Published As
Publication number | Publication date |
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EP2709142A4 (en) | 2015-01-07 |
US8927386B2 (en) | 2015-01-06 |
WO2012167715A1 (zh) | 2012-12-13 |
EP2709142A1 (en) | 2014-03-19 |
JP2014522568A (ja) | 2014-09-04 |
CN102820227A (zh) | 2012-12-12 |
US20130196489A1 (en) | 2013-08-01 |
CN102820227B (zh) | 2015-08-19 |
EP2709142B1 (en) | 2016-03-23 |
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