CN104253127B - 具有降低衬底翘曲的背面结构的集成电路 - Google Patents

具有降低衬底翘曲的背面结构的集成电路 Download PDF

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CN104253127B
CN104253127B CN201310395495.8A CN201310395495A CN104253127B CN 104253127 B CN104253127 B CN 104253127B CN 201310395495 A CN201310395495 A CN 201310395495A CN 104253127 B CN104253127 B CN 104253127B
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groove
wafer
back side
components according
crystal wafer
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CN104253127A (zh
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陈志明
王嗣裕
喻中
喻中一
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明通过形成在晶圆的反面上的结构来改善深沟槽电容器引起的晶圆翘曲。反面上的结构包括张力膜。张力膜可形成在晶圆的背面上的沟槽内，这样会增强其效果。在一些实施例中，使用晶圆形成3D‑IC器件。在一些实施例中，3D‑IC器件包括高电压或高功率电路。本发明还公开了具有降低衬底翘曲的背面结构的集成电路。

Description

具有降低衬底翘曲的背面结构的集成电路
技术领域
本发明半导体技术领域，尤其涉及一种具有降低衬底翘曲的背面结构的集成电路。
背景技术
由于集成电路的发明，半导体产业在不断寻找提高集成电路元件（晶体管、二极管、电阻器、电容器等）集成度的方法。在大部分情况下，密度的提高源自部件尺寸的减小，从而使更多的元件可形成在给定区域内。虽然已经取得这些进步，然而这些元件仍留在基本的二维布局。虽然在二维布局的限制内已实现了密度的大幅度提高，但是却很难实现进一步的发展。
已经创造三维集成电路（3D IC）来克服这些限制。在3D IC中，两个或更多的半导体主体形成为垂直对准且接合在一起，并且每一个半导体主体都包括集成电路。提高器件密度的另一种方法是通过各个晶圆上的垂直器件结构。垂直结构能够大大降低集成电路（IC）器件所需的表面积。深沟槽电容器是一种已受关注的垂直器件结构。深沟槽电容器可用于各种电容量，最显著的是形成动态随机存取存储器（DRAM）。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种集成电路器件，包括：
第一半导体衬底，具有正面和背面；
第一结构，包括形成在所述正面上的深沟槽电容器，所述第一结构包括向所述衬底施加压应力的张力材料；以及
第二结构，形成在所述衬底的所述背面上，所述第二结构包括向所述衬底施加压应力的张力材料；
其中，所述第二结构包括选自由下列组成的组的结构：
厚度大于位于所述正面上的相同材料的任何膜的厚度的一层或多层张力膜；以及
填充所述衬底内的沟槽的张力材料。
在可选实施例中，所述背面结构未形成所述器件的电路的一部分。
在可选实施例中，所述背面结构包括填充所述衬底内的沟槽的张力材料。
在可选实施例中，所述背面上的用张力材料填充的沟槽和所述正面上的所述深沟槽电容器形成于其内的沟槽具有与使用相同光刻掩模形成的两组沟槽相一致的图案。
在可选实施例中，所述背面上的沟槽的深度与所述正面上的沟槽的深度明显不同。
在可选实施例中，所述背面结构包括总厚度大于1μm的一个以上的涂层。
在可选实施例中，所述集成电路器件进一步包括：一层或多层压缩膜，形成在所述深沟槽电容器上方；其中，所述压缩膜向所述衬底施加张应力，所述张应力的大小为由包括深沟槽电容器的结构向所述衬底施加的压缩力的至少20%。
在可选实施例中，所述集成电路器件进一步包括：第二半导体衬底，在其上形成有电路；其中，所述器件是3D-IC器件。
在可选实施例中，所述集成电路器件还包括：形成在所述第二半导体衬底上的高电压或高功率电路。
在可选实施例中，所述第二半导体衬底的电路通过硅通孔连接至包括所述深沟槽电容器的电路。
在可选实施例中，所述第二半导体衬底的电路通过晶圆与晶圆的接合连接至包括所述深沟槽电容器的电路。
根据本发明的另一方面，还提供了一种制造集成电路器件的方法，包括：
提供第一半导体晶圆；
在所述晶圆的正面上形成第一结构，所述第一结构包括深沟槽电容器；以及
在所述晶圆的背面上形成压应力诱导的第二结构；
其中，所述第二结构包括选自由下列组成的组的结构：
厚度大于所述正面上的相同材料的任何膜的厚度的一层或多层压缩膜；以及
填充所述衬底内的沟槽的张力材料。
在可选实施例中，形成的正面结构和背面结构中的第一结构使得所述晶圆在一个方向上翘曲，而形成的所述正面结构和所述背面结构中的第二结构使所述翘曲降低了至少一半。
在可选实施例中，在所述衬底的所述背面上形成所述压应力诱导的第二结构包括在所述晶圆中形成沟槽，然后用张力材料填充所述沟槽。
在可选实施例中，形成所述深沟槽电容器包括使用光刻掩模的光刻工艺；以及，在所述背面上形成所述第二结构包括使用相同的掩模蚀刻所述晶圆的所述背面中的沟槽。
在可选实施例中，选择位于所述晶圆的背面上的沟槽的尺寸，以使所述晶圆的背面上的应力和所述正面上的应力平衡。
在可选实施例中，在所述晶圆的背面上形成所述压应力诱导的结构包括形成总厚度大于1μm的一层或多层张力膜。
在可选实施例中，所述方法还包括：在所述晶圆的正面上的结构上方形成一层或多层压缩膜；其中，选择所述压缩膜的厚度，以平衡所述晶圆的正面和背面上的应力。
在可选实施例中，所述方法还包括：将所述第一半导体晶圆连接至包括高电压或高功率集成电路的第二半导体晶圆，以形成3D-IC
在可选实施例中，所述方法还包括：将所述第一半导体晶圆的电路通过晶圆与晶圆接合连接至第二半导体晶圆的电路。
附图说明
图1示出了根据本发明实施例的工艺的流程图；
图2至图5示出了根据图1所示方法的在不同加工阶段的本发明一实施例的晶圆；
图6示出了根据本发明另一个实施例的工艺的流程图；
图7至图18示出了根据图6所示方法的在不同加工阶段的本发明一实施例的集成电路器件；
图19至图21示出了根据本发明各种可选实施例的集成电路器件；
图22示出了根据本发明另一个实施例的工艺的流程图；以及
图23至图25示出了根据本发明一些实施例的3D-IC器件。
具体实施方式
在制造具有深沟槽电容器的集成电路器件的过程中，其上形成有电容器的晶圆可能变得弯曲。发明人发现，对于具有多层导电层的深沟槽电容器来说，这种弯曲现象尤为严重。弯曲可能到会给诸如化学机械抛光的后续工艺带来不利影响的程度。对于形成3D-IC器件的晶圆来说，这种弯曲可能尤其成为问题。
发明人通过在晶圆的背面上形成具有张应力的结构解决了此问题。在一些实施例中，这些结构是张力膜。在一些实施例中，这些结构包括用张力材料（tensile material）填充的沟槽。位于晶圆背面上的结构能够充分降低晶圆弯曲，从而能够进行进一步的加工。在一些实施例中，通过在晶圆正面的电容器上方形成一层或多层压缩膜来进一步降低弯曲。
图1示出了本发明提供的示例性工艺100的流程图。图2至图5示出了在工艺100的不同阶段的晶圆201。工艺100开始于步骤101，提供晶圆201。在此阶段，如图2所示，晶圆201是平坦的。
工艺100继续进行步骤103，在晶圆201的正面202上形成深沟槽电容器203。深沟槽电容器203的材料在高温条件下沉积且具有与晶圆201不同的热膨胀系数。当晶圆201冷却后，填充深沟槽电容器203的材料收缩的程度比形成晶圆201的材料的收缩程度大。由于填充深沟槽电容器203的材料粘附至晶圆201，填充深沟槽电容器203的材料成为张力膜或材料，这意味着张应力下的膜或材料。这些张应力向晶圆201的正面202施加压缩力。如图3所示，这种力能使晶圆201发生弯曲。
将弯曲206的量定义为限制晶圆201的表面202上所有点的任两个平面208之间的最短距离。在一些实施例中，深沟槽电容器203对晶圆201施加充分的应力以拉紧晶圆201至弯曲206，该弯曲206大于后续加工过程中缺少抵消弯曲应力（诸如本发明提供的那些）的结构情况下所能容忍的弯曲。在一些实施例中，150μm是后续加工过程中能够容忍的最大弯曲。
工艺100继续进行步骤105，在晶圆201的背面204上形成具有张应力的结构205。如图4所示，结构205能够抵消深沟槽电容器203引起的应力并且降低弯曲206。虽然在本实例中示出的结构205是在形成深沟槽电容器203之后形成的，但是，在其他实施例中，可以在深沟槽电容器203之前或与深沟槽电容器203同时形成结构205的全部或部分。
在一些实施例中，通过步骤105产生的结构205将晶圆弯曲度206降低至小于150μm。在一些实施例中，步骤105产生的结构205向晶圆201的背面204上施加压缩力，该压缩力的大小为深沟槽电容器203向正面202施加的压缩力的至少50%。在一些实施例中，结构205将晶圆弯曲206降低了至少50%。
工艺100继续进行步骤107，进行化学机械抛光。步骤107的步骤示例说明了如果晶圆201具有过度的弯曲206，可能在整个表面202上非均匀性地操作至不可接受的程度。在一些实施例中，这些步骤是非常常见的，在前段制程（FEOL）加工过程中和后段制程（BEOL）加工之前进行步骤107。
工艺100可以继续进行可选步骤109。在步骤109中，在深沟槽电容器203上方形成一层或多层可选压缩膜207。压缩膜是一种通常在沉积（冷却时）之后收缩的程度比膜粘附的结构的收缩程度小的膜，因此，该膜在应力下产生。如图5所示，压缩膜207能够进一步平衡深沟槽电容器203引起的应力，并且也能进一步降低晶圆弯曲206。
步骤109可包括控制以微调步骤109的应力平衡。在一些实施例中，步骤109包括测量晶圆弯曲度206和利用测量值来确定压缩膜207的厚度。在步骤105期间可进行用于确定结构205的厚度或深度的相似的工序。在一些实施例中，步骤109将晶圆弯曲度206降低至不存在能抵消弯曲度应力的结构（诸如结构205和207）情形下深沟槽电容器203可能引起的弯曲度的20%以下。
在一些实施例中，在晶圆201的背面204上形成一层或多层附加张力膜（未示出）来代替在晶圆201的正面上形成压缩膜207。在其他实施例中，组合使用背面204上的额外张力膜和正面202上的压缩膜207，以实现步骤109的应力平衡。
图6提供了工艺300的流程图，工艺300是在工艺100范围内的一种更详细的工艺的实例。图7至图18示出了通过工艺300制造的示例性IC器件200。器件200包括晶圆201的至少一部分和深沟槽电容器203。
工艺300的第一步骤101为提供半导体衬底201。衬底201包括半导体主体。在一些实施例中，衬底201由半导体的单晶材料形成。半导体主体的实例包括但不限于：硅、绝缘体上硅（SOI）、Ge、SiC、GaAs、GaAlAs、InP、GaN和SiGe。半导体衬底201可包括附图中未示出的、但通过可在工艺300的步骤之前、同时或之后进行的一个或多个步骤形成的区域、结构和器件。
在一些实施例中，半导体衬底201是半导体晶圆。晶圆201的直径在300mm以下，其为半导体产业内的目前常见的晶圆。然而，在一些其他实施例中，晶圆201的直径大于300mm，例如，450mm。由于大直径的晶圆对翘曲具有更强的敏感度，所以本发明的工艺和结构对这些晶圆尤其有用。
工艺300继续进行一系列步骤103，形成深沟槽电容器203。如图7所示，步骤301为在半导体衬底201的正面202上形成图案化掩模209。掩模209可包括一个或多层。可使用任何适合的材料或材料的组合。掩模209典型地是一种使用光刻胶（未示出）通过光刻技术图案化的硬掩模，光刻胶由包括通过光刻掩模（也未示出）曝光的工艺图案化而成。硬掩模材料可以是二氧化硅。适用于硬掩模209的其他材料的实例包括但不限于氮化硅和SiON。掩模层209可通过任何合适的工艺或工艺的组合形成。
步骤303为通过穿过掩模209蚀刻半导体衬底201形成沟槽212，如图8所示。可以使用任何合适的蚀刻工艺。合适的蚀刻工艺通常是等离子体蚀刻。在大多数实施例中，沟槽212具有高纵横比。高纵横比是深度214和宽度216的比，其为10:1或更大。在一些实施例中，沟槽212的纵横比介于20:1至50:1之间。在一些实施例中，深度214介于500nm至10,000nm之间。在多数实施例中，宽度216介于约28nm至500nm之间。在一些实施例中，宽度216介于50nm至200nm之间。
在多数实施例中，存在大量均匀间隔且平行的沟槽212。大量可以是大于10的数。通常，这个数大于100。如果沟槽212之间的距离保持为约大于沟槽212的长度的常数时，则认为相邻的成对沟槽212是平行的，其中，沟槽212的长度比沟槽宽度216大一个以上量级。
步骤305为去除掩模209的位于相邻沟槽212之间的一部分231的修整工艺，如图8和图9所示。在一些实施例中，步骤305是使用光刻胶掩模的蚀刻工艺。在一些其他实施例中，步骤305是优先去除位置231处的掩模209的无掩模蚀刻。通过使用横向或各向同性蚀刻工艺能够实现对位置231的优先蚀刻，掩模209在位置231处的量与掩模209离沟槽212远的部分相比，横向或各向同性蚀刻利用更大的表面积。无掩模蚀刻工艺可以是湿蚀刻。
步骤309为掺杂沟槽212附近的衬底201以形成导电阱211，如图10所示。掺杂可以是n型或p型。可使用任何合适的掺杂工艺。用于步骤307的典型掺杂工艺是扩散掺杂工艺。例如，可通过将加热的衬底201暴露于POCl3蒸汽中使半导体201掺杂磷。
步骤311中，沿着沟槽212内衬形成介电阻挡层213。介电阻挡层213可由任何合适的电介质的一层或多层形成。介电阻挡层213的典型结构包括两个以上的层。这些层的常用材料包括SiO2、SiON和SiN。可用于介电阻挡层213的材料的其他实例包括但不限于Ta2O、Al2O3和高k电介质。可通过任何合适的工艺或工艺的组合形成介电阻挡层213。初始步骤可以是去渣（deglazing）以去除在先前加工过程中形成在沟槽212的侧壁上的氧化物。
步骤313为沉积导电材料215以填充沟槽212从而形成电容器203，如图11所示。导电材料215也形成在掩模209上方以及掩模层209中的开口内。导电材料215可以是任何合适的导电材料并且可包括多层不同的导电材料。可使用的导电材料的实例包括掺杂半导体、金属和金属化合物。可通过任何合适的工艺或工艺的组合沉积导电材料215。在一些实施例中，导电材料215是多晶硅。
步骤313之后，通常期望应用化学机械抛光以去除位于掩模209上方的导电材料215。但是，在这一加工阶段，翘曲206可能会干扰抛光。步骤105是在衬底201的背面204上形成结构205以降低翘曲206的一系列步骤。
在工艺300中，步骤105开始于步骤315，在衬底201的背面204上形成掩模217，如图12所示。在步骤317中，如图13所示，通过穿过掩模217中的开口蚀刻衬底201以在背面204中形成沟槽214。在步骤319中，如图14所示，用张力材料填充沟槽214，以形成结构205。
在一些实施例中，在步骤317中，使用光刻掩模图案化沟槽214，该光刻掩模与用于图案化其中形成有深沟槽电容器203的沟槽212的掩模相同。这些实施例的优势在于，无需额外的掩模就可形成沟槽214。通过这些实施例产生了沟槽214的图案和沟槽212的图案相对应的器件。在一些实施例中，虽然沟槽214和沟槽212具有相同的图案，但是这两组沟槽的深度不同。可以选择不同的深度以更好地平衡晶圆201的背面应力和正面应力。在一些实施例中，基于弯曲206的测量值来选择沟槽214的深度。
在大多数实施例中，结构205的张力材料是热膨胀系数比张力材料粘附的半导体衬底201的材料的热膨胀系数大的材料。由于衬底201和结构205的材料在沉积之后冷却，结构205的材料的收缩程度大于衬底201的材料的收缩程度，因此结构205的材料向衬底201且邻近衬底背面204施加压缩力。这种力与由电容器203向衬底201且邻近衬底正面202施加的力相对抗，从而降低了翘曲206。
在沉积成为结构205的张力膜的材料之前形成沟槽214能够大幅度增大结构205施加给衬底201的应力。然而，在一些实施例中，没有形成沟槽214。虽然没有形成沟槽214简化了工艺300，但是，要求结构205的材料具有更大的厚度，以向衬底201的背面204提供等量的应力。而且，如果没有形成沟槽214，由结构205向衬底201施加的最大应力通常会变得较小。
虽然考虑到电容器203的期望性能而选择沟槽212的尺寸，但是不能类似地限制沟槽214的尺寸。因此，在宽度、深度、密度和所跨面积中的一个或多个方面，沟槽214和沟槽212是可以不同的。通常，所施加的应力随沟槽图案密度而增大。因此，在一些实施例中，沟槽214的图案密度大于沟槽212的图案密度，例如，分别为15%和23%。在一些实施例中，沟槽214的纵横比（深度和宽度之比）小于沟槽212的纵横比。较小的纵横比有利于处理。
通过步骤105形成结构205之后，方法300继续进行步骤107，平坦化工艺（通常为化学机械抛光）。对于器件200，通过步骤107，去除掩模209中的开口外侧的导电材料215，以产生如图15所示的结构。如图16所示，工艺300可进行额外的步骤，诸如去除掩模209的剩余部分的步骤321和氧化以形成介电阻挡层219的步骤323。
工艺300可继续进行额外的步骤，包括BEOL加工。在一些实施例中，如图17所示，继续步骤包括在DTC203上方形成压缩膜207的步骤109。在一些实施例中，压缩膜207是层间介电（ILD）层，但是膜207可以是形成在DTC203上方的任一层。
在多数实施例中，由热膨胀系数小于衬底201的材料的热膨胀系数的材料在衬底201的正面202上形成压缩膜207。由于衬底201和膜207在沉积后冷却，因此膜207的材料的收缩程度小于衬底201的材料的收缩程度，并且向衬底201的正面202施加力。该力与电容器203在衬底201上施加的力相对抗，从而进一步降低了翘曲206。如图18所示，工艺300通常继续进行在ILD层207中形成用于接触件的孔的步骤325以及用导电材料填充孔以形成接触件221的步骤327。
图6所示的工艺300和图7至图18所示的器件200仅示出了一种类型的深沟槽电容器203。通常，本发明的构思可应用于任何类型的深沟槽电容器。本发明的方法和结构尤其适用于具有包括两层以上导电层的深沟槽电容器的集成电路器件。在一些实施例中，DTC203具有两层导电层。导电层的数量越多，应力越大。因此，在一些实施例中，DTC203具有三层导电层。
图19示出了器件200A，其是使用具有两个导电层结构的深沟槽电容器203A的器件200的一个实例。电容器203A包括第一介电层213A、第一导电层215A、第二介电层213B和第二导电层215B。这些层可具有前述介电层213和导电层215的任何合适的组成。例如，介电层213A、213B可以是ONO多层结构，并且导电层215A、215B可以是掺杂多晶硅。
在一些实施例中，应力诱导结构205至少部分与深沟槽电容器203同时形成。在一些这样的实施例中，通过将填充DTC203的沟槽的膜213和215应用于背面204来实现。在一些实施例中，同时地，填充沟槽212以形成DTC203和填充沟槽214以形成应力诱导结构205。这样会产生图20所示的器件200B的应力诱导结构205B。虽然结构205B和深沟槽电容器相似，但是在大多数的实施例中，结构205，即使是形成了205B，也不会成为器件200的电路的任何部分。
在一些可选的实施例中，在衬底201的背面204上没有形成沟槽。在这些实施例中，膜213、215可覆盖背面204，但是，通常不会为其本身提供足够的应力以抵消DTC203引起的翘曲。在一些实施例中，在背面204的上方形成额外的张力膜223，从而形成应力诱导结构205。图21示出具有应力诱导结构205C的器件200C。在一些实施例中，不管DTC203的膜213和215中的任一个膜是否涂敷在背面223，具有足够厚度的张力膜223能够充分抵消DTC203引起的应力。通常，这就要求张力膜的厚度至少是1μm。在大多数实施例中，该膜的厚度大于衬底201的正面202上的任何可比材料的膜的厚度。张力膜的实例包括SiO2膜、SiN膜、SiC膜、SiOC膜以及多晶硅膜。
在一些实施例中，器件200用于3D-IC器件内。晶圆翘曲可能影响接合和封装，特别是如果在切割一个或多个晶圆之前将3D-IC器件的两个或多个元件接合。在一些实施例中，本发明的结构和方法尤其适用于这种情形：切割之前先将两个晶圆进行封装或接合。
在一些实施例中，3D-IC器件包括高电压或高功率电路。甚至是在已切割两个晶圆之后，尤其要注意这样器件的翘曲。高电压和高功率电路易于出现大幅度的温度变化。由于翘曲是由热膨胀系数的失配引起的，所以3D-IC器件内的管芯可能随着温度的变化而发生翘曲和不翘曲。由于本发明没有提供应力平衡结构，所以，翘曲或不翘曲现象可引起3D-IC器件内管芯中的一个管芯与另一个管芯或结构分离或分层。
图22提供了根据本发明一些实施例的形成3D-IC器件的方法310的流程图。工艺310包括步骤101，提供晶圆形式的衬底201；步骤103，在晶圆201的正面202上形成深沟槽电容器203；以及步骤105，在晶圆201的背面204上形成具有张应力的结构205。可微调结构205的尺寸，特别是沟槽214的深度（如果包括），以平衡正面应力。步骤109是方法310的可选部分。在步骤109中，在DTC103的上方形成压缩膜207。在一些实施例中，利用膜207的厚度来微调晶圆201的正面202和晶圆201的背面204上的应力之间的平衡。
步骤329为将晶圆201接合至第二晶圆，且在步骤331中，切割晶圆。当翘曲206保持为小时，有利于接合。然而，甚至在切割一个或两个晶圆之后，有利于降低翘曲。因此，在一些实施例中，接合329之前切割一个或两个晶圆。
图23提供了可由方法310产生的3D-IC器件500的实例。器件500是本发明一些实施例提供的引线接合的3D-IC器件的实例。器件500包括高电压或高功率集成电路器件400和具有DTC203和背面应力诱导结构205的一个或多个器件200。在图23的实例中，器件500包括两个这种器件：器件200A和器件200B。缓冲层511将器件200B和器件400隔开。器件200A、200B和400被封装在一起，且通过引线511连接至引线框架（lead frame）515。器件400包括半导体衬底401、高电压或高功率器件403以及金属互连结构407。
图24提供了可由方法310产生的3D-IC器件510的实例。器件510是本发明一些实施例提供的3D-IC器件的实例，其中，3D-IC器件的元件通过硅通孔（TSV）连接。器件510包括通过TSV503连接的高电压或高功率集成电路器件400和器件200。TSV503穿过半导体衬底401且连接至器件200的金属互连结构209的焊料凸块505。TSV503可直接或通过器件400的金属互连件407连接至焊料凸块501。焊料凸块501用于将3D-IC器件510连接至其他器件。在一些实施例中，在切割之前，连接器件200和400。
图25提供了可由方法310产生的3D-IC器件520的实例。器件520是本发明一些实施例提供的3D-IC器件的实例，其中，3D-IC器件的元件通过直接的晶圆和晶圆接合连接。器件520包括高电压或高功率集成电路器件400以及具有DTC203和背面应力诱导结构205的器件200。通过任何合适的直接连接方法，将器件400的金属互连结构407直接连接至器件200的金属互连结构209。例如，适用的直接连接方法的实例包括共晶接合、焊料接合以及热压接合。TSV503穿过衬底401或衬底201，以形成金属互连结构407和409与焊料凸块501之间的连接。焊料凸块501用于将3D-IC器件520连接至其他器件。在一些实施例中，在切割之前，连接器件200和400。
本发明提供了包括一种包括半导体衬底的集成电路器件，其中，半导体衬底在正面上具有深沟槽电容器和在背面上具有应力诱导结构。背面上的应力诱导结构包括张力材料，该张力材料对衬底施加的应力与由深沟槽电容器施加的应力相对抗。背面上的结构包括一层或多层张力膜，其中，张力膜的厚度大于正面上的任何相似的膜的厚度或填充形成在衬底背面中的沟槽的张力材料的厚度。
本发明提供了制造一种集成电路器件的方法，该方法包括在晶圆的正面上形成深沟槽电容器，以及在晶圆的背面上形成具有张应力的结构。背面上的结构向衬底上施加的应力和深沟槽电容器施加的应力相对抗。背面上的结构包括一层或多层张力膜，该张力膜的厚度大于正面上的任何相似膜的厚度或填充形成在衬底背面中的沟槽的张力材料的厚度。
在一些实施例和实例中已经示出和/或描述了本发明的元件和部件。虽然只在一个实施例或实例中描述了具体元件或部件，或那些具体元件或部件的广义或狭义形式，但是在一定程度上，广义或狭义形式的所有元件和部件可与其他元件或部件在一定程度上组合在一起，这样的组合对于本领域的普通技术人员来说是符合逻辑的。

Claims (19)

1.一种集成电路器件，包括：
第一半导体衬底，具有正面和背面；
第一结构，包括形成在所述正面向下延伸的第一沟槽中的深沟槽电容器，所述第一结构包括向所述第一半导体衬底施加压应力的张力材料；以及
第二结构，形成在所述第一半导体衬底的所述背面上，所述第二结构包括向所述第一半导体衬底施加压应力的张力材料；
其中，所述第二结构包括选自由下列组成的组的结构：厚度大于位于所述正面上的相同材料的任何膜的厚度的一层或多层张力膜；以及
填充所述第一半导体衬底内的沟槽的张力材料；
附加背面层，邻接所述第二结构，所述附加背面层向所述第一半导体衬底的背面施加附加应力。
2.根据权利要求1所述的集成电路器件，其中，所述第二结构未形成所述器件的电路的一部分。
3.根据权利要求1所述的集成电路器件，其中，所述第二结构包括填充所述第一半导体衬底内的第二沟槽的张力材料。
4.根据权利要求3所述的集成电路器件，其中，所述背面上的用张力材料填充的沟槽和所述正面上的所述深沟槽电容器形成于其内的沟槽具有与使用相同光刻掩模形成的两组沟槽相一致的图案。
5.根据权利要求4所述的集成电路器件，其中，所述背面上的第二沟槽的深度与所述正面上的第一沟槽的深度明显不同。
6.根据权利要求1所述的集成电路器件，其中，所述第二结构包括总厚度大于1μm的一个以上的涂层。
7.根据权利要求1所述的集成电路器件，进一步包括：
第二半导体衬底，在其上形成有电路；
其中，所述器件是3D-IC器件。
8.根据权利要求7所述的集成电路器件，还包括：形成在所述第二半 导体衬底上的高电压或高功率电路。
9.根据权利要求7所述的集成电路器件，其中，所述第二半导体衬底的电路通过硅通孔连接至包括所述深沟槽电容器的电路。
10.根据权利要求7所述的集成电路器件，其中，所述第二半导体衬底的电路通过晶圆与晶圆的接合连接至包括所述深沟槽电容器的电路。
11.一种制造集成电路器件的方法，包括：
提供第一半导体晶圆；
在所述第一半导体晶圆的正面上形成第一结构，所述第一结构包括在所述正面向下延伸的第一沟槽中的深沟槽电容器；以及
在所述第一半导体晶圆的背面上形成压应力诱导的第二结构；
其中，所述第二结构包括选自由下列组成的组的结构：
厚度大于所述正面上的相同材料的任何膜的厚度的一层或多层压缩膜；以及
填充衬底内的沟槽的张力材料；
在所述第一半导体晶圆的背面上形成附加背面层，所述附加背面层邻接所述第二结构，所述附加背面层向所述衬底的背面施加附加应力。
12.根据权利要求11所述的制造集成电路器件的方法，其中，形成的正面结构和背面结构中的第一结构使得所述第一半导体晶圆在一个方向上翘曲，而形成的所述正面结构和所述背面结构中的第二结构使所述翘曲降低了至少一半。
13.根据权利要求11所述的制造集成电路器件的方法，其中，在所述衬底的所述背面上形成所述压应力诱导的第二结构包括在所述第一半导体晶圆中形成第二沟槽，然后用张力材料填充所述第二沟槽。
14.根据权利要求13所述的制造集成电路器件的方法，其中：
形成所述深沟槽电容器包括使用光刻掩模的光刻工艺；以及
在所述背面上形成所述第二结构包括使用相同的掩模蚀刻所述第一半导体晶圆的所述背面中的第二沟槽。
15.根据权利要求13所述的制造集成电路器件的方法，其中，选择位于所述第一半导体晶圆的背面上的第二沟槽的尺寸，以使所述第一半导体 晶圆的背面上的应力和所述正面上的应力平衡。
16.根据权利要求11所述的制造集成电路器件的方法，其中，在所述第一半导体晶圆的背面上形成所述压应力诱导的结构包括形成总厚度大于1μm的一层或多层张力膜。
17.根据权利要求11所述的制造集成电路器件的方法，还包括：
选择所述附加背面层的厚度，以平衡所述第一半导体晶圆的正面和背面上的应力。
18.根据权利要求11所述的制造集成电路器件的方法，还包括：
将所述第一半导体晶圆连接至包括高电压或高功率集成电路的第二半导体晶圆，以形成3D-IC。
19.根据权利要求11所述的制造集成电路器件的方法，还包括：
将所述第一半导体晶圆的电路通过晶圆与晶圆接合连接至第二半导体晶圆的电路。
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