CN108091611A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN108091611A
CN108091611A CN201611046394.XA CN201611046394A CN108091611A CN 108091611 A CN108091611 A CN 108091611A CN 201611046394 A CN201611046394 A CN 201611046394A CN 108091611 A CN108091611 A CN 108091611A
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isolated area
semiconductor fin
remaining
layer
mask layer
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CN108091611B (zh
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张海洋
肖芳元
王彦
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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Abstract

本发明公开了一种半导体装置及其制造方法，涉及半导体技术领域。该方法包括：提供衬底结构，其包括：衬底、在衬底上沿着第一方向延伸的一个或多个半导体鳍片、在半导体鳍片上的硬掩模层、以及在半导体鳍片周围的隔离区；隔离区的上表面与硬掩模层的上表面基本齐平，隔离区包括第一隔离区和第二隔离区，第一隔离区位于半导体鳍片在第一方向上的侧面，第二隔离区位于半导体鳍片在不同于第一方向的第二方向上的侧面。然后，去除硬掩模层。之后，对第一隔离区高于半导体鳍片的区域进行刻蚀。之后，在半导体鳍片和剩余的第一隔离区上形成掩模层。之后，对第二隔离区进行刻蚀，使得剩余的第二隔离区的上表面低于半导体鳍片的上表面。之后，去除掩模层。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体装置及其制造方法。
背景技术
在鳍式场效应晶体管(Fin Field Effect Transistor，FinFET)中，为了提高器件的性能，可以对鳍片的端部进行刻蚀以形成凹陷，然后在凹陷中外延生长半导体材料，从而向沟道引入期望的应力。为了改善外延生长的半导体材料的形貌，可能会在浅沟槽隔离(STI)区上形成伪栅结构。
但是，发明人发现，STI区的上表面低于鳍片的上表面，而随着半导体器件的关键尺寸的逐渐缩小，STI区上的伪栅结构如果稍有偏离则会与鳍片搭起来，也即形成桥(bridge)，这可能会造成漏电现象，从而影响器件的可靠性。
发明内容
本发明的一个目的在于提出一种半导体装置的制造方法，能够得到抬高的隔离区。
根据本发明的一个实施例，提供了一种半导体装置的制造方法，包括：提供衬底结构，所述衬底结构包括：衬底；在所述衬底上沿着第一方向延伸的一个或多个半导体鳍片；在所述半导体鳍片上的硬掩模层；以及在所述半导体鳍片周围的隔离区；其中，所述隔离区的上表面与所述硬掩模层的上表面基本齐平，所述隔离区包括第一隔离区和第二隔离区，所述第一隔离区位于所述半导体鳍片在所述第一方向上的侧面，所述第二隔离区位于所述半导体鳍片在不同于所述第一方向的第二方向上的侧面；去除所述硬掩模层；对所述第一隔离区高于所述半导体鳍片的区域进行刻蚀；在所述半导体鳍片和剩余的第一隔离区上形成掩模层；对所述第二隔离区进行刻蚀，使得剩余的第二隔离区的上表面低于所述半导体鳍片的上表面；去除所述掩模层。
在一个实施例中，所述对所述第一隔离区高于所述半导体鳍片的区域进行刻蚀包括：去除所述第一隔离区高于所述半导体鳍片的区域，以使得剩余的第一隔离区的上表面与所述半导体鳍片的上表面基本齐平。
在一个实施例中，所述对所述第一隔离区高于所述半导体鳍片的区域进行刻蚀包括：去除所述第一隔离区高于所述半导体鳍片的区域的一部分，以使得剩余的第一隔离区的上表面高于所述半导体鳍片的上表面。
在一个实施例中，所述在所述半导体鳍片和剩余的第一隔离区上形成掩模层包括：沉积掩模材料层，以覆盖所述半导体鳍片、剩余的第一隔离区和所述第二隔离区；对沉积的掩模材料层进行平坦化，以使得剩余的掩模材料层与所述第二隔离区基本齐平，所述剩余的掩模材料层作为所述掩模层。
在一个实施例中，所述在所述半导体鳍片和所述剩余的第一隔离区上形成掩模层包括：沉积掩模材料层，以覆盖所述半导体鳍片、所述剩余的第一隔离区和所述第二隔离区；对沉积的掩模材料层进行回刻，以使得剩余的掩模材料层与所述第二隔离区基本齐平，所述剩余的掩模材料层作为所述掩模层。
在一个实施例中，通过带状等离子体定向刻蚀工艺对所述第一隔离区高于所述半导体鳍片的区域进行刻蚀。
在一个实施例中，通过湿法刻蚀去除所述硬掩模层和所述掩模层。
在一个实施例中，所述硬掩模层、所述隔离区和所述掩模层的材料包括硅的氧化物、硅的氮化物或硅的氮氧化物。
在一个实施例中，所述方法还包括：在所述半导体鳍片上形成第一栅极结构，并且在剩余的第一隔离区上形成第二栅极结构。
根据本发明的另一个实施例，提供了一种半导体装置，包括：衬底；位于衬底上沿着第一方向延伸的一个或多个半导体鳍片；和位于所述半导体鳍片周围的隔离区，所述隔离区包括第一隔离区和第二隔离区；其中，所述第一隔离区位于所述半导体鳍片在所述第一方向上的侧面，所述第一隔离区的上表面与所述半导体鳍片的上表面基本齐平，或者，所述第一隔离区的上表面高于所述半导体鳍片的上表面；所述第二隔离区位于所述半导体鳍片在不同于所述第一方向的第二方向上的侧面，并且所述第二隔离区的上表面低于所述半导体鳍片的上表面。
在一个实施例中，所述装置还包括：在所述半导体鳍片上的第一栅极结构，以及在所述第一隔离区上的第二栅极结构。
本发明提供了一种新颖的半导体装置的制造方法，根据该方法可以得到抬高的隔离区，也即第一隔离区，与现有技术相比，第一隔离区的上表面与半导体鳍片的上表面基本齐平或者高于半导体鳍片的上表面，也即第一隔离区的高度有所提升。因此，后续在第一隔离区上形成的伪栅结构(对应后续的第二栅极结构)即使偏离也不会与鳍片搭成桥，减轻了伪栅结构与半导体鳍片搭成桥造成的漏电现象，提高了器件的可靠性。
根据本发明的不同实施例，还可以实现至少下列效果中一项或多项：提高器件性能，提高了器件可靠性，使得工艺流程相对简单，和/或降低了成本。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本发明的示例性实施例，并且连同说明书一起用于解释本发明的原理，在附图中：
图1是根据本发明一个实施例的半导体装置的制造方法的简化流程图；
图2A-图7C示出了根据本发明一个实施例的半导体装置的制造方法的不同阶段的示意图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应理解，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不应被理解为对本发明范围的限制。
此外，应当理解，为了便于描述，附图中所示出的各个部件的尺寸并不必然按照实际的比例关系绘制，例如某些层的厚度或宽度可以相对于其他层有所夸大。
以下对示例性实施例的描述仅仅是说明性的，在任何意义上都不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和装置可能不作详细讨论，但在适用这些技术、方法和装置情况下，这些技术、方法和装置应当被视为本说明书的一部分。
应注意，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义或说明，则在随后的附图的说明中将不需要对其进行进一步讨论。
发明人发现：如果能提升STI区的高度，例如将STI区的高度提升到与半导体鳍片一样高，则可以改善漏电的问题。因此，发明人提出了一种形成抬高的STI区的半导体装置的方法。
图1是根据本发明一个实施例的半导体装置的制造方法的简化流程图。图2A-图7C示出了根据本发明一个实施例的半导体装置的制造方法的不同阶段的示意图。在下文的描述中，除非特别指出，否则，图NA是根据本发明一个实施例的半导体装置的制造方法的一个阶段的俯视图，图NB是沿着图NA中的B-B’截取的截面图，图NC是沿着图NA中的C-C’截取的截面图，其中N为1-7范围内的正整数。
下面结合图1、以及图2A-图7C对根据本发明一个实施例的半导体装置的制造方法进行说明。
如图1所示，首先，在步骤102，提供衬底结构。图2A示出了根据本发明一个实施例的衬底结构的俯视图。图2B是沿着图2A中的B-B’截取的截面图，也可以称为沿着第一方向的截面图。图2C是沿着图2A中的C-C’截取的截面图，也可以称为沿着第二方向的截面图。
如图2A、图2B和图2C所示，衬底结构包括衬底201。衬底201例如可以是硅衬底、III-V族半导体材料的衬底、绝缘体上硅(SOI)衬底等。
衬底结构还包括位于衬底201上沿着第一方向延伸的一个或多个半导体鳍片202和在半导体鳍片202上的硬掩模层203。这里，第一方向是半导体鳍片202延伸的方向，也可以称为沿着沟道的方向。半导体鳍片202的材料与衬底201的材料可以相同，也可以不同。硬掩模层203的材料例如可以是硅的氧化物、硅的氮化物或硅的氮氧化物等。优选地，硬掩模层203的材料可以是硅的氮化物，例如氮化硅。
衬底结构还包括在半导体鳍片202周围的隔离区204。这里，隔离区204的上表面与硬掩模层203的上表面基本齐平，也即，在工艺偏差范围内的齐平。隔离区204包括第一隔离区214和第二隔离区224，第一隔离区214位于半导体鳍片202在第一方向(A-A’方向)上的侧面，第二隔离区224位于半导体鳍片202在不同于第一方向的第二方向(C-C’方向)上的侧面。这里，第二方向例如可以是与第一方向基本垂直的方向，也可以称为垂直于沟道的方向。在一个实施例中，隔离区204的材料可以是诸如氧化物、氮化物、氮氧化物等的电介质材料。
应理解，在衬底结构包括沿着第一方向延伸的多个半导体鳍片202的情况下，在第一方向上的相邻的半导体鳍片202之间的隔离区即为第一隔离区。在衬底结构包括沿着第二方向延伸的多个半导体鳍片202的情况下，在第二方向上的相邻的半导体鳍片202之间的隔离区即为第二隔离区。
衬底结构例如可以通过如下方式来形成：提供初始衬底；在初始衬底上形成图案化的初始硬掩模层；以初始硬掩模层为掩模对初始衬底进行刻蚀，从而形成衬底、在衬底上的第一半导体鳍片和在第一半导体鳍片上的第一硬掩模层；将第一半导体鳍片和第一硬掩模层切断，例如利用单扩散区切断隔离(Single Diffusion Break，SDB)技术将第一半导体鳍片和第一硬掩模层切断，从而形成半导体鳍片和在半导体鳍片上的硬掩模层；之后可以沉积隔离材料，然后对隔离材料进行平坦化，从而形成隔离区。
回到图1，在步骤104，去除硬掩模层203，如图3A、图3B和图3C所示。例如，可以通过湿法刻蚀去除硬掩模层203。在去除硬掩模层203后，露出了半导体鳍片202以及第一隔离区214高于半导体202的区域。
接下来，在步骤106，对第一隔离区214高于半导体鳍片202的区域进行刻蚀。
在一个实现方式中，如图4A、图4B和图4C所示，去除第一隔离区214高于半导体鳍片202的区域的全部，以使得剩余的第一隔离区214A的上表面与半导体鳍片202的上表面基本齐平。在另一个实现方式中，可以去除第一隔离区214高于半导体鳍片202的区域的一部分，以使得剩余的第一隔离区214A的上表面高于半导体鳍片202的上表面。
优选地，可以通过带状等离子体定向刻蚀工艺对第一隔离区214高于半导体鳍片202的区域进行刻蚀。带状等离子体定向刻蚀可以对某个特定方向上的材料进行刻蚀，而对其他方向上的材料基本不刻蚀或刻蚀很少。因此，利用带状等离子体定向刻蚀工艺可以仅刻蚀位于半导体鳍片202在第一方向上的侧面的第一隔离区214，而不刻蚀位于半导体鳍片202在第二方向上的侧面的第二隔离区224。
之后，在步骤108，在半导体鳍片202和剩余的第一隔离区214A上形成掩模层501，如图5A、图5B和图5C所示。
例如，可以沉积掩模材料层(未示出)，以覆盖半导体鳍片202、剩余的第一隔离区214A和第二隔离区224。之后，在一个实现方式中，可以对沉积的掩模材料层进行平坦化，例如化学机械抛光(CMP)，以去除第二隔离区224上的掩模材料层，从而使得剩余的掩模材料层与第二隔离区224基本齐平，剩余的掩模材料层作为掩模层501。或者，在另一个实现方式中，可以对沉积的掩模材料层进行回刻，去除第二隔离区224上的掩模材料层，以使得剩余的掩模材料层与第二隔离区224基本齐平，剩余的掩模材料层作为掩模层501。作为一个示例，掩模层501的材料可以包括硅的氮化物、硅的氧化物或硅的氮氧化物等。
之后，在步骤110，对第二隔离区224进行刻蚀，使得剩余的第二隔离区224A的上表面低于半导体鳍片202的上表面，如图6A、图6B和图6C所示。例如，可以通过干法刻蚀对第二隔离区224进行刻蚀。
之后，在步骤112，去除掩模层501，如图7A、图7B和图7C所示。例如，可以通过湿法刻蚀去除掩模层501。
参见图7B和图7C，剩余的第一隔离区214A的上表面与半导体鳍片202的上表面基本齐平，剩余的第二隔离区224A的上表面低于半导体鳍片202的上表面。另外，如上所述，在去除第一隔离区214高于半导体鳍片202的区域的一部分的情况下，剩余的第一隔离区214A的上表面可以高于半导体鳍片202的上表面。
之后，可以在半导体鳍片202上形成第一栅极结构，并且在剩余的第一隔离区214A上形成第二栅极结构。
根据上述制造方法可以得到抬高的隔离区，也即第一隔离区，与现有技术相比，第一隔离区的上表面与半导体鳍片的上表面基本齐平或者高于半导体鳍片的上表面，也即第一隔离区的高度有所提升。因此，后续在第一隔离区上形成的伪栅结构(对应后续的第二栅极结构)即使偏离也不会与鳍片搭成桥，减轻了伪栅结构与半导体鳍片搭成桥造成的漏电现象，提高了器件的可靠性。
本发明还提供了一种半导体装置，参见图7A、7B和7C，该装置包括：衬底201、位于衬底201上沿着第一方向延伸的一个或多个半导体鳍片202和位于半导体鳍片202周围的隔离区。隔离区包括第一隔离区214A和第二隔离区224A。第一隔离区214A位于半导体鳍片202在第一方向上的侧面，第一隔离区214A的上表面与半导体鳍片202的上表面基本齐平(参见图7B)，或者，第一隔离区214A的上表面高于半导体鳍片的上表面。第二隔离区224A位于半导体鳍片202在不同于第一方向的第二方向上的侧面，并且第二隔离区224A的上表面低于半导体鳍片202的上表面(参见图7C)。
在一个实施例中，半导体装置还可以包括：在半导体鳍片202上的第一栅极结构，以及在第一隔离区214A上的第二栅极结构。
至此，已经详细描述了根据本发明实施例的半导体装置及其制造方法。为了避免遮蔽本发明的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本发明的精神和范围。

Claims (11)

1.一种半导体装置的制造方法，其特征在于，包括：
提供衬底结构，所述衬底结构包括：衬底；在所述衬底上沿着第一方向延伸的一个或多个半导体鳍片；在所述半导体鳍片上的硬掩模层；以及在所述半导体鳍片周围的隔离区；其中，所述隔离区的上表面与所述硬掩模层的上表面基本齐平，所述隔离区包括第一隔离区和第二隔离区，所述第一隔离区位于所述半导体鳍片在所述第一方向上的侧面，所述第二隔离区位于所述半导体鳍片在不同于所述第一方向的第二方向上的侧面；
去除所述硬掩模层；
对所述第一隔离区高于所述半导体鳍片的区域进行刻蚀；
在所述半导体鳍片和剩余的第一隔离区上形成掩模层；
对所述第二隔离区进行刻蚀，使得剩余的第二隔离区的上表面低于所述半导体鳍片的上表面；
去除所述掩模层。
2.根据权利要求1所述的方法，其特征在于，所述对所述第一隔离区高于所述半导体鳍片的区域进行刻蚀包括：
去除所述第一隔离区高于所述半导体鳍片的区域，以使得剩余的第一隔离区的上表面与所述半导体鳍片的上表面基本齐平。
3.根据权利要求1所述的方法，其特征在于，所述对所述第一隔离区高于所述半导体鳍片的区域进行刻蚀包括：
去除所述第一隔离区高于所述半导体鳍片的区域的一部分，以使得剩余的第一隔离区的上表面高于所述半导体鳍片的上表面。
4.根据权利要求1所述的方法，其特征在于，所述在所述半导体鳍片和剩余的第一隔离区上形成掩模层包括：
沉积掩模材料层，以覆盖所述半导体鳍片、剩余的第一隔离区和所述第二隔离区；
对沉积的掩模材料层进行平坦化，以使得剩余的掩模材料层与所述第二隔离区基本齐平，所述剩余的掩模材料层作为所述掩模层。
5.根据权利要求1所述的方法，其特征在于，所述在所述半导体鳍片和所述剩余的第一隔离区上形成掩模层包括：
沉积掩模材料层，以覆盖所述半导体鳍片、所述剩余的第一隔离区和所述第二隔离区；
对沉积的掩模材料层进行回刻，以使得剩余的掩模材料层与所述第二隔离区基本齐平，所述剩余的掩模材料层作为所述掩模层。
6.根据权利要求1所述的方法，其特征在于，通过带状等离子体定向刻蚀工艺对所述第一隔离区高于所述半导体鳍片的区域进行刻蚀。
7.根据权利要求1所述的方法，其特征在于，通过湿法刻蚀去除所述硬掩模层和所述掩模层。
8.根据权利要求1所述的方法，其特征在于，
所述硬掩模层、所述隔离区和所述掩模层的材料包括硅的氧化物、硅的氮化物或硅的氮氧化物。
9.根据权利要求1所述的方法，其特征在于，还包括：
在所述半导体鳍片上形成第一栅极结构，并且在剩余的第一隔离区上形成第二栅极结构。
10.一种半导体装置，其特征在于，包括：
衬底；
位于衬底上沿着第一方向延伸的一个或多个半导体鳍片；和
位于所述半导体鳍片周围的隔离区，所述隔离区包括第一隔离区和第二隔离区；
其中，所述第一隔离区位于所述半导体鳍片在所述第一方向上的侧面，所述第一隔离区的上表面与所述半导体鳍片的上表面基本齐平，或者，所述第一隔离区的上表面高于所述半导体鳍片的上表面；
所述第二隔离区位于所述半导体鳍片在不同于所述第一方向的第二方向上的侧面，并且所述第二隔离区的上表面低于所述半导体鳍片的上表面。
11.根据权利要求10所述的装置，其特征在于，还包括：
在所述半导体鳍片上的第一栅极结构，以及在所述第一隔离区上的第二栅极结构。
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