CN107958934A - 不对称鳍状结构及其制作方法 - Google Patents

不对称鳍状结构及其制作方法 Download PDF

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CN107958934A
CN107958934A CN201610905131.3A CN201610905131A CN107958934A CN 107958934 A CN107958934 A CN 107958934A CN 201610905131 A CN201610905131 A CN 201610905131A CN 107958934 A CN107958934 A CN 107958934A
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finlike component
finlike
component
side wall
layer
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林昭宏
黄同隽
蔡世鸿
郑志祥
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN201610905131.3A priority Critical patent/CN107958934A/zh
Priority to US15/347,797 priority patent/US20180108656A1/en
Publication of CN107958934A publication Critical patent/CN107958934A/zh
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Abstract

本发明公开一种不对称鳍状结构及其制作方法。其中该不对称鳍状结构包含一基底，基底具有一上表面，一鳍状元件由基底延伸而成并且和基底连结，鳍状元件包含一第一侧壁和一第三侧壁，第一侧壁和第三侧壁分别位于鳍状元件的相对两侧，第一侧壁接触基底的上表面以及一外延层接触并仅覆盖鳍状元件的第一侧壁，第三侧壁没有和任何外延层接触。

Description

不对称鳍状结构及其制作方法
技术领域
本发明涉及一种不对称鳍状结构，尤其是涉及一种只有一侧有外延层的不对称鳍状结构。
背景技术
在现有半导体产业中，多晶硅广泛地应用于半导体元件如金属氧化物半导体(metal-oxide-semiconductor，MOS)晶体管中，作为标准的栅极填充材料选择。然而，随着金属氧化物半导体晶体管尺寸持续地微缩，传统多晶硅栅极穿透效应导致元件效能降低，及其难以避免的空乏效应(depletion effect)等问题，使得等效的栅极介电层厚度增加、栅极电容值下降，进而导致元件驱动能力的衰退等困境。
因此现有平面式金属氧化物半导体晶体管的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面的场效晶体管元件，例如鳍状晶体管来取代平面晶体管元件已成为目前的主流发展趋势，其具有立体的栅极通道(channel)结构，可有效减少基底的漏电、降低短通道效应，并具有较高的驱动电流。但由于鳍状晶体管是属于立体的结构，较传统结构复杂，制造难度也偏高，因此如何改良现行制作工艺以提升鳍状晶体管良率即为现今一重要课题
发明内容
根据本发明的一较佳实施例，一种不对称鳍状结构，包含一基底包含一上表面，一第一鳍状元件由基底延伸而成并且和基底连结，其中第一鳍状元件包含一第一侧壁，第一侧壁接触上表面以及一第一外延层接触并仅覆盖第一鳍状元件的第一侧壁，其中第一鳍状元件的材料和第一外延层的材料不同，第一鳍状元件及第一外延层共同形成不对称鳍状结构。
根据本发明的另一较佳实施例，本发明提供一种不对称鳍状结构的制作方法，包含以下步骤，首先提供一基底，一第一鳍状元件和一第二鳍状元件设于基底上并且由基底延伸出来，第一鳍状元件和第二鳍状元件平行，其中第一鳍状元件包含一第一侧壁，第二鳍状元件包含一第二侧壁，第一侧壁不面向第二鳍状元件，第二侧壁不面向第一鳍状元件，之后进行一外延制作工艺，同时仅在第一侧壁上和第二侧壁上分别形成一第一外延层和一第二外延层。
附图说明
图1至图4以及图6至图9为依据本发明的一较佳实施例所绘示的一种不对称鳍状结构的制作方法；
图5为根据本发明的另一较佳实施例所绘示的移除掩模层步骤；
图10为根据本发明的较佳实施例所绘示的鳍状晶体管。
主要元件符号说明
10 基底 11 上表面
12 第一鳍状元件 14 第二鳍状元件
16 第三鳍状元件 18 第四鳍状元件
19 鳍状元件 20 第一帽盖层
21 鳍状元件 22 第二帽盖层
24 第三帽盖层 26 第四帽盖层
28 第一絶缘层 30 第一沟槽
32 第二沟槽 34 掩模层
36 保护层 38 第一外延层
40 第二外延层 42 第三外延层
44 第四外延层 46 第二絶缘层
48 栅极结构 50 多晶硅栅极
52 栅极介电层 100 不对称鳍状结构
112 第一侧壁 114 第二侧壁
116 第三侧壁 118 第四侧壁
119 侧壁 200 不对称鳍状结构
212 第五侧壁 214 第六侧壁
216 第七侧壁 218 第八侧壁
300 不对称鳍状结构 312 凹陷
400 不对称鳍状结构 500 鳍状晶体管
具体实施方式
图1至图4以及图6至图9为依据本发明的一较佳实施例所绘示的一种不对称鳍状结构的制作方法。如图1所示，首先提供一基底10，基底10可以为一硅(Silicon)基底、一锗(Germanium)基底、一砷化镓(Gallium Arsenide)基底、一锗化硅(Silicon Germanium)基底、一磷化铟(Indium Phosphide)基底、一氮化镓(Gallium Nitride)基底、一碳化硅(Silicon Carbide)基底或是一硅覆绝缘(silicon on insulator,SOI)基底。基底10上设有第一区域A，在第一区域A的基底10上设有多个鳍状元件，例如，一第一鳍状元件12、一第二鳍状元件14、一第三鳍状元件16和一第四鳍状元件18共四个鳍状元件依序排列，但鳍状元件的个数视产品需求而调整，不限于图1中所绘示的四个。第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18的材料较佳为硅，或是具有堆叠的外延材料，例如选自锗化硅(SiGe)、碳化硅(SiC)、磷化硅(SiP)等化合物半导体的组合，第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18互相平行。第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18都是接触基底10并且由基底10延伸出来，较佳地，第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18的材料和基底10的材料完全相同。在第一鳍状元件12的顶面上、第二鳍状元件14的顶面上、第三鳍状元件16的顶面上和第四鳍状元件18的顶面上分别形成有第一帽盖层20、第二帽盖层22、第三帽盖层24和第四帽盖层26，第一帽盖层20、第二帽盖层22、第三帽盖层24和第四帽盖层26的材料可以为氮化硅、氧化硅等与鳍状元件。另外鳍状元件之间的间距有两种，此两种间距会交替设置在鳍状元件之间。举例而言，在第一鳍状元件12和第二鳍状元件14之间的间距为第一间距S1，第三鳍状元件16和第四鳍状元件18之间的间距也是第一间距S1，在第二鳍状元件14和第三鳍状元件16之间的间距是第二间距S2，第一间距S1小于第二间距S2。根距本发明的一实施例，第一间距S1为11纳米，第二间距S2为19纳米，但不限于此。
此外，第一鳍状元件12包含一第一侧壁112和一第五侧壁212，第一侧壁112和第五侧壁212分别位于第一鳍状元件12的相对两侧，也就是说第一侧壁112不邻接第五侧壁212，第一侧壁112不面向第二鳍状元件14，但第五侧壁212则面向第二鳍状元件14，第一侧壁112接触基底10的一上表面11；第二鳍状元件14包含一第二侧壁114和一第六侧壁214，第二侧壁114和第六侧壁214分别位于第二鳍状元件14的相对两侧，也就是说第二侧壁114不邻接第六侧壁214，再者第二侧壁114不面向第一鳍状元件12，但第六侧壁214则面向第一鳍状元件12，第二侧壁114接触基底10的上表面11，同样地第三鳍状元件16包含一第三侧壁116和一第七侧壁216，第三侧壁116和第七侧壁216分别位于第三鳍状元件16的相对两侧，同样地第四鳍状元件18包含一第四侧壁118和一第八侧壁218，第四侧壁118和第八侧壁218分别位于第四鳍状元件18的相对两侧，第三侧壁116不面向第四鳍状元件18，第四侧壁118不面向第三鳍状元件16。之后全面形成一第一絶缘层28覆盖基底10、第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18，平坦化第一絶缘层28和第一帽盖层20的顶面切齐。之后可进行掺质注入步骤，在第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18中形成掺杂阱(图未示)。
如图2所示，部分移除第一絶缘层28使得部分的第一鳍状元件12、部分的第二鳍状元件14、部分的第三鳍状元件16和部分的第四鳍状元件18曝露出来，此时在第一鳍状元件12和第二鳍状元件14之间形成一第一沟槽30、在第三鳍状元件16和第四鳍状元件18之间形成第一沟槽30，在第二鳍状元件14和第三鳍状元件16之间形成一第二沟槽32，第二沟槽32的宽度W2大于第一沟槽30的宽度W1。移除部分的第一絶缘层28的方式可以为一清洗或蚀刻制作工艺，例如包含在具有氨气和三氟化氮的环境下移除第一絶缘层28。之后可进行另一掺质注入步骤，在第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18注入掺质以调整第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18的临界电压，依据本发明的较佳实施例，第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18的材料较佳是硅，本掺质注入步骤的目的主要是用于把硅的临界电压调整为接近锗化硅的电压，以配合后续在第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18上形成的锗化硅的临界电压。
如图3所示，形成一掩模层34顺应地覆盖第一鳍状元件12、第二鳍状元件14、第三鳍状元件16、第四鳍状元件18和第一絶缘层28，此外掩模层34也顺应地覆盖第一沟槽30和第二沟槽32，但由于第一沟槽30的宽度W1较小，掩模层34又特意设计其厚度使得填入第一沟槽30的掩模层34会将第一沟槽30的开口完全封闭，并且在第一沟槽30内留下一空隙，在其它实施例中，掩模层34在第一沟槽30内可以不留空隙。此外，第二沟槽32的宽度W2较第一沟槽30的宽度W1大，因此第二沟槽32的开口未被掩模层34封闭。掩模层34可以为氧化硅，其形成方式可利用原子层化学气相沉积、物理气相沉积或化学气相沉积等制作工艺形成。根据本发明的一实施例，掩模层34的厚度为55埃，但不限于此。
如图4所示，非等向性移除掩模层34使得第一侧壁112、第二侧壁114、第三侧壁116和第四侧壁118曝露出来，并且保留在第一沟槽30内的掩模层34。详细来说，由于第一沟槽30的开口被掩模层34封闭，而第二沟槽32开口是打开的，因此在移除掩模层34时，第一沟槽30中的掩模层34会被保留，也就是说第五侧壁212、第六侧壁214、第七侧壁216和第八侧壁218未被曝露出来，如此就造成了第一鳍状元件12上的相对两个侧壁一个被掩模层34遮蔽，一个未被遮蔽，同样地，第二鳍状元件14、第三鳍状元件16和第四鳍状元件18上的相对两个侧壁也是一个被掩模层34遮蔽，一个未被遮蔽。
图5为根据本发明的另一较佳实施例所绘示的移除掩模层步骤，其中具有相同功能的元件将给予相同的元件符号。图5为接续图3的制作工艺，如图5所示，若是基底10分为一第一区域A和一第二区域B，第一区域A为PMOS区或NMOS区而第二区域B为NMOS区或PMOS区，在第一区域A中的鳍状元件的总数为单数，请一并参考图4和图5，要使得鳍状元件上的相对两侧的侧壁一个被掩模层遮蔽，一个未被遮蔽，必须要有成对的鳍状元件让掩模层可以用封闭沟槽开口的方式遮蔽鳍状元件的侧壁，若是在第一区域A中的鳍状元件的总数为单数，则必定至少有一个鳍状元件19无法配对，通常无法配对的鳍状元件19会位于第一区域A的边缘接近第二区域B的位置，在这种情况下，就需要额外形成一保护层36覆盖部分的落单的鳍状元件19，之后才能进行非等向性移除掩模层34，此外由于第二区域B中的鳍状元件21在后续的制作工艺和第一区域A的鳍状元件不同，因此也需要用保护层36覆盖第二区域B中的鳍状元件21，之后才能进行非等向性移除掩模层。因此在图5的步骤中，形成一保护层36覆盖部分的落单的鳍状元件19和覆盖第二区域B，之后进行非等向性移除掩模层，使得部分的掩模层34被移除，曝露出第一侧壁112、第二侧壁114、第三侧壁116、第四侧壁118和落单的鳍状元件的一侧壁119，然后移除保护层36。图4和图5的差异只在于图5中多了第二区域B中的鳍状元件21以及在第一区域A中多一个落单的鳍状元件19，图5的后续的制作工艺就和图4的后续制作工艺相同，因此后续制作工艺只以接续图4的制作工艺为例。
图6为接续图4的制作工艺步骤。如图6所示，选择性薄化曝露出来的第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18，详细来说，薄化过后，在第一絶缘层28中的第一鳍状元件12具有一第一宽度T1，而在第一絶缘层28之外的第一鳍状元件12具有一第三宽度T3，第一宽度T1大于第三宽度T3，此外，在薄化过后，第一鳍状元件12的第一侧壁112具有一阶梯轮廓，换句话说，第一侧壁112上会有一凹陷312，而第五侧壁212则为一平坦轮廓。同样地薄化过后，在第一絶缘层28中的第二鳍状元件14、第三鳍状元件16和第四鳍状元件18的宽度会比在第一絶缘层28之外的第二鳍状元件14、第三鳍状元件16和第四鳍状元件18大，在第二侧壁114、第三侧壁116和第四侧壁118上分别会有一凹陷。
如图7所示，进行一外延制作工艺，同时仅在第一鳍状元件12的第一侧壁112上形成一第一外延层38、仅在第二鳍状元件14的第二侧壁114上形成一第二外延层40、仅在第三鳍状元件16的第三侧壁116上形成一第三外延层42和仅在第四鳍状元件18的第四侧壁118上形成一第四外延层44。值得注意的是：由于掩模层34依然覆盖第一沟槽30，因此第五侧壁212、第六侧壁214、第七侧壁216和第八侧壁218上都没有形成任何外延层。至此本发明的不对称鳍状结构已经完成，第一鳍状元件12结合第一外延层38构成一不对称鳍状结构100，同样的第二鳍状元件14结合第二外延层40构成一不对称鳍状结构200，第三鳍状元件16结合第三外延层42构成一不对称鳍状结构300，第四鳍状元件18结合第四外延层44构成一不对称鳍状结构400。此外，在图5中的保护层36也可以留到外延制作工艺完成之后才移除。其中，第一外延层38、第二外延层40、第三外延层42和第四外延层44可与第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18为相同材料或不同材料，例如选自锗化硅(SiGe)、碳化硅(SiC)、磷化硅(SiP)等化合物半导体的组合，在本实施例中，第一外延层38、第二外延层40、第三外延层42和第四外延层44与第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18为不同材料，而第一外延层38、第二外延层40、第三外延层42和第四外延层44较佳为锗化硅，第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18为硅。
如图8所示，形成一第二絶缘层46覆盖第一絶缘层28，并且平坦化第二絶缘层46和第一帽盖层20的顶面切齐。如图9所示，移除部分的第二絶缘层46和掩模层34，并且移除整个第一帽盖层20、整个第二帽盖层22、整个第三帽盖层24和整个第四帽盖层26，使得至少部分的第一外延层38、部分的第二外延层40、部分的第三外延层42和部分的第四外延层44曝露出来。此时第二外延层40和第三外延层42之间的间距为第一间距S1，也就是说第二外延层40和第三外延层42之间的间距和第一鳍状元件12和第二鳍状元件14之间的间距相同。
图10为根据本发明的较佳实施例所绘示的鳍状晶体管。如图10所示，形成一栅极结构48横跨不对称鳍状结构100/200/300/400，栅极结构48包含一多晶硅栅极50和一栅极介电层52。之后可以在第一鳍状元件12、第二鳍状元件14、第三鳍状元件16和第四鳍状元件18中形成源极/漏极掺杂区(图未示)。至此第一鳍状元件12、第一外延层38、栅极结构48和源极/漏极掺杂区构成一鳍状晶体管500，其它如第二鳍状元件14、第三鳍状元件16、第四鳍状元件18、第二外延层40、第三外延层42、第四外延层44、栅极结构48和源极/漏极掺杂区也各自组成鳍状晶体管。以鳍状晶体管500来看，当开启时，鳍状晶体管500的通道(channel)会部分形在第一鳍状元件12中，另一部分会形成在第一外延层38中，由于第一鳍状元件12的材料较佳为硅，第一外延层38较佳为锗化硅，为了让通道的开关条件一致，在图2的步骤已预先将硅的临界电压调整为趋近于锗化硅的临界电压。
此外，在后续制作工艺中，视情况需要，多晶硅栅极50可以被移除以金属电极取代，并且在形成金属电极之前，可以先形成高介层常数的介电层以及功函数层横跨各个不对称鳍状结构。根据本发明的较佳实施例，利用本发明所形成的鳍状晶体管500较佳为P型鳍状晶体管。
图9为依据本发明的一较佳实施例所绘示的一种不对称鳍状结构组，不对称鳍状结构组可以由单个或多个不对称鳍状结构所组成，如图9所示，不对称鳍状结构组包含一不对称鳍状结构100，不对称鳍状结构100包含基底10，基底10具有一上表面11，一第一鳍状元件12由基底10延伸而成并且和基底10接触且连结，不对称鳍状结构组可以选择性地另包含一不对称鳍状结构200，一第二鳍状元件14由基底10延伸而成并且和基底10接触且连结，第二鳍状元件14和第一鳍状元件12平行，此外第一鳍状元件12包含一第一侧壁112，第一侧壁112接触基底10的上表面11，一第一外延层38接触并仅覆盖第一鳍状元件12的第一侧壁112，第一鳍状元件12的材料和第一外延层38的材料不同；其中第二鳍状元件14包含一第二侧壁114，第二侧壁114接触基底10的上表面11并且可选择性地和第一侧壁112平行，一第二外延层40接触并仅部分覆盖第二鳍状元件14的第二侧壁114，其中第二鳍状元件14的材料和第二外延层40的材料不同，另外，第一侧壁112不面向第二鳍状元件114，第二侧壁114不面向第一鳍状元件12。基底10可以为一硅基底、一锗基底、一砷化镓基底、一锗化硅基底、一磷化铟基底、一氮化镓基底、一碳化硅基底或是一硅覆绝缘基底，而第一鳍状元件12的材料和第二鳍状元件14的材料相同，依据本发明的较佳实施例，第一鳍状元件12的材料和第二鳍状元件14的材料皆为硅，此外基底10较佳为硅基底，因此第一鳍状元件12的材料、第二鳍状元件14的材料和基底10的材料相同，而第一外延层38和第二外延层40的材料相同，第一外延层38和第二外延层40的材料皆为锗化硅。当在在其它实施例中，基底10、第一鳍状元件12的材料和第二鳍状元件14的材料也可以不相同。
值得注意的是：第一鳍状元件12上另包含有一第五侧壁212，第五侧壁和第一侧壁112较佳为互相平行，第一侧壁112和第五侧壁212分别位于第一鳍状元件12的相对两侧，且第一侧壁112不邻接第五侧壁212，第五侧壁212没有和任何外延层接触，详细来说，第五侧壁212没有和任何锗化硅接触；此外，第二鳍状元件14另包含一第六侧壁214，第六侧壁214和第二侧壁114较佳为互相平行，第二侧壁114和第六侧壁214分别位于第二鳍状元件14的相对两侧，且第六侧壁214不邻接第二侧壁114，第六侧壁214上没有和任何外延层接触，详细来说，第六侧壁214没有和任何锗化硅接触。另外第五侧壁212面向第二鳍状元件14，第六侧壁214面向第一鳍状元件12，第五侧壁212面向第六侧壁214。
第一鳍状元件12和第一外延层38组成一个不对称鳍状结构100，第二鳍状元件14和第二外延层40组成另一个不对称鳍状结构200，不对称鳍状结构100和不对称鳍状结构200构成不对称鳍状结构组。详细来说，不对称鳍状结构100的轮廓是两侧不对称的，举例而言，在第一鳍状元件12只有第一侧壁112上有第一外延层38，在第五侧壁212上则没有第一外延层38。若是对称的情况，则在第一侧壁112和第五侧壁212都需要有第一外延层38。不对称鳍状结构200也是和不对称鳍状结构100相同的情形。不对称鳍状结构组，可依产品需求在基底10上重复出现多次，举例而言，基底上可以另包含不对称鳍状结构300和构成不对称鳍状结构400，基本上不对称鳍状结构100和不对称鳍状结构300的结构相同，不对称鳍状结构200和不对称鳍状结构400的结构相同，也就是说不对称鳍状结构300和构成不对称鳍状结构400构成了另一个不对称鳍状结构组，不对称鳍状结构300由第三鳍状元件16结合第三外延层42所构成，不对称鳍状结构400由第四鳍状元件18结合第四外延层44所构成。值得注意的是第三外延层42和第二外延层40之间为第一间距S1，第一鳍状元件12和第二鳍状元件14之间也为第一间距S1，也就是说第一鳍状元件12和第二鳍状元件14之间的间距和第三外延层42和第二外延层40之间的间距相同。
此外，不对称鳍状结构100的轮廓构成一个旗子轮廓加上旗杆轮廓，第一鳍状元件12即是旗子轮廓，而第一外延层38即是旗杆轮廓。也就是说不对称鳍状结构100的轮廓是不对称的，第一鳍状元件12只有一侧有第一外延层38。同样地，不对称鳍状结构200、不对称鳍状结构300和不对称鳍状结构400也都各自构成旗子轮廓加上旗杆轮廓，不对称鳍状结构200、不对称鳍状结构300和不对称鳍状结构400的轮廓也都是不对称的。一第一絶缘层28位于第一鳍状元件12和第二鳍状元件14之间，一掩模层34在第一鳍状元件12和第二鳍状元件14之间，并且覆盖第一絶缘层28，第一絶缘层28和掩模层34不接触第一外延层38和第二外延层40。第一絶缘层28和掩模层34较佳为氧化硅。本发明的不对称鳍状结构组可应用在鳍状晶体管500，如图10所示，一栅极结构48横跨并接触由第一鳍状元件12和第一外延层38组成的不对称鳍状结构100，栅极结构48也可以横跨由第二鳍状元件14和第二外延层40组成的不对称鳍状结构200、第三鳍状元件16和第三外延层42组成的不对称鳍状结构300和第四鳍状元件18和第四外延层44组成的不对称鳍状结构400，栅极结构48包含一多晶硅栅极50和一栅极介电层52。
本发明只在一个鳍状元件上一个侧壁形成外延层，有别于传统技术上以外延层包覆一个鳍状元件的至少三个侧壁，如此以本发明的方式，外延层就不会占据过多的鳍状元件的间距，可以避免在后续制作工艺中，功函数层无法顺应地填入过窄的鳍状元件的间距。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (18)

1.一种不对称鳍状结构，包含：
基底，包含一上表面；
第一鳍状元件，由该基底延伸而成并且和该基底连结，其中该第一鳍状元件包含第一侧壁，该第一侧壁接触该上表面；以及
第一外延层，接触并仅覆盖该第一鳍状元件的该第一侧壁，其中该第一鳍状元件及该第一外延层共同形成该不对称鳍状结构。
2.如权利要求1所述的不对称鳍状结构，其中该第一鳍状元件的材料和该第一外延层的材料不同。
3.如权利要求1所述的不对称鳍状结构，另包含：第三侧壁位于该第一鳍状元件上，该第一侧壁和该第三侧壁分别位于该第一鳍状元件的相对两侧，其中该第三侧壁没有和任何外延层接触。
4.如权利要求1所述的不对称鳍状结构，另包含：
第二鳍状元件，由该基底延伸出来并且和该基底连结，该第二鳍状元件和该第一鳍状元件平行，其中该第二鳍状元件包含第二侧壁，该第二侧壁接触该上表面；
第二外延层，接触并仅部分覆盖该第二鳍状元件的该第二侧壁，其中该第二鳍状元件的材料和该第二外延层的材料不同。
5.如权利要求4所述的不对称鳍状结构，另包含：第四侧壁，位于该第二鳍状元件上，该第二侧壁和该第四侧壁分别位于该第二鳍状元件的相对两侧，其中该第四侧壁没有和任何外延层接触。
6.如权利要求4所述的不对称鳍状结构，其中该第二侧壁不面向该第一鳍状元件。
7.如权利要求4所述的不对称鳍状结构，另外包含一絶缘层位于该第一鳍状元件和该第二鳍状元件之间，该絶缘层不接触该第一外延层和该第二外延层。
8.如权利要求1所述的不对称鳍状结构，其中该第一鳍状元件为硅，该第一外延层为锗化硅。
9.如权利要求1所述的不对称鳍状结构，另包含栅极结构，横跨该第一鳍状元件。
10.如权利要求1所述的不对称鳍状结构，其中该第一鳍状元件和该基底为相同材料。
11.一种不对称鳍状结构的制作方法，包含：
提供一基底，一第一鳍状元件和一第二鳍状元件设于该基底上并且由该基底延伸出来，该第一鳍状元件和该第二鳍状元件平行，其中该第一鳍状元件包含一第一侧壁，该第二鳍状元件包含一第二侧壁，该第一侧壁不面向该第二鳍状元件，该第二侧壁不面向该第一鳍状元件；以及
进行一外延制作工艺，同时仅在该第一侧壁上和该第二侧壁上分别形成一第一外延层和一第二外延层。
12.如权利要求11所述的一种不对称鳍状结构的制作方法，其中在进行该外延制作工艺之前另包含：
在该第一鳍状元件上形成一第一帽盖层，在该第二鳍状元件上形成一第二帽盖层；
全面形成一第一絶缘层覆盖该基底、该第一鳍状元件和该第二鳍状元件，该第一絶缘层和第一帽盖层的顶面切齐；
部分移除该第一絶缘层使得部分的该第一鳍状元件和部分的该第二鳍状元件曝露出来，并且该第一鳍状元件和该第二鳍状元件之间形成一沟槽；
形成一掩模层顺应地覆盖该第一鳍状元件、该第二鳍状元件和该第一絶缘层，并且该掩模层将该沟槽的开口封闭；以及
非等向性移除该掩模层使得该第一侧壁和该第二侧壁曝露出来，并且保留在该沟槽内的该掩模层。
13.如权利要求12所述的一种不对称鳍状结构的制作方法，另包含：在非等向性移除该掩模层之后，进行一外延制作工艺之前，薄化曝露出来的该第一鳍状元件和该第二鳍状元件。
14.如权利要求12所述的一种不对称鳍状结构的制作方法，其中在形成该第一外延层和该第二外延层之后，另包含：
形成一第二絶缘层，覆盖该第一絶缘层，并且该第二絶缘层和该第一帽盖层的顶面切齐；
移除部分的第二絶缘层和该掩模层，使得至少部分的该第一外延层和部分的该第二外延层曝露出来；以及
形成一栅极结构横跨该第一鳍状元件、该第二鳍状元件、该第一外延层和该第二外延层。
15.如权利要求11所述的一种不对称鳍状结构的制作方法，另包含：一第三鳍状元件和一第四鳍状元件由该基底延伸出来，该第一鳍状元件、该第二鳍状元件、该第三鳍状元件和该第四鳍状元件依序排列，该第三鳍状元件包含一第三侧壁，该第四鳍状元件包含一第四侧壁，该第三侧壁不面向该第四鳍状元件，该第四侧壁不面向该第三鳍状元件。
16.如权利要求15所述的一种不对称鳍状结构的制作方法，另包含：在进行该外延制作工艺时，同时仅在该第三侧壁上和该第四侧壁上分别形成一第三外延层和一第四外延层。
17.如权利要求16所述的一种不对称鳍状结构的制作方法，其中该第一鳍状元件和该第二鳍状元件之间包含一第一间距，该第二外延层和第三外延层之间包含该第一间距。
18.如权利要求17所述的一种不对称鳍状结构的制作方法，其中该第一鳍状元件和该第二鳍状元件之间包含一第一间距，该第二鳍状元件和该第三鳍状元件之间包含一第二间距，该第三鳍状元件和该第四鳍状元件包含该第一间距，该第一间距小于该第二间距。
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