CN102820227B - 一种深沟槽超级pn结的形成方法 - Google Patents
一种深沟槽超级pn结的形成方法 Download PDFInfo
- Publication number
- CN102820227B CN102820227B CN201110151784.4A CN201110151784A CN102820227B CN 102820227 B CN102820227 B CN 102820227B CN 201110151784 A CN201110151784 A CN 201110151784A CN 102820227 B CN102820227 B CN 102820227B
- Authority
- CN
- China
- Prior art keywords
- medium
- layer
- junction
- epitaxial material
- epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 59
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000008021 deposition Effects 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 7
- 238000001020 plasma etching Methods 0.000 claims description 6
- 150000004767 nitrides Chemical group 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 101100400452 Caenorhabditis elegans map-2 gene Proteins 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Manufacturing & Machinery (AREA)
- Formation Of Insulating Films (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
Claims (8)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110151784.4A CN102820227B (zh) | 2011-06-08 | 2011-06-08 | 一种深沟槽超级pn结的形成方法 |
PCT/CN2012/076353 WO2012167715A1 (zh) | 2011-06-08 | 2012-05-31 | 一种深沟槽超级pn结的形成方法 |
EP12796409.6A EP2709142B1 (en) | 2011-06-08 | 2012-05-31 | Method for forming a PN superjunction |
JP2014513043A JP5755803B2 (ja) | 2011-06-08 | 2012-05-31 | 深溝を有する新型pn接合の形成方法 |
US13/878,453 US8927386B2 (en) | 2011-06-08 | 2012-05-31 | Method for manufacturing deep-trench super PN junctions |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110151784.4A CN102820227B (zh) | 2011-06-08 | 2011-06-08 | 一种深沟槽超级pn结的形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102820227A CN102820227A (zh) | 2012-12-12 |
CN102820227B true CN102820227B (zh) | 2015-08-19 |
Family
ID=47295478
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110151784.4A Active CN102820227B (zh) | 2011-06-08 | 2011-06-08 | 一种深沟槽超级pn结的形成方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8927386B2 (zh) |
EP (1) | EP2709142B1 (zh) |
JP (1) | JP5755803B2 (zh) |
CN (1) | CN102820227B (zh) |
WO (1) | WO2012167715A1 (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10461152B2 (en) | 2017-07-10 | 2019-10-29 | Globalfoundries Inc. | Radio frequency switches with air gap structures |
US10833153B2 (en) | 2017-09-13 | 2020-11-10 | Globalfoundries Inc. | Switch with local silicon on insulator (SOI) and deep trench isolation |
US10446643B2 (en) | 2018-01-22 | 2019-10-15 | Globalfoundries Inc. | Sealed cavity structures with a planar surface |
US10156676B1 (en) | 2018-02-26 | 2018-12-18 | Globalfoundries Inc. | Waveguides with multiple airgaps arranged in and over a silicon-on-insulator substrate |
US10393960B1 (en) | 2018-02-26 | 2019-08-27 | Globalfoundries Inc. | Waveguides with multiple-level airgaps |
US11410872B2 (en) | 2018-11-30 | 2022-08-09 | Globalfoundries U.S. Inc. | Oxidized cavity structures within and under semiconductor devices |
US10923577B2 (en) | 2019-01-07 | 2021-02-16 | Globalfoundries U.S. Inc. | Cavity structures under shallow trench isolation regions |
US11127816B2 (en) | 2020-02-14 | 2021-09-21 | Globalfoundries U.S. Inc. | Heterojunction bipolar transistors with one or more sealed airgap |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5923073A (en) * | 1991-07-01 | 1999-07-13 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device and semiconductor device manufactured according to the method |
CN1691284A (zh) * | 2004-03-31 | 2005-11-02 | 株式会社电装 | 半导体器件的制造方法 |
CN101872724A (zh) * | 2009-04-24 | 2010-10-27 | 上海华虹Nec电子有限公司 | 超级结mosfet的制作方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61283141A (ja) * | 1985-06-10 | 1986-12-13 | Nec Corp | 半導体装置の製造方法 |
JPH01108746A (ja) * | 1987-10-21 | 1989-04-26 | Toshiba Corp | 半導体装置の製造方法 |
US6399506B2 (en) * | 1999-04-07 | 2002-06-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for planarizing an oxide layer |
JP2001244328A (ja) * | 2000-02-29 | 2001-09-07 | Denso Corp | 半導体装置の製造方法 |
US7811907B2 (en) * | 2005-09-29 | 2010-10-12 | Denso Corporation | Method for manufacturing semiconductor device and epitaxial growth equipment |
CN101510557B (zh) * | 2008-01-11 | 2013-08-14 | 艾斯莫斯技术有限公司 | 具有电介质终止的超结半导体器件及制造该器件的方法 |
JP5572924B2 (ja) * | 2008-06-23 | 2014-08-20 | 富士電機株式会社 | 半導体装置の製造方法 |
JP2010028018A (ja) * | 2008-07-24 | 2010-02-04 | Fuji Electric Device Technology Co Ltd | 半導体ウエハおよび半導体装置と半導体装置の製造方法 |
CN101752252A (zh) * | 2008-12-16 | 2010-06-23 | 上海华虹Nec电子有限公司 | CoolMOS结构中纵向P型区的形成方法 |
JP2011096691A (ja) * | 2009-10-27 | 2011-05-12 | Toshiba Corp | 半導体装置の製造方法 |
CN102280402A (zh) * | 2010-06-12 | 2011-12-14 | 上海华虹Nec电子有限公司 | 刻蚀和填充深沟槽的方法 |
TWI463571B (zh) * | 2011-12-08 | 2014-12-01 | Vanguard Int Semiconduct Corp | 半導體裝置的製造方法 |
-
2011
- 2011-06-08 CN CN201110151784.4A patent/CN102820227B/zh active Active
-
2012
- 2012-05-31 US US13/878,453 patent/US8927386B2/en active Active
- 2012-05-31 JP JP2014513043A patent/JP5755803B2/ja active Active
- 2012-05-31 EP EP12796409.6A patent/EP2709142B1/en active Active
- 2012-05-31 WO PCT/CN2012/076353 patent/WO2012167715A1/zh active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5923073A (en) * | 1991-07-01 | 1999-07-13 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device and semiconductor device manufactured according to the method |
CN1691284A (zh) * | 2004-03-31 | 2005-11-02 | 株式会社电装 | 半导体器件的制造方法 |
CN101872724A (zh) * | 2009-04-24 | 2010-10-27 | 上海华虹Nec电子有限公司 | 超级结mosfet的制作方法 |
Also Published As
Publication number | Publication date |
---|---|
EP2709142A4 (en) | 2015-01-07 |
US8927386B2 (en) | 2015-01-06 |
WO2012167715A1 (zh) | 2012-12-13 |
JP5755803B2 (ja) | 2015-07-29 |
EP2709142A1 (en) | 2014-03-19 |
JP2014522568A (ja) | 2014-09-04 |
CN102820227A (zh) | 2012-12-12 |
US20130196489A1 (en) | 2013-08-01 |
EP2709142B1 (en) | 2016-03-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102820227B (zh) | 一种深沟槽超级pn结的形成方法 | |
CN103065959B (zh) | 一种减小硅刻蚀负载效应的方法 | |
CN104488084B (zh) | 形成锥形氧化物的方法 | |
CN106298945A (zh) | 屏蔽栅沟槽型mosfet工艺方法 | |
US20150050792A1 (en) | Extra narrow diffusion break for 3d finfet technologies | |
CN108231759A (zh) | 半导体结构 | |
CN102709229A (zh) | 一种形成钨塞的方法 | |
CN110416152A (zh) | 深槽隔离结构及工艺方法 | |
CN103928386B (zh) | 一种浅沟槽隔离结构的制造方法 | |
CN102437047B (zh) | 一种sti结构cmp方法以及sti结构制作方法 | |
CN102623339A (zh) | 改善双层栅mos结构的中间氧化层厚度均匀性的方法 | |
CN105206512A (zh) | 改进多重图形化掩膜层的方法 | |
CN103632950B (zh) | 沟槽型双层栅mos中的多晶硅之间的氮化膜形成方法 | |
CN103187353A (zh) | 浅沟槽隔离区的形成方法 | |
CN102820212B (zh) | 一种深沟槽超级pn结的形成方法 | |
CN104851834A (zh) | 一种半导体器件的制备方法 | |
CN103035486A (zh) | 同时填充及平坦化不同尺寸深沟槽的方法 | |
CN102082082A (zh) | 填充高深宽比沟槽的外延工艺方法 | |
CN103000519B (zh) | 去除超级结高压器件外延沉积过程中产生的硅脊的方法 | |
CN103137543A (zh) | 实现浅沟槽隔离的工艺方法 | |
CN103854979B (zh) | 一种超级结外延cmp工艺方法 | |
CN104282612A (zh) | 一种半导体器件浅沟槽隔离结构的制作方法 | |
CN102956537B (zh) | 一种浅槽隔离结构及制作方法 | |
CN102856181A (zh) | 多栅器件的形成方法 | |
CN107994016B (zh) | 浅沟槽隔离结构及其制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Free format text: FORMER OWNER: WUXI HUARUN SHANGHUA TECHNOLOGY CO., LTD. Effective date: 20140403 |
|
C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: WUXI, JIANGSU PROVINCE TO: 214028 WUXI, JIANGSU PROVINCE |
|
TA01 | Transfer of patent application right |
Effective date of registration: 20140403 Address after: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Applicant after: Wuxi CSMC Semiconductor Co., Ltd. Address before: No. 5 Hanjiang Road, national hi tech Industrial Development Zone, Wuxi, China Applicant before: Wuxi CSMC Semiconductor Co., Ltd. Applicant before: Wuxi Huarun Shanghua Technology Co., Ltd. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20171127 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |