CN106298945A - 屏蔽栅沟槽型mosfet工艺方法 - Google Patents

屏蔽栅沟槽型mosfet工艺方法 Download PDF

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CN106298945A
CN106298945A CN201610876651.6A CN201610876651A CN106298945A CN 106298945 A CN106298945 A CN 106298945A CN 201610876651 A CN201610876651 A CN 201610876651A CN 106298945 A CN106298945 A CN 106298945A
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shield grid
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丛茂杰
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

本发明公开了一种屏蔽栅沟槽型MOSFET工艺方法，包含的工艺步骤为：第1步，在硅片上刻蚀沟槽，淀积一层氧化膜，然后填充多晶硅并回刻；第2步，再淀积一层氧化膜并进行化学机械研磨；第3步，进行氧化硅刻蚀，将硅片表面的氧化硅去除；第4步，光刻胶定义出图形，进行有源区沟槽的氧化硅刻蚀；第5步，剥离光刻胶，生长栅氧化膜，淀积多晶硅并回刻。本发明所述的屏蔽栅沟槽型MOSFET工艺方法，相比于传统工艺，在层间氧化硅化学机械研磨之后增加一步湿法刻蚀，将硅片表面的氧化硅膜去除，避免了传统工艺中多晶硅层间氧化膜湿法刻蚀时沿着光刻胶边缘下方横向刻蚀，因此，在版图设计时就不再需要放置dummy trench，节省了管芯面积，同时增加了工艺稳定性。

Description

屏蔽栅沟槽型MOSFET工艺方法
技术领域
本发明涉及半导体器件制造领域，特别是指一种屏蔽栅沟槽型MOSFET工艺方法。
背景技术
屏蔽栅沟槽型MOSFET，作为一种功率器件，具有击穿电压高，导通电阻低，开关速度快的特点。如图1所示，沟槽内填充多晶硅，多晶硅分为两部分：位于沟槽下部的多晶硅形成屏蔽栅多晶硅4，位于沟槽上部的多晶硅构成多晶硅栅极6,两层多晶硅之间隔有氧化硅膜层5。
当前屏蔽栅沟槽型MOSFET的制造工艺，由于在多晶硅间氧化膜湿法刻蚀时会沿着光刻胶下方横向刻蚀，且横向刻蚀量不稳定，所以，在有源区沟槽和终端区沟槽之间要放1～2个赝沟槽(dummy trench)，如图1中1是有源区沟槽，3是终端区沟槽，2即为dummytrench。
具体的工艺来说，是在沟槽刻蚀形成之后，先淀积一层氧化膜，然后在沟槽中淀积填充多晶硅，之后进行回刻，将有源区沟槽的上半部多晶硅刻蚀掉，留下沟槽下半部的对晶硅，然后淀积层间氧化层并进行化学机械平坦化，再涂覆光刻胶定义出图形，采用湿法刻蚀氧化硅，如图2所示，湿法刻蚀在光刻胶下形成横向的钻蚀，在去除光刻胶后，可以看到光刻胶边缘处沟槽内壁氧化硅过刻蚀形成氧化硅空洞，在后续进行栅极多晶硅形成过程中会在原沟槽内壁氧化硅空洞处残留多晶硅，如图1中虚线圈注处，造成工艺的不稳定。
发明内容
本发明所要解决的技术问题是提供一种屏蔽栅沟槽型MOSFET工艺方法，能节省管芯面积，同时提高工艺稳定性。
为解决上述问题，本发明所述的屏蔽栅沟槽型MOSFET工艺方法，包含如下的工艺步骤：
第1步，在硅片上刻蚀沟槽，淀积一层氧化膜，然后填充多晶硅并回刻；
第2步，再淀积一层氧化膜并进行化学机械研磨；
第3步，进行氧化硅刻蚀，将硅片表面的氧化硅去除；
第4步，光刻胶定义出图形，进行有源区沟槽的氧化硅刻蚀；
第5步，剥离光刻胶，生长栅氧化膜，淀积多晶硅并回刻。
进一步地，所述第1步中，对有源区沟槽进行多晶硅回刻，保留有源区沟槽内下部的多晶硅以形成屏蔽栅。
进一步地，所述第2步中，淀积的氧化膜作为层间氧化膜，化学机械研磨后残留的氧化膜厚度不大于
进一步地，所述第3步中，所述的氧化硅刻蚀采用湿法刻蚀。
进一步地，所述第4步中，对有源区沟槽的氧化硅进行刻蚀，形成有源区沟槽内多晶硅栅极与屏蔽栅之间的隔离介质层。
进一步地，所述第5步中，淀积多晶硅并回刻至硅片表面，沟槽内填充的多晶硅与硅片表面平齐，形成多晶硅栅极。
本发明所述的屏蔽栅沟槽型MOSFET工艺方法，相比于传统工艺，在层间氧化硅化学机械研磨之后增加一步湿法刻蚀，将硅片表面的氧化硅膜去除，避免了传统工艺中多晶硅层间氧化膜湿法刻蚀时沿着光刻胶边缘下方横向刻蚀，因此，在版图设计时就不再需要放置dummy trench，节省了管芯面积，同时增加了工艺稳定性。
附图说明
图1是屏蔽栅MOSFET的剖面示意图。
图2是传统工艺氧化硅湿法刻蚀的工艺示意图，光刻胶下的氧化膜出现横向刻蚀，沟槽内壁的氧化膜层出现空洞。
图3是传统工艺沟槽内壁的氧化膜层空洞处出现多晶硅残留示意图。
图4～8是本发明各步工艺示意图。
图9是本发明工艺流程图。
附图标记说明
1是有源区沟槽，2是dummy trench,3是终端区沟槽，4是屏蔽栅多晶硅，5是层间氧化膜，6是多晶硅(栅极)，7是光刻胶。
具体实施方式
本发明所述的屏蔽栅沟槽型MOSFET工艺方法，包含如下的工艺步骤：
第1步，如图4所示，在硅片上刻蚀沟槽，包括有源区沟槽1及终端区沟槽3。淀积一层氧化膜，氧化膜5覆盖硅片表面及沟槽内壁。然后淀积多晶硅，使沟槽内填充满多晶硅。再对有源区沟槽进行多晶硅回刻，保留有源区沟槽内下部的多晶硅以形成屏蔽栅4。
第2步，如图5所示，再淀积一层氧化膜并进行化学机械研磨；淀积的氧化膜作为层间氧化膜5，化学机械研磨后残留的氧化膜厚度不大于
第3步，进行氧化硅的湿法刻蚀，将硅片表面的氧化硅去除，如图6所示。
第4步，光刻胶7定义出图形，进行有源区沟槽的氧化硅刻蚀。如图7所示，对有源区沟槽的氧化硅进行刻蚀，形成有源区沟槽内多晶硅栅极与屏蔽栅之间的隔离介质层。
第5步，剥离光刻胶，生长栅氧化膜，淀积多晶硅并回刻硅片表面形成多晶硅栅极6，如图8所示。
通过上述工艺步骤，本发明优化了工艺程序，在层间氧化硅化学机械研磨之后增加一步湿法刻蚀，将硅片表面的氧化硅膜提前去除，后续的光刻胶直接形成在硅片表面，避免了传统工艺中多晶硅层间氧化膜湿法刻蚀时，光刻胶下的氧化膜在光刻胶边缘处出现横向刻蚀。因此，在版图设计时就不再需要放置dummy trench 2，节省了管芯面积，同时增加了工艺稳定性。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (6)

1.一种屏蔽栅沟槽型MOSFET工艺方法，其特征在于：包含如下的工艺步骤：
第1步，在硅片上刻蚀沟槽，淀积一层氧化膜，然后填充多晶硅并回刻；
第2步，再淀积一层氧化膜并进行化学机械研磨；
第3步，进行氧化硅刻蚀，将硅片表面的氧化硅去除；
第4步，光刻胶定义出图形，进行有源区沟槽的氧化硅刻蚀；
第5步，剥离光刻胶，生长栅氧化膜，淀积多晶硅并回刻。
2.如权利要求1所述的屏蔽栅沟槽型MOSFET工艺方法，其特征在于：所述第1步中，对有源区沟槽进行多晶硅回刻，保留有源区沟槽内下部的多晶硅以形成屏蔽栅。
3.如权利要求1所述的屏蔽栅沟槽型MOSFET工艺方法，其特征在于：所述第2步中，淀积的氧化膜作为层间氧化膜，化学机械研磨后残留的氧化膜厚度不大于
4.如权利要求1所述的屏蔽栅沟槽型MOSFET工艺方法，其特征在于：所述第3步中，所述的氧化硅刻蚀采用湿法刻蚀。
5.如权利要求1所述的屏蔽栅沟槽型MOSFET工艺方法，其特征在于：所述第4步中，对有源区沟槽的氧化硅进行刻蚀，形成有源区沟槽内多晶硅栅极与屏蔽栅之间的隔离介质层。
6.如权利要求1所述的屏蔽栅沟槽型MOSFET工艺方法，其特征在于：所述第5步中，淀积多晶硅并回刻至硅片表面，沟槽内填充的多晶硅与硅片表面平齐，形成多晶硅栅极。
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Cited By (7)

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CN111081540A (zh) * 2019-12-30 2020-04-28 广州粤芯半导体技术有限公司 屏蔽栅沟槽功率器件的制造方法
CN111508846A (zh) * 2020-05-25 2020-08-07 上海华虹宏力半导体制造有限公司 屏蔽栅沟槽型mosfet工艺方法
CN112701043A (zh) * 2020-12-28 2021-04-23 广州粤芯半导体技术有限公司 一种半导体器件的制造方法
CN112802754A (zh) * 2021-01-06 2021-05-14 江苏东海半导体科技有限公司 一种隔离栅沟槽型mosfet器件及其制造方法
CN112864236A (zh) * 2021-03-09 2021-05-28 上海恒灼科技有限公司 一种中高压屏蔽栅场效应晶体管的制备方法
CN113327858A (zh) * 2020-07-15 2021-08-31 上海先进半导体制造有限公司 屏蔽栅场效应晶体管及其制造方法
CN114334661A (zh) * 2022-03-09 2022-04-12 广州粤芯半导体技术有限公司 一种沟槽型双层栅功率mosfet及其制造方法

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