WO2012167715A1 - 一种深沟槽超级pn结的形成方法 - Google Patents

一种深沟槽超级pn结的形成方法 Download PDF

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WO2012167715A1
WO2012167715A1 PCT/CN2012/076353 CN2012076353W WO2012167715A1 WO 2012167715 A1 WO2012167715 A1 WO 2012167715A1 CN 2012076353 W CN2012076353 W CN 2012076353W WO 2012167715 A1 WO2012167715 A1 WO 2012167715A1
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layer
forming
medium
deep trench
dielectric layer
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PCT/CN2012/076353
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English (en)
French (fr)
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吴宗宪
王根毅
袁雷兵
吴芃芃
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无锡华润上华半导体有限公司
无锡华润上华科技有限公司
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Priority to US13/878,453 priority Critical patent/US8927386B2/en
Priority to EP12796409.6A priority patent/EP2709142B1/en
Priority to JP2014513043A priority patent/JP5755803B2/ja
Publication of WO2012167715A1 publication Critical patent/WO2012167715A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

Definitions

  • the present invention relates to semiconductor fabrication techniques, and more particularly to a fabrication technique for a deep trench super PN junction. Background technique
  • the manufacturing process of the conventional super PN junction is mainly realized by deep trench etching, epitaxial filling, and silicon CMP planarization.
  • the method for forming a super PN junction in the conventional technology includes the following steps: Step 1: depositing a single thick epitaxial layer (N type) on the N+ substrate silicon wafer;
  • Step 2 forming a deep trench in the epitaxial layer, specifically, a long thermal oxide layer, then depositing a silicon nitride layer, depositing a plasma enhanced oxide layer, etching the above three layers up to the silicon substrate, and then going Glue, and etching the deep trench with the three films as a hard mask, and then wet removing the remaining plasma enhanced oxide layer on the surface of the silicon nitride;
  • Step 4 Grinding to the silicon surface by CMP to achieve planarization.
  • the present invention has been made in view of the above problems, and aims to provide a super PN junction forming method which is compatible with a conventional process and which is simple in process and high in efficiency.
  • the method for forming a deep trench super PN junction of the present invention comprising: a deposition step of depositing an epitaxial layer on a substrate;
  • a third medium with a second filling step comprising forming the surface layer of the second dielectric layer and the epitaxial material to form a surface filling layer of a prescribed height
  • the first dielectric layer, the second barrier layer, and the surface fill layer are removed to achieve a planarized removal step of the epitaxial material.
  • a plasma etching method may be employed in the etching step.
  • the third medium is filled with an excipient device, the third medium being a fluid medium.
  • the filling fluid medium material and the plasma etch back are used, so that the process complicated by the CMP flattening, the control difficulty, and the high cost can be effectively solved. technical problem.
  • the plasma etching method may be performed by adjusting a selection ratio of etching so that an etching rate to the epitaxial material and the third medium is 1:1.
  • the surface-filled layer has a height at least higher than a highest point of the epitaxial material.
  • the third medium of fluidity is filled with the entire surface of the second dielectric layer and the epitaxial material by rotation, coating using the excipient device.
  • each layer is removed by a wet method.
  • the lowest point of the epitaxial material exceeds an interface between the first dielectric shield and the epitaxial material.
  • the first medium is an oxide
  • the second medium is a nitride
  • the epitaxial material is Si
  • the third medium is SOG.
  • the thickness of the first medium is formed to be greater than 50 ⁇ ⁇ , and the thickness of the second medium is formed to be greater than 300 ⁇ .
  • DRAWINGS Figure i is an overall flow chart showing the formation process of a super PN junction in a real mode of the present invention.
  • 2 is an exploded perspective view showing a super PN junction forming process according to an embodiment of the present invention.
  • 3 is an exploded perspective view showing a super PN junction forming process according to an embodiment of the present invention.
  • 4 is an exploded perspective view showing a super PN junction forming process according to an embodiment of the present invention.
  • Fig. 5 is an exploded perspective view showing a super PN junction forming process according to an embodiment of the present invention.
  • the super PN junction forming method of the present invention mainly comprises: Step 1: a deposition step of depositing an epitaxial layer on a substrate;
  • Step 2 forming a dielectric formation step of the first dielectric layer and the second dielectric layer on the epitaxial layer;
  • Step 3 forming a deep trench formation step in the epitaxial layer
  • Step 4 filling the deep trench with an epitaxial material to fill the entire deep trench and exceeding a first filling step of the second dielectric layer;
  • Step 5 filling a third medium with a second filling step comprising forming the second interlayer layer and the entire surface of the epitaxial material to form a surface filling layer of a prescribed height;
  • Step 6 etching the surface-filled layer to an etching step at an interface between the first dielectric layer and the epitaxial material
  • Step 7 removing the first dielectric layer, the second dielectric layer, and the surface filling layer to achieve a planarization removal step of the epitaxial material.
  • FIGS. 2 to 5 are exploded perspective views showing a super PN junction forming process according to an embodiment of the present invention.
  • a method for forming a deep trench super PN junction Mainly have the following steps:
  • Step 1 depositing an epitaxial layer 100 on the substrate
  • Step 2 forming a first dielectric layer 200 and a second dielectric layer 300 sequentially on the epitaxial layer 100;
  • Step 3 forming a deep trench 400 in the epitaxial layer
  • Step 4 As shown in FIG. 2, the deep trench 400 is filled with an epitaxial material 500 to fill the entire deep trench 400 and exceed the second dielectric layer 200.
  • Step 5 As shown in FIG. 3, the third medium 600 is covered and filled with the entire surface including the second dielectric layer 200 and the epitaxial material 500 to form a surface filling layer of a predetermined height.
  • Step 6 as shown in FIG. 4, the surface-filled layer is etched back to the first dielectric layer
  • Step 7 removing the surface dielectric layer, that is, the first dielectric layer 100, the second dielectric layer 200, and the surface filling layer, to achieve planarization of the epitaxial material.
  • the method of filling the third dielectric material and etching back can effectively solve the technical problem of complicated process, difficult control, and high cost caused by planarization by CMP.
  • a fluid material is preferably used.
  • SOG can usually be used.
  • the flowing third medium 600 such as SOG is filled with the entire surface including the second dielectric layer 200 and the epitaxial material 500 in Fig. 2 to form a surface filling layer of a prescribed height.
  • the excipient device fills the entire surface by flowing the third medium 600 by spinning and coating.
  • the so-called “prescribed height” herein means at least higher than the highest point of the epitaxial material 500.
  • the etching selectivity ratio may be adjusted, for example, by engraving the epitaxial material 500 and the third medium 600.
  • the etch selectivity ratio is 1:1, whereby the epitaxial material 500 and the third dielectric 600 can be etched at the same rate, and both can be etched flat to planarize the epitaxial material.
  • the epitaxial material 500 Si is commonly used.
  • a wet method may be employed as a method of removing the first dielectric layer 100, the second dielectric layer 200, and the surface-filled layer.
  • the first dielectric layer 100 may preferably be an oxide
  • the second dielectric layer 200 is preferably a nitride.
  • the thickness of the first medium is formed to be greater than 500 A
  • the thickness of the second medium is formed to be greater than 300 ⁇ .
  • the epitaxial material (Si) is planarized by using a method compatible with the existing process, the process is simple, high in efficiency, and no special equipment (ie, CMP equipment) is required, thereby greatly reducing The process cost and the problem of unstable Si device parameters caused by CMP can be effectively avoided.

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Abstract

提供了一种深沟槽超级PN结的形成方法，包括：在衬底上沉积外延层（100）的沉积步骤；在外延层上依次形成第一介质层（200）、第二介质层（300）；在外延层中形成深沟槽（400）；对深沟槽填充外延材料（500）以充满整个深沟槽并且超过第二介质层；将流动性的第三介质（600）填满包含第二介质层和例如Si的外延材料的整个表面，形成规定高度的表面填充层；对表面填充层进行等离子回刻，直至第一介质层和外延材料的界面处；去除所述第一介质层、第二介质层和表面填充层以实现硅平坦化的去除步骤。利用本发明，能够使用与现有的工艺兼容的方法实现Si的平坦化，具有工艺简单、效率高、工艺成本低的优点，并能够有效避免利用CMP导致的Si器件参数不稳定的问题。

Description

一种深沟槽超级 PN结的形成方法 技术领域
本发明涉及半导体制造技术，尤其涉及一种深沟槽超级 PN结（ Super Junction ) 的制造技术。 背景技术
在半导体领域中， 用来提高功率 MOS 性能的超级 PN 结 （Super Junction )技术在高压领域的作用非常显著。
传统的超级 PN结的制造工艺中主要是采用深槽刻蚀、 外延填充、 硅 CMP平坦化的方法来实现。
具体地， 传统技术中形成超级 PN结的方法， 包括以下步骤： 步驟 1: 在 N+衬底硅片上沉积单一的厚外延层（N型）；
步骤 2: 在该外延层中形成深沟槽， 具体地， 先生长热氧化层， 然后 沉积氮化硅层，再沉积等离子体增强氧化层，通过刻蚀以上三层直至硅衬 底， 然后去胶， 并以所述三种膜作为硬掩模刻蚀成深沟槽， 然后湿法去除 氮化硅表面剩余的等离子体增强氧化层；
步骤 3: 在深沟槽中填充外延硅（P型）形成超级 PN结；
步骤 4: 通过 CMP法研磨到硅表面达到平坦化。
然而， 在所述利用 CMP的技术中， 因为一般生产线的 CMP设备都 用在后道， 与加工超级 PN结的设备不能混用， 因此， 利用 CMP平坦化 制造超级 PN结方法工艺必须采用专用 CMP设备而导致工艺控制难度大， 成本较高。 发明内容
本发明鉴于所述问题， 旨在提供一种能够与常规工艺兼容、且工艺简 单、 效率高的超级 PN结（ Super Junction ) 的形成方法。
本发明的深沟槽超级 PN结的形成方法， 其特征在于， 包括： 在衬底上沉积外延层的沉积步骤；
在所述外延层上依次形成第一介质层、 第二介质层的介质形成步骤； 在所述外延层形成深沟槽的深沟槽形成步骤； 对所述深沟槽填充外延材料以充满整个深沟槽并且超过第二介质层 的第一填充步骤；
将第三介质填满包含所述第二介质层和所述外延材料的整个表面，形 成规定高度的表面填充层的第二填充步骤；
对所述表面填充层进行回刻直至第一介质层和外延材料的界面处的 刻蚀步骤；
去除所述第一介质层、第二介盾层和表面填充层以实现外延材料的平 坦化的去除步骤。
优选地， 可以在所述刻蚀步骤中， 采用等离子刻蚀法。
优选地， 在所述第二填充步骤中， 使用辅料设备填充所述第三介质， 所述第三介质是流动性的介质。
利用所述发明， 替代现有技术中采用的 CMP, 而采用填充流动性介 质材料和等离子回刻， 因此， 能够有效解决利用 CMP进行平坦化所带来 的工艺复杂、 控制难度大， 成本高的技术问题。
优选地，所述等离子刻蚀法可以是通过调整刻蚀的选择比以使得对所 述外延材料和对所述第三介质的刻蚀速率为 1: 1。
优选地， 所述表面填充层的高度至少比所述外延材料的最高点高。 优选地， 在所述第二填充步骤中， 使用所述辅料设备通过旋转、 涂布 将流动性的第三介质填满所述第二介质层和外延材料的整个表面。
优选地， 在所述去除步骤中， 采用湿法去除各层。
优选地，在所述第一填充步骤中， 所述外延材料最低点超过所述第一 介盾与所述外延材料的界面。
优选地， 所述第一介质是氧化物， 所述第二介质是氮化物， 所述外延 材料是 Si, 所述第三介质是 SOG。
优选地， 所述第一介质的厚度形成为大于 50θΑ， 所述第二介质的厚 度形成为大于 300 A。
如上所述， 通过采用填充流动性介盾材料和等离子回刻， 能够使用与 现有的工艺兼容的方法实现硅的平坦化， 而无需专用的 CMP设备， 因此 具有工艺简单、效率高、工艺成本低的优点， 而且能够有效避免利用 CMP 导致的 Si器件参数不稳定的问题。 附图说明 图 i是表示本发明一实族方式的超级 PN结形成过程的整体流程图。 图 2是表示本发明一实施方式的超级 PN结形成过程的分解示意图。 图 3是表示本发明一实施方式的超级 PN结形成过程的分解示意图。 图 4是表示本发明一实施方式的超级 PN结形成过程的分解示意图。 图 5是表示本发明一实施方式的超级 PN结形成过程的分解示意图。 具体实施方式
下面介绍的是本发明的多个可能实施例中的一些， 旨在提供对本发明 的基本了解。并不旨在确认本发明的关键或决定性的要素或限定所要保护 的范围。
为使本发明的目的、技术方案和优点更加清楚， 下面结合附图对本发 明作进一步的详细描述。
以下， 参照图 1 ~图 5， 对本发明一实施方式的深沟槽超级 PN结的 图 1是表示本发明一实施方式的超级 PN结形成过程的整体流程图。 首先， 如图 1所示， 本发明的超级 PN结形成方法主要包括： 步骤 1: 在衬底上沉积外延层的沉积步骤；
步骤 2: 在所述外延层上依次形成第一介质层、 第二介质层的介质形 成步骤；
步骤 3: 在所述外延层形成深沟槽的深沟槽形成步骤；
步骤 4: 对所述深沟槽填充外延材料以充满整个深沟槽并且超过第二 介质层的第一填充步骤；
步骤 5: 将第三介质填满包含所述第二介盾层和所述外延材料的整个 表面， 形成规定高度的表面填充层的第二填充步骤；
步骤 6: 对所述表面填充层进行回刻直至第一介质层和外延材料的界 面处的刻蚀步骤；
步骤 7: 去除所述第一介质层、 第二介质层和表面填充层以实现外延 材料的平坦化的去除步骤。
图 2 ~ 5是表示本发明一实施方式的超级 PN结形成过程的分解示意 图。
下面对于上述步骤 1 ~ 7, 参照图 2 ~ 5进行具体说明。
如图 2 ~图 5所示， 本发明一实施方式的深槽超级 PN结的形成方法 主要具备下述步骤：
步骤 1 : 在衬底上沉积外延层 100;
步骤 2: 在所述外延层 100的上依次形成第一介质层 200、 第二介质 层 300的形成步骤；
步骤 3: 在所述外延层形成深沟槽 400;
步骤 4: 如图 2所示，对所述深沟槽 400填充外延材料 500以充满整 个深沟槽 400并且超过第二介质层 200。
步骤 5: 如图 3所示， 将第三介质 600覆盖、 填满包含所述第二介质 层 200和外延材料 500的整个表面， 形成规定高度的表面填充层。
步骤 6: 如图 4所示， 对所述表面填充层进行回刻， 直至第一介质层
200和外延材料 500的界面处。
步驟 7: 去除所述表面介质层即第一介质层 100、 第二介质层 200和 所述表面填充层， 实现外延材料的平坦化。
这样， 替代现有技术中采用的 CMP， 通过采用填充第三介质材料和 回刻的方法， 能够有效解决利用 CMP进行平坦化所带来的工艺复杂、 控 制难度大， 成本高的技术问题。
下面， 对于上述实施方式的几种变形例进行说明。
对于所述第三介质 600， 最好采用流动性的材料。 例如， 通常可以采 用 SOG。 这样， 在所述步骤 5中， 将流动的第三介质 600例如 SOG填充 图 2中的包含所述第二介质层 200和外延材料 500的整个表面， 形成规 定高度的表面填充层
在填充第三介质 600时， 可以采用常用的辅料设备。在使用辅料设备 填充流动的第三介质 600时，辅料设备通过旋转、涂布将流动的第三介质 600填满整个表面。
这里的所谓的 "规定高度" 是指至少比所述外延材料 500 的最高点 高。
在所述步骤 6中， 作为回刻的手段， 较佳地是采用等离子刻蚀法。 为 了实现对外延材料 500和第三介质 600两者的平整刻蚀，在等离子刻蚀方 法中， 可以通过调整刻蚀的选择比， 例如通过使得对外延材料 500和所 述第三介质 600的刻蚀选择比为 1 : 1 , 由此， 能够以相同的速率对外延 材料 500和第三介质 600进行刻蚀， 能够将两者刻蚀平整， 实现外延材 料的平坦化。 这里， 通常作为外延材料 500， 常用的是 Si。
进一步，在所述步骤 7中，作为去除第一介质层 100、第二介质层 200 和所述表面填充层的方法， 可以采用湿法。
另外， 所述第一介质层 100优选地可以是氧化物， 所述第二介质层 200优选地为氮化物。 所述第一介质的厚度形成为大于 500 A ， 所述第二 介质的厚度形成为大于 300 A。
综上所述， 利用本发明， 由于使用与现有的工艺兼容的方法实现外延 材料（Si ) 的平坦化， 工艺简单、 效率高、 无需专用的设备（即 CMP的 设备） ， 因此， 大大降低了工艺成本， 并能够有效避免利用 CMP导致的 Si器件参数不稳定的问题。
以上例子主要说明了本发明的超级 PN结的形成方法。 尽管只对其中 一些本发明的实施方式进行了描述， 但是本领域普通技术人员应当了解， 本发明可以在不偏离其主旨与范围内以许多其他的形式实施。 因此， 所展 示的例子与实施方式被视为示意性的而非限制性的，在不脱离如所附各权 利要求所定义的本发明精神及范围的情况下，本发明可能涵盖各种的修改
— v 'er "

Claims

1， 一种深沟槽超级 PN结的形成方法， 其特征在于， 包括： 在衬底上沉积外延层的沉积步骤；
在所述外延层上依次形成第一介盾层、 第二介质层的介质形成 步骤；
在所述外延层形成深沟槽的深沟槽形成步骤；
对所述深沟槽填充外延材料以充满整个深沟槽并且超过第二 介质层的第一填充步骤；
将第三介质填满包含所述第二介质层和所述外延材料的整个 表面， 形成规定高度的表面填充层的第二填充步骤；
对所述表面填充层进行回刻直至第一介质层和外延材料的界 面处的刻蚀步骤；
去除所述第一介盾层、 第二介质层和表面填充层以实现外延材 料的平坦化的去除步骤。
2. 如权利要求 1所述深沟槽超级 PN结的形成方法， 其特征在 于，
在所述刻蚀步骤中， 采用等离子刻蚀法。
3. 如权利要求 2所述深沟槽超级 PN结的形成方法， 其特征在 于，
所述等离子刻蚀法是通过调整刻蚀的选择比以使得对所述外 延材料和对所述第三介质的刻蚀速率为 1: 1。
4. 如权利要求 2所述深沟槽超级 PN结的形成方法， 其特征在 于，
在所述第二填充步骤中， 使用辅料设备填充所述第三介质， 所 述第三介质是流动性的介质。
5. 如权利要求 4所述深沟槽超级 PN结的形成方法， 其特征在 于，
所述表面填充层的高度至少比所述外延材料的最高点高。
6.如权利要求 4所述深沟槽超级 PN结的形成方法， 其特征在 于， 在所述第二填充步骤中， 使用所述辅料设备通过旋转、 涂布将 流动性的第三介盾填满所述第二介盾层和外延材料的整个表面。
7. 如权利要求 4所述深沟槽超级 PN结的形成方法， 其特征在 于，
在所述去除步骤中， 釆用湿法去除各层。
8. 如权利要求 4所述深沟槽超级 PN结的形成方法， 其特征在 于，
在所述第一填充步骤中， 所述外延材料最低点超过所述第一介 质与所述外延材料的界面。
9. 如权利要求 1 ~ 8任意一项所述的深沟槽超级 PN结的形成 方法， 其特征在于，
所述第一介质是氧化物， 所述第二介质是氮化物， 所述外延材 料是 Si, 所述第三介质是 SOG。
10.如权利要求 9所述深沟槽超级 PN结的形成方法， 其特征 在于，
所述第一介质的厚度形成为大于 500A,所述第二介质的厚度形 成为大于 300 A。
PCT/CN2012/076353 2011-06-08 2012-05-31 一种深沟槽超级pn结的形成方法 WO2012167715A1 (zh)

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