JP7407583B2 - 自己整合マルチパターニングにおいてスペーサプロファイルを再整形する方法 - Google Patents
自己整合マルチパターニングにおいてスペーサプロファイルを再整形する方法 Download PDFInfo
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- 125000006850 spacer group Chemical group 0.000 title claims description 298
- 238000000059 patterning Methods 0.000 title claims description 11
- 239000000463 material Substances 0.000 claims description 229
- 238000000034 method Methods 0.000 claims description 168
- 238000005240 physical vapour deposition Methods 0.000 claims description 50
- 238000005137 deposition process Methods 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 42
- 238000000151 deposition Methods 0.000 claims description 30
- 238000004377 microelectronic Methods 0.000 claims description 12
- 238000000231 atomic layer deposition Methods 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000011282 treatment Methods 0.000 claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 5
- 239000013077 target material Substances 0.000 claims description 5
- 239000011162 core material Substances 0.000 description 78
- 230000015556 catabolic process Effects 0.000 description 22
- 238000006731 degradation reaction Methods 0.000 description 22
- 239000004065 semiconductor Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000002245 particle Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000004215 Carbon black (E152) Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 238000001900 extreme ultraviolet lithography Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- -1 nitrogen-containing hydrocarbon Chemical class 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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Description
本出願は、参照のためその内容を本明細書に援用する2018年12月12日出願の米国仮特許出願第62/778,794号明細書:題名“METHODS TO RESHAPE SPACER PROFILES IN SELF-ALIGNED MULTIPLE PATTERNING”と、2019年3月12日出願の米国特許出願第16/299,623号明細書:題名“METHODS TO RESHAPE SPACER PROFILES IN SELF-ALIGNED MULTIPLE PATTERNING”からの優先権を主張する。
102 基板
104 スペーサ
106、346 コア位置
108、348 スペース位置
110 破線
112 粒子
202 コア
204 スペーサ材料層
300、310、315、320、330、340、400、410、420、430、500、510、520 例示的実施形態
312、317 矢印
314、316、422 追加スペーサ材料
324 対称スペーサ
502、504、506、512、514、522、524、526 ブロック
Claims (22)
- スペーサプロファイルを再整形する方法であって、
マイクロエレクトロニクス・ワークピースの基板の材料層上にコアを形成する工程と;
前記コアを覆ってスペーサ材料層を形成する工程と;
1つ又は複数の指向性堆積処理を使用して追加スペーサ材料を堆積させ、そして、1つ又は複数のエッチ処理工程を使用することで、前記スペーサ材料層を再整形することにより、前記コアに隣接して、各々が対称な上部を持つ対称スペーサを形成する工程と、を含み、
前記1つ又は複数の指向性堆積処理は1つ又は複数の斜め物理気相成長(PVD)処理を含む、
方法。 - 前記対称スペーサは自己整合マルチパターニング(SAMP)プロセスの一部として形成される、請求項1に記載の方法。
- 前記対称スペーサは、
前記1つ又は複数の指向性堆積処理により、前記スペーサ材料層が前記コアの角を覆う前記スペーサ材料層の角へ追加スペーサ材料を堆積させ、そして、
前記1つ又は複数のエッチ処理により、前記コアに隣接する対称スペーサを残すように前記スペーサ材料層及び前記追加スペーサ材料をエッチングする、
ことにより形成される、請求項1に記載の方法。 - 前記スペーサ材料層の角は丸角である、請求項3に記載の方法。
- 前記対称スペーサは、
前記スペーサ材料層をエッチングして、前記コアに隣接する非対称スペーサを形成し、
前記1つ又は複数の指向性堆積処理により、前記非対称スペーサの角へ追加スペーサ材料を堆積させ、そして、
前記1つ又は複数のエッチ処理により、前記コアに隣接する対称スペーサを残すように前記追加スペーサ材料をエッチングする、
ことにより形成される、請求項1に記載の方法。 - 前記非対称スペーサの前記角は丸角を有する、請求項5に記載の方法。
- 前記対称スペーサを形成するために平坦化処理を少なくとも部分的に使用する工程をさらに含む、請求項1に記載の方法。
- 前記スペーサ材料層及び前記追加スペーサ材料は共通の材料である、請求項1に記載の方法。
- 前記スペーサ材料層と前記追加スペーサ材料は異なる材料である、請求項1に記載の方法。
- 前記1つ又は複数の斜めPVD処理は30~60度の角度で前記追加スペーサ材料を付与する、請求項1に記載の方法。
- 前記1つ又は複数の斜めPVD処理は45度の角度で前記追加スペーサ材料を付与する、請求項1に記載の方法。
- 前記1つ又は複数の斜めPVD処理は追加スペーサ材料を2つの異なる方向に同時に堆積させるために使用される、請求項1に記載の方法。
- 第1組の1つ又は複数の斜めPVD処理が追加スペーサ材料を第1の方向に堆積させるために使用され、第2組の1つ又は複数の斜めPVD処理が追加スペーサ材料を第2の方向に堆積させるために使用される、請求項1に記載の方法。
- 前記第1組からの斜めPVD処理が前記第2組からの斜めPVD処理と交互に行われる、請求項13に記載の方法。
- 同じ処理ケミストリ又は異なる処理ケミストリを有する複数の斜め物理気相成長(PVD)処理が使用される、請求項1に記載の方法。
- 同じターゲット材料又は異なるターゲット材料を有する複数の斜め物理気相成長(PVD)処理が使用される、請求項1に記載の方法。
- 前記対称スペーサを残すように前記コアを除去する工程をさらに含む請求項1に記載の方法。
- 前記対称スペーサのパターンを前記基板の前記材料層へ転写する工程をさらに含む請求項17に記載の方法。
- エッチング均一性の目標レベルが前記パターンの前記転写において達成される、請求項18に記載の方法。
- 前記スペーサ材料層は酸化物又は窒化物のうちの少なくとも1つを含み、前記追加スペーサ材料は酸化物又は窒化物のうちの少なくとも1つを含む、請求項1に記載の方法。
- 前記コアは有機平坦化層又は非晶質シリコン層のうちの少なくとも1つから形成される、請求項1に記載の方法。
- 前記スペーサ材料層は原子層成長法を使用して形成される、請求項1に記載の方法。
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