CN102473706A - 肖特基二极管开关和包含它的存储部件 - Google Patents
肖特基二极管开关和包含它的存储部件 Download PDFInfo
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- CN102473706A CN102473706A CN2010800324119A CN201080032411A CN102473706A CN 102473706 A CN102473706 A CN 102473706A CN 2010800324119 A CN2010800324119 A CN 2010800324119A CN 201080032411 A CN201080032411 A CN 201080032411A CN 102473706 A CN102473706 A CN 102473706A
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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Abstract
一种开关元件,包括:第一半导体层,该第一半导体层具有第一部分和第二部分;第二半导体层,该第二半导体层具有第一部分和第二部分;置于第一半导体层和第二半导体层之间的绝缘层;第一金属接触件,该第一金属接触件与第一半导体层的第一部分接触形成第一结并且与第二半导体层的第一部分接触形成第二结;第二金属接触件,该第二金属接触件与第一半导体层的第二部分接触形成第三结并且与第二半导体层的第二部分接触形成第四结,其中第一结和第四结是肖特基接触,第二结和第三结是欧姆接触。
Description
背景技术
新型存储器已展现出与常用类型的存储器相媲美的显著可能性。例如,非易失性自旋转移扭矩随机存取存储器(在本文中称为“STRAM”)和阻性随机存取存储器(在本文中称为“RRAM”)均被认为是下一代存储器的良好候选。可通过增加可在芯片上形成的存储部件(存储器单元及其相关联的驱动器件)的密度来最大化与已知的存储器类型(诸如FLASH存储器(NAND或NOR))相比而言更有效竞争的STRAM和RRAM的能力。
发明内容
本文公开的是一种开关元件,包括:第一半导体层,该第一半导体层具有第一部分和第二部分;第二半导体层,该第二半导体层具有第一部分和第二部分;置于第一半导体层和第二半导体层之间的绝缘层;第一金属接触件,该第一金属接触件与第一半导体层的第一部分接触形成第一结并且与第二半导体层的第一部分接触形成第二结;第二金属接触件,该第二金属接触件与第一半导体层的第二部分接触形成第三结并且与第二半导体层的第二部分接触形成第四结,其中第一结和第四结是肖特基接触,第二结和第三结是欧姆接触。
本文还公开的是一种非易失性存储器元件,包括:开关器件,该开关器件具有:第一半导体层,该第一半导体层具有第一部分和第二部分;第二半导体层,该第二半导体层具有第一部分和第二部分;置于第一半导体层和第二半导体层之间的绝缘层;第一金属接触件,该第一金属接触件与第一半导体层的第一部分接触形成第一结并且与第二半导体层的第一部分接触形成第二结;第二金属接触件,该第二金属接触件与第一半导体层的第二部分接触形成第三结并且与第二半导体层的第二部分接触形成第四结,其中第一结和第四结是肖特基接触,且第二结和第三结是欧姆接触;以及非易失性存储器单元,其中开关器件与非易失性存储器单元串联电连接。
本文中还公开的是形成开关元件的方法,包括以下步骤:提供分层制品,该分层制品包括第一半导体层、绝缘层和第二半导体层;形成第一掩摸区,其中第一掩摸区仅保护该分层制品的第一部分;利用第一能级仅掺杂第二半导体层的第一部分;形成第二掩摸区,其中该第二掩摸区仅保护分层制品的第二部分,其中该分层制品的第一部分和第二部分仅部分重叠;利用第二能级仅掺杂第一半导体层的第二部分,其中第一能级和第二能级是不同的,由此形成经掺杂的分层制品;仅在经掺杂的分层制品的一部分上形成接触件掩摸;蚀刻至少第二半导体层、绝缘层和第一半导体层的一部分;在第二半导体层、绝缘层和第一半导体层的蚀刻区域中形成第一和第二金属接触件。
通过阅读以下详细描述,这些以及各个其他特征和优点将是显而易见的。
附图简述
考虑以下结合附图对本公开的各个实施例的详细描述,可更完整地理解本公开,在附图中:
图1A是本文中所公开的开关元件的实施例的示意图;
图1B是描绘本文中所公开的开关元件的功能的电路图;
图1C是本文中所公开的假设开关元件的电流-电压(I-V)曲线;
图2A和2B是本文中所公开的开关元件的示意图;
图3是描绘形成开关元件的示例性方法的流程图;
图4A至4G描绘在各制造阶段上的开关元件;
图5A至5C是可在本文中所公开的非易失性存储器元件中使用的各种类型的阻性感测存储器(RSM)单元(图5A和5B描绘STRAM;而图5C描绘RRAM)的示意图;
图6A是本文中所公开的非易失性存储器元件的示意图;
图6B是本文中所公开的非易失性存储器元件的电路图;
图7A至7C是可包含本文中所公开的非易失性存储部件的交叉存储器阵列的多个部分的立体图(图7A和7B)和简图(图7C)。
这些附图不一定按比例示出。附图中所使用的相同数字表示相同组件。然而,应当理解,在给定附图中使用数字表示组件并不旨在限制在另一附图中用相同数字标记的组件。
详细描述
在以下描述中,参考形成本说明书一部分的一组附图,其中通过解说示出了若干具体实施例。应当理解,可构想并可作出其他实施例而不背离本公开的范围或精神。因此,以下详细描述不具有限制性含义。
除非另外指示,否则在说明书和权利要求书中使用的表示特征大小、数量和物理性质的所有数字应当理解为在任何情况下均由术语“大约”所修饰。因此,除非相反地指出,否则在上述说明书和所附权利要求中阐述的数值参数是近似值,这些近似值可利用本文中公开的教示根据本领域技术人员所寻求获得的期望性质而变化。
借由端点对数值范围的陈述包括归入该范围内的所有数字(例如,1至5包括1、1.5、2、2.75、3、3.80、4和5)以及该范围内的任何范围。
如本说明书和所附权利要求书中所使用的,单数形式“一”、“一个”和“该”涵盖具有复数引用对象的实施例,除非该内容另外明确地指出。如本说明书和所附权利要求书中所使用的,术语“或”一般以包括“和/或”的含义来使用,除非该内容另外明确地指出。
空间相关的术语,包括但不限于“较低”、“较高”、“之下”、“下面”“之上”和“在顶端”,如果在本文中使用,则用于便于说明以描述一个元件与另一元件的空间关系。除附图中所示的和本文中所描述的特定方向之外,这些空间相关的术语还涵盖在使用或操作中的器件的诸个不同方向。例如,如果在图中所描述的单元被调转或翻转,先前描述的在其他元件之下或下面的部分而后将会在此类其他元件的上方。
如本文中所使用的,例如当元件、组件或层被描述为“在其上”、“连接至”、“耦合”或“接触”另一元件、部件或层时,其可直接在其上、直接连接到、直接耦合、直接接触,或者居间元件、部件或层可在其上、连接、耦合或接触特定元件、组件或层。例如当元件、组件或层被称为开始“直接在其上”、“直接连接到”、“直接耦合”、或“直接接触”另一元件时,则不存在居间元件、组件或层。
本文中所公开的是可用作开关的电子器件。所公开的电子器件还可称为开关器件或开关元件。一般而言,开关是能够切断电路、断开电流或使电流从一个导体转向另一个的电组件。本文中所公开的开关还可称为双向开关。双向开关可切断电路并且还可引导电流通过开关的任一路。开关器件可在先前使用的或已经使用二极管的应用中以及其它应用中使用。本文中所公开的开关器件还可承受高驱动电流。
如本文中所公开的开关器件的实施例可从图1A中看出。示例性开关器件包括第一半导体层130、绝缘层140、第二半导体层150、第一金属接触件160和第二金属接触件170。如图1A所见,绝缘层140(在实施例中也可称为第一绝缘层140)可定位在第一半导体层130和第二半导体层150之间。在诸个实施例中,绝缘层140可直接定位在第一半导体层130和第二半导体层150之间并且与第一半导体层130和第二半导体层150两者接触。
在诸个实施例中,第一金属接触件160与第一半导体层130、绝缘层140和第二半导体层150相邻。在诸个实施例中,第一金属接触件160与第一半导体层130、绝缘层140和第二半导体层150各自的第一部分131、141和151相邻。在诸个实施例中,第一金属接触件160与第一半导体层130、绝缘层140和第二半导体层150的第一部分131、141和151接触。在诸个实施例中,第一金属接触件160与第一半导体层130、绝缘层140和第二半导体层150的第一部分131、141和151直接接触。
在诸个实施例中,第二金属接触件170与第一半导体层130、绝缘层140和第二半导体层150相邻。在诸个实施例中,第二金属接触件170与第一半导体层130、绝缘层140和第二半导体层150各自的第二部分133、143和153相邻。在诸个实施例中,第二金属接触件170与第一半导体层130、绝缘层140和第二半导体层150的第二部分133、143和153接触。在诸个实施例中,第二金属接触件170与第一半导体层130、绝缘层140和第二半导体层150的第二部分133、143和153直接接触。
第一半导体层130的第一部分131在第一结162处接触第一金属接触件160;第二半导体层150的第一部分151在第二结164处接触第一金属接触件160;第一半导体层130的第二部分133在第三结172处接触第二金属接触件170;并且第二半导体层150的第二部分153在第四结174处接触第二金属接触件170。第一、第二、第三和第四结162、164、172和174是欧姆结或者是肖特基结。
每当金属和半导体紧密接触时,在两种材料之间存在防止大多数载流子(电子或空穴)从一种材料穿入另一材料的电势垒。仅仅少量载流子具有足够的能量越过势垒进入另一材料。当偏压施加到该结时,它具有两种效应之一:其可使得势垒表现为自半导体侧较低,或者其可使得势垒表现为自半导体侧较高。该偏压不会改变自金属侧的势垒高度。这样的结果是肖特基势垒,也称为肖特基结或整流接触,其中该结对于一种偏置极性呈导通而对另一种偏置极性不导通。另一方面,欧姆接触对于两种极性导电性相同。欧姆接触或欧姆结具有线性且对称的电流-电压(I-V)曲线;肖特基接触或肖特基结具有非线性且不对称的电流-电压(I-V)曲线。
特定金属-半导体结是欧姆结还是肖特基结可至少部分地取决于金属的功率函数、半导体的带隙、半导体中掺杂物的类型和浓度、以及其它因素。一般而言,重掺杂半导体和金属的结形成较薄的能量势垒(掺杂物水平越重、势垒越薄)。在反向偏置的情况下,由于量子力学隧道效应,电荷将流过势垒。在诸个实施例中,重掺杂半导体材料和金属的结将形成欧姆接触(电流将沿任一方向流过:在一个方向上的正向偏置电流,在另一(反向)方向上的隧穿),而未掺杂或轻掺杂半导体材料和金属的结将形成肖特基结。
在本文中所公开的开关元件的诸个实施例中,第一半导体层130将具有一个欧姆接触和一个肖特基接触,而第二半导体层150将具有一个欧姆接触和一个肖特基接触。第一半导体层130内的肖特基接触和欧姆接触的取向一般与第二半导体层150内的肖特基接触和欧姆接触的取向相反。在诸个实施例中,第一结162可以是肖特基结,第二结164可以是欧姆结,第三结172可以是欧姆结,且第四结174可以是肖特基结。在诸个实施例中,第一结162可以是欧姆结,第二结164可以是肖特基结,第三结172可以是肖特基结,且第四结174可以是欧姆结。
第一和第二半导体层130和150内的肖特基接触和欧姆接触的相反取向使开关元件具有这样的双向开关构造。当施加具有第一极性的电流时双向开关允许电流沿第一方向流动,而当施加具有第二极性(与第一极性相反)的电流时双向开关允许电流沿第二方向(与第一方向相反)流动。图1B描绘示出本文中所公开的开关元件的双向特性的电路图。如图1B的电路图所见,第一半导体层和第二半导体层分别提供并联的第一二极管180和第二二极管185的功能。第一二极管180允许电流沿与第二二极管185所允许的相反的方向流动。图1C示出了假设公开的开关元件的电流-电压(I-V)曲线。如图1C所见,第一二极管180具有阈值电压VT1,在该阈值电压VT1下大量电流开始沿第一方向流动;第二二极管185具有阈值电压VT2,在该阈值电压VT2下大量电流开始沿第二方向流动。如图1C所示,VT1和VT2的极性是相反的,在这两个电压下从开关元件流动的电流也是如此。这提供了基本上阻断电压VT1和VT2之间的电流且允许具有第一极性的电流在低于VT2的电压下流动且具有第二极性的电流在高于VT1的电压下流动的开关元件。
在用作开关时,这表示如果小于VT2的电压被施加到开关元件,则电流将沿第一方向流动;而如果大于VT1的电压被施加到开关元件,则电流将沿第二方向流动。该开关元件因此可被用于控制电流流过诸如非易失性存储器单元之类的电连接组件的方向。
本文中所公开的开关元件可有利地提供双向开关和承受高驱动电流能力的组合。本文中所公开的开关元件可在高驱动电流是必要的情况(因为所公开的开关元件的电流路径的(与常规MOS晶体管相比)相对较大的横截面(这使得它能够流送相对大量的电流))下使用。处理高驱动电流的能力是有利的,因为该开关因此可被用于必需或期望高驱动电流的组件,其示例是自旋转移扭矩随机存取存储器(STRAM)。
图2A示出本文中所公开的开关元件的另一实施例。图2A中的开关元件包括以上讨论的组件且还包括其它组件。例如,与第一半导体层230相邻的可以是另一绝缘层220,还可将其称为第二绝缘层220。在诸个实施例中,第二绝缘层220可与第一半导体层230直接相邻。第二绝缘层220可用于将第一半导体层230与衬底210电绝缘。衬底可以是导电材料或半导体材料。衬底210可用于向开关元件提供结构稳定性,且可有助于开关元件的形成过程。
在图1C中示出的假设I-V曲线是对称的。一般而言,为了使所公开的开关元件的I-V曲线是对称的,跨越第一半导体层和第二半导体层的路径长度必须至少基本上相同,且金属/半导体结(例如,162、164、172和174)的表面积必须至少基本上相同。不具有对称的第一和第二半导体层和/或基本相同的表面积的开关元件可被修改以变得不对称性较小。这可例如通过修改构成开关元件的组件、通过改变掺杂物(特性或量)、通过改变金属接触件之一或两者、通过改变本文中未讨论的其它因素或通过改变这些因素的组合来实现。在一些应用中,具有对称I-V曲线的开关元件可能是有利的。例如,对于将与存储器元件结合使用的开关元件,具有对称I-V曲线是有利的。
图2A中示出的示例性开关元件可相对容易地被制造成具有对称I-V曲线,因为使第一和第二半导体层的厚度基本相同是通常而言较为简单的。在诸个实施例中,具有基本相同厚度的第一半导体层和第二半导体层的开关元件很可能具有对称I-V曲线。
图2B中示出的示例性开关元件很可能不具有对称I-V曲线。如图2B所见,所示的开关元件具有第一半导体层230,该第一半导体层230显著厚于第二半导体层250;以及第一结262和第三结274,第一半导体层230的第一结262和第三结274的表面积显著大于第二半导体层250的结(即,与第一金属接触件260和第二金属接触件270的第二结264和第四结272)。这很可能导致第一半导体层230具有高于第二半导体层250的阈值电压。这种开关元件因此很可能具有不对称I-V曲线。
第一半导体层和第二半导体层可包括任何半导体材料。第一半导体层和第二半导体层可以是但不必须是相同的材料。可用于第一半导体层、第二半导体层或两者的示例性半导体包括但不限于:硅、含硅化合物、锗、含锗化合物、含铝化合物、含硼化合物、含镓化合物、含铟化合物、含镉化合物、含锌化合物、含铅化合物、含锡化合物。示例性元素和化合物半导体包括但不限于:硅(例如结晶硅)、锗、碳化硅(SiC)、硅锗(SiGe)、锑化铝(AlSb)、砷化铝(AlAs)、氮化铝(AlN)、磷化铝(AlP)、淡化硼(BN)、磷化硼(BP)、砷化(BAs)、锑化镓(GaSb)、砷化镓(GaAs)、氮化镓(GaN)、磷化镓(GaP)、锑化铟(InSb)、砷化铟(InAs)、氮化铟(InN)、磷化铟(InP)、砷化铝镓(AlGaAs、AlxGal-xAs)、砷化铟镓(InGaAs、InxGal-xAs)、磷化铟镓(InGaP)、砷化铝铟(AlInAs)、锑化铝铟(AlInSb)、砷化氮化镓(GaAsN)、砷化磷化镓(GaAsP)、氮化铝镓(AlGaN)、磷化铝镓(AlGaP)、氮化铟镓(InGaN)、砷化锑化铟(InAsSb)、锑化铟镓(InGaSb)、磷化铝镓铟(AlGaInP、也为InAlGaP、InGaAlP、AlInGaP)、砷化磷化铝镓(AlGaAsP)、砷化磷化铟镓(InGaAsP)、砷化磷化铝铟(AlInAsP)、砷化氮化铝镓(AlGaAsN)、砷化氮化铟镓(InGaAsN)、砷化氮化铟铝(InAlAsN)、砷化锑化氮化镓(GaAsSbN)、氮化砷化锑化镓铟(GaInNAsSb)、砷化锑化磷化镓铟(GaInAsSbP)、硒化镉(CdSe)、硫化镉(CdS)、碲化镉(CdTe)、氧化锌(ZnO)、硒化锌(ZnSe)、硫化锌(ZnS)、碲化锌(ZnTe)、碲化镉锌(CdZnTe、CZT)、碲化汞镉(HgCdTe)、碲化汞锌(HgZnTe)、硒化汞锌(HgZnSe)、氯化亚铜(CuCl)、硒化铅(PbSe)、硫化铅(PbS)、碲化铅(PbTe)、硫化锡(SnS)、碲化锡(SnTe)、碲化铅锡(PbSnTe)、碲化铊锡(Tl2SnTe5)、碲化铊锗(Tl2GeTe5)、碲化铋(Bi2Te3)、磷化镉(Cd3P2)、砷化镉(Cd3As2)、镉锑化(Cd3Sb2)、磷化锌(Zn3P2)、砷化锌(Zn3As2)以及锑化锌(Zn3Sb2)。
第一半导体层和第二半导体层两者的一部分是掺杂的。掺杂是将杂质有意地引入半导体以改变其电学性质的过程。所选的特定掺杂物可至少部分地取决于最终开关元件中期望的特定性质、要掺杂的半导体材料的特性、本文中未讨论的其它因素、或以上的组合。示例性掺杂物可包括但不限于族III和族V元素。在半导体材料是族IV材料(例如,硅、锗以及碳化硅)的诸个实施例中,族III或族V元素可用作掺杂物。具体的示例性掺杂物可包括但不限于:硼(B)、砷(As)、磷(P)和镓(Ga)。
第一绝缘层以及可选的第二绝缘层可由电绝缘的任意材料来形成。第一绝缘层以及可选的第二绝缘层可以是但不必须是相同的材料。示例性绝缘层材料包括但不限于氧化物,诸如氧化铝(Al2O3)、氧化硅(SiO2)和氧化镁(MgO)。
金属接触件可以由任何导电金属材料制成。第一金属接触件和第二金属接触件可以是但不必须是相同的材料。示例性金属导电材料包括但不限于:钨(W)或贵金属,诸如金(Au)、铂(Pt)、钯(Pd)、铹(Rh)、铜(Cu)、镍(Ni)、银(Ag)、钴(Co)、铁(Fe)或它们的硅化物。
在诸个实施例中,第一和第二半导体层均由结晶硅所制成。在诸个实施例中,用硼、磷或砷来掺杂第一和第二半导体层。在诸个实施例中,第一绝缘层和第二绝缘层(如果存在的话)则由氧化硅(SiO2)来制成。在诸个实施例中,金属接触件为钨(W)、硅化镍或硅化钴。
诸如图2A所描绘的开关元件的示例性制造方法在图3中提供,并在图4A至4G中按步骤示出。一般而言,这种制造方案可包括诸种半导体制造方法,包括光刻技术和诸如蚀刻和化学机械平坦化(CMP)之类的其它去除技术。包括但不限于等离子体气相沉积(PVD)、基于离子化等离子体的溅射、长抛溅射、化学气相沉积(CVD)、原子层沉积(ALD)、以及金属有机化学气相沉积(MOCVD)的沉积方法可被用于沉积在示例性方法中所沉积的各层。图3描绘的步骤以及其在图4A至4G中的图示决不限制制造本文中所公开的开关元件的方式。还应该注意到,图4A至4G不一定按比例绘制,也没有必要绘制出每个制备状态下的制品,即,制品的一些中间阶段可能并未在该一系列附图中示出。参照附图4A至4G所述的材料和工艺也绝非限制可在此处使用的材料和工艺。
图3和图4A至4G中示出的示例性方法描绘衬底的使用。本领域的技术人员在阅读本说明书后将理解到,衬底的使用不是必须的,本文中所公开的开关元件可在不使用衬底的情况下被制造,开关元件在制造后可被置于支承上,衬底可被使用并且随后在开关制造期间或之后被去除,或者根本不需要使用衬底。该衬底(如果被使用)可包括诸如硅、硅和锗的混合物以及其他类似的材料之类的材料。
在图3中示出描绘制造本文中所公开的开关元件的示例性方法的流程图。示例性方法中的第一步是步骤310,提供分层制品。分层制品至少包括第一半导体层、绝缘层(也可称为第一绝缘层)和第二半导体层,且使绝缘层定位在第一半导体层和第二半导体层之间。示例性分层制品402可见于图4B,且包括衬底410、第二绝缘层420、第一半导体层430、第一绝缘层440和第二半导体层450。在阅读本说明书后应理解,分层制品可具有比图4B所示更多或更少的层。可例如通过商业上可获得的资源来制造或获取分层制品。
可用于制造分层制品的示例性任选步骤见于步骤302、304和306。步骤302包括提供第一分层结构。第一分层结构可至少包括第一衬底、第二绝缘层和第一半导体层,且使第二绝缘层定位在第一衬底和第一半导体层之间。第一分层结构的示例可包括衬底(例如,硅晶片),具有置于其上的绝缘层以及置于绝缘层上的第一半导体层。可通过沉积绝缘材料或通过氧化一部分衬底以由一部分衬底形成绝缘材料(例如,SiO2)来形成第一分层结构的绝缘层(第二绝缘层)。示例性第一分层结构405在图4A中示出且包括衬底410、第二绝缘层420和第一半导体层430。
步骤304包括提供第二分层结构。第二分层结构可至少包括绝缘层(可称为第一绝缘层)和第二半导体层,且使绝缘层置于第二半导体层上(或反之亦然)。第二分层结构的示例可包括被氧化的衬底(例如,硅晶片),其中被氧化的部分成为绝缘层且未被氧化的部分成为第二半导体层。或者,半导体材料(诸如硅晶片)可具有置于其上的绝缘材料以在第二半导体层上形成绝缘层。在诸如硅晶片之类的衬底被用于形成第二分层结构的实施例中,可去除硅晶片的一部分以调节第二半导体层的厚度。这可利用诸如化学机械平坦化(CMP)之类的技术来完成。示例性第二分层结构407在图4A中示出且包括绝缘层440和第二半导体层450。
步骤306包括使第一分层结构与第二分层结构接触(或者反之亦然)。第一和第二分层结构被配置成使得第二分层结构的绝缘层与第一分层结构的第一半导体层相邻以形成分层制品。在诸个实施例中,第一分层结构的第一半导体层与第二分层结构的绝缘层直接相邻或直接接触。然后可利用晶片接合技术将第一和第二分层结构接合在一起。完成该步骤就形成了图4B所见的分层制品402。
尽管提供了分层制品(不管经由步骤302、304和306还是以其它方式),形成开关元件的方法中的下一步骤是步骤320,掺杂分层制品。掺杂分层制品的步骤用于掺杂第一半导体层的一部分和第二半导体层的一部分。更具体地,掺杂分层制品的步骤用于掺杂第二半导体层的第一部分和第一半导体层的第二部分(或者反之亦然)。掺杂分层制品所采取的示例性任选步骤在步骤322、324、326和328中示出。
步骤322包括形成第一掩模区。掩模区(以下将讨论的第一掩模区和第二掩模区)由防止掺杂物注入到位于其下材料的材料所制成(在该上下文中,上和下由掺杂物源的位置来定义,且掺杂物源位于分层制品的所有层和掩模区之上)。可用作掩模区的示例性材料包括但不限于:氧化物材料、氮化硅或光阻。第一掩模区仅保护一部分分层制品免受注入影响。图4C所描绘的制品包括第一掩模区411。
下一步骤(步骤324)包括掺杂分层制品的一部分。第一掩模区(在步骤322中形成)允许仅掺杂分层制品的一部分,例如第一部分。如图4C所见,在第一掩模区下防止注入(由箭头所描绘),而在第一掩模区未覆盖分层制品的区域允许注入(由箭头所描绘)。利用第一能级完成对分层制品的第一部分的掺杂。在诸个实施例中,掺杂第一部分导致第二半导体层450为重掺杂且第一半导体层430仅为轻掺杂或基本完全未掺杂。可通过使用不同的能级来实现有差别的掺杂水平(或掺杂和基本未掺杂)。
如本文所描绘的步骤324实现第二半导体层450(在本实施例中描绘为分层制品的上层)的优先掺杂。可通过使用较低注入能量的掺杂来实现仅对分层结构中一个或多个上层的优先掺杂。使用较低能量的掺杂可给予掺杂物仅够穿透某一深度的能量。图4D描绘在步骤324完成之后第二半导体层450中存在的掺杂物451。
步骤326包括形成第二掩模区。第二掩模区仅保护一部分分层制品免受注入影响。图4D所描绘的制品包括第二掩模区413。第一掩模区411和第二掩模区413的位置可至少部分重叠。在诸个实施例中,第一掩模区411和第二压模区413不完全重叠且仅部分重叠。第二掩模区413一般至少保护第二半导体层450的在步骤324中被掺杂的那个部分。在诸个实施例中,第二掩模区413一般保护第二半导体层450的在步骤324中被掺杂的那个部分以及第二半导体层450的在步骤324中未掺杂的一部分。
下一步骤(步骤328)包括掺杂分层制品的一部分。第二掩模区(在步骤326中形成)允许仅掺杂分层制品的一部分,例如第二部分。如图4D所见,在第二掩模区下防止注入(由箭头所描绘),而在第二掩模区未覆盖分层制品的区域允许注入(由箭头所描绘)。利用第二能级完成对分层制品的第二部分的掺杂。第二能级不同于(用于掺杂第一部分的)第一能级。在诸个实施例中,掺杂第二部分导致第一半导体层430为重掺杂且第二半导体层450仅为轻掺杂或基本完全未掺杂。利用较高能量的掺杂使掺杂物更深地注入到分层制品。较高能级的掺杂一般也不会使掺杂物沉积或至少不会使大量掺杂物沉积在分层制品的上层。图4E描绘在步骤328完成之后第一半导体层430中存在的掺杂物431。
步骤320或任选的步骤322、324、326和328的效果是掺杂或重掺杂仅仅第二半导体层450的第一部分且掺杂或重掺杂仅仅第一半导体层430的第二部分。第一和第二半导体层430和450中的掺杂或重掺杂区域的这种相反构造形成在第一和第二半导体层430和450中相反对齐的欧姆和肖特基结(在金属接触件形成之后)。步骤320的效果是形成本文中称为经掺杂的分层制品(图4中所见)并指示为409。
在图3中描绘的方法中的下一步骤是步骤330,形成金属接触件。一般而言,可利用蚀刻和沉积技术来完成金属接触件的形成。形成金属接触件所采取的示例性具体任选步骤在步骤332、334和336中示出。在该形成金属接触件的任选方法中的第一步骤是步骤332,形成接触件掩模。在图4F中描绘的接触件掩模452一般仅掩盖经掺杂的分层制品的一部分。在诸个实施例中,接触件掩模452掩盖经掺杂的分层制品中第一半导体层450或第二半导体层430任一个中未掺杂的区域。还可以说,接触件掩模452至少掩盖经掺杂的分层制品中第一掩模区411和第二掩模区413提供保护免受掺杂的部分。一般而言,接触件掩模位于经掺杂的分层制品的中间。在诸个实施例中,接触件掩模452被定位成使得当经掺杂的分层结构一旦被蚀刻,经掺杂的第一半导体层和经掺杂的第二半导体层的至少一部分就将保留。
下一步骤(步骤334)包括利用接触件掩模452来蚀刻经掺杂的分层制品。该步骤用于去除经掺杂的分层制品的一个或多个部分。从经掺杂的分层制品去除未受接触掩模452保护的部分。蚀刻可被认为是形成第一和第二金属接触件区461和471。第一和第二金属接触件区461和471最终将以金属来填充以形成金属接触件。可使用已知的蚀刻技术和方法执行蚀刻。
下一步骤(步骤336)包括在第一和第二金属接触件区461和471中沉积金属。在诸个实施例中,可将金属沉积成超过恰好第一和第二金属接触件区461和471。在诸个实施例中,可在整个经掺杂的分层制品上将金属沉积至填充第一和第二金属接触件区461和471的深度,且该金属还在先前由接触件掩模452掩盖的区域上提供一层。可经由例如CMP来去除额外的金属,使得保留金属的位置仅是第一和第二金属接触件区461和471以形成第一和第二金属接触件460和470。图4G描绘在形成第一和第二金属接触件460和470之后的分层制品,形成开关元件。
还可在本文所讨论和例示的步骤之前、之后、期间或其组合上执行本文中未描绘或讨论的其它任选制造步骤。还可执行该方法以在一次中制造一个以上的开关元件。
本文中所公开的开关元件可与非易失性存储器单元一起使用,作为非易失性存储器单元的可选元件。用于如本文中所述的存储器件中的非易失性存储器单元可包括许多不同类型的存储器。可用于本文中公开的电子器件中的非易失性存储器单元的示例性类型包括但不限于阻性感测存储器(RSM)单元。示例性RSM单元包括但不限于:铁电RAM(FeRAM或FRAM);磁阻RAM(MRAM);阻性RAM(RRAM);相变存储器(PCM)(也被称为PRAM、PCRAM和C-RAM);可编程金属化单元(PMC)(也被称为导电桥接RAM或CBRAM);以及自旋扭矩转移RAM(也被称为STRAM)。
在诸个实施例中,RSM单元可以是STRAM单元。STRAM存储单元包括MTJ(磁性隧道结),MTJ一般包括被薄的绝缘层分开的两个磁性电极层,其也被称为隧道阻挡层。在图5A中描绘MTJ的实施例。图5A的MTJ 500包括被绝缘层520间隔开的第一磁性层510和第二磁性层530。第一磁性层510和第二磁性层530均可为独立的多层结构。图5B描绘与第一电极层540和第二电极层550相接触的MTJ 500。第一电极层540和第二电极层550分别将第一磁性层510和第二磁性层530电连接到控制电路(未示出),从而经由磁性层提供读写电流。第一磁性层510和第二磁性层530的磁化向量的相对取向可由跨MTJ 500的电阻来确定;并且跨MTJ 500的电阻可由第一磁性层510和第二磁性层530的磁化向量的相对取向来确定。
第一磁性层510和第二磁性层530一般由诸如铁(Fe)、钴(Co)和镍(Ni)合金之类的铁磁合金制成。在诸个实施例中,第一磁性层510和第二磁性层530可由诸如FeMn、NiO、IrMn、PtPdMn、NiMn和TbCo之类的合金制成。绝缘层520一般由诸如氧化铝(Al2O3)或氧化镁(MgO)之类的绝缘材料制成。
磁性层之一(例如第一磁性层510)的磁化一般被钉扎在预定方向上,而另一磁性层(例如第二磁性层530)的磁化方向在自旋扭矩的影响下自由地旋转。第一磁性层510的钉扎可经由例如使用与诸如PtMn、IrMn及其他的反铁磁有序材料的交换偏置来实现。
可通过允许第一电流沿第二磁性层530(自由层)至第一磁性层510(钉扎层)的方向流过存储器单元来对特定的MTJ 500进行读取。MTJ 500的电阻可取决于自由层与钉扎层对齐或反对齐而改变。然后可检测到取决于电阻的电压,并将其与基准电压比较,确定MTJ对齐或反对齐,即包括“1”或“0”。可通过允许第二电流(第二电流大于第一电流)通过MTJ而对特定的MTJ 500进行写入。使电流通过一个路线将写入“1”,且使电流通过另一路线将写入“0”。本文中公开的开关元件的双向特性可提供驱动电流沿两条路线通过MTJ500的能力。
在诸个实施例中,RSM单元可以是RRAM单元。图5C是示例性阻性随机存取存储器(RRAM)单元560的示意图。RRAM单元560包括介质层512,其通过改变介质层512的电阻对电流或电压作出响应。这种现象可被称为电脉冲诱发的变阻效应。该效应将存储器的电阻(即,数据状态),例如,从一个或多个高电阻状态改变到低电阻状态。介质层512插入在第一电极514和第二电极516之间,并且作为RRAM单元的数据存储材料层。第一电极514和第二电极516电连接到电压源(未示出)。第一电极514和第二电极516可由诸如例如金属之类的任何有用的导电材料构成。
构成介质层512的材料可以是任何已知有用的RRAM材料。在诸个实施例中,构成介质层512的材料可包括诸如金属氧化物之类的氧化物材料。在一些实施例中,金属氧化物是二元氧化物材料或复合金属氧化物材料。在其他实施例中,构成介质层512的材料可包括硫族化物固体电解质材料或有机/聚合物材料。
二元金属氧化物材料可被表示为MxOy的化学式。在该式中,字符“M”、“O”、“x”和“y”分别指金属、氧、金属组分比和氧组分比。金属“M”可以是过渡金属和/或铝(Al)。在此情况下,过渡金属可以是镍(Ni)、铌(Nb)、钛(Ti)、锆(Zr)、铪(Hf)、钴(Co)、铁(Fe)、铜(Cu)和/或铬(Cr)。可用作介质层512的二元金属氧化物的具体示例包括:CuO、NiO、CoO、ZnO、CrO2、TiO2、HfO2、ZrO2、Fe2O3和Nb2O5。
在诸个实施例中,金属氧化物可以是任何有用的复合金属氧化物,诸如例如具有式Pr0.7Ca0.3MnO3、或SrTiO3、或SiZrO3的复合氧化物材料、或者掺杂有Cr或Nb的这些氧化物。该复合物还可包括LaCuO4、或Bi2Sr2CaCu2O8。固体硫族化物材料的一个示例是包含银(Ag)成分的锗-硒化物(GexSe100-x)。有机材料的一个示例是聚(3,4-亚乙二氧基噻吩)(即,PEDOT)。
RSM单元还可包括具有与图5C相类似的结构、使用诸如锆钛酸铅(称为“PZT”)或SrBi2Ta2O9(称为“SBT”)之类的材料的铁电电容器。在这些存储单元中,电流可被用于切换偏振方向并且读电流可检测偏振是向上还是向下。在这些实施例中,读操作是破坏性过程,其中单元将丢失包含其中的数据,从而需要刷新以将数据写回到单元。
所公开的存储器元件包括以上公开的开关元件;以及非易失性存储器单元。在图6A中描绘本文中所公开的存储器元件600的示例性实施例。存储器元件600包括开关元件615,该开关元件615包括如上所述和例示的第一半导体层650、绝缘层640、第二半导体层630、第一金属接触件660和第二金属接触件670。相对于存储器单元605的空间取向不旨在受图示限制。取向一般仅旨在示出非易失性存储器单元605串联电连接至金属接触件之一(图6A示出非易失性存储器单元605电连接至第二金属接触件670,但它当然可以是第一金属接触件660)。
图6B是描绘非易失性存储器元件的组件的功能的电路图。如此处所见,开关元件615充当两个并联的单独二极管611和612。开关元件615然后串联至用作电阻器的非易失性存储器单元605。由源680提供的电压可提供大于VT1的电压(见图1C)(这允许电流沿一路线通过电路)或小于的VT2电压(见图1C)(这允许电路沿另一路线通过电路)。两条路线可允许在非易失性存储器单元605上执行各操作,包括确定非易失性存储器单元605的阻态。
本文中所公开的存储器元件可用在存储器阵列中。在诸个实施例中,本文中所公开的存储器元件可用在交叉存储器阵列中。在图7A中示出交叉存储器阵列的示例性描绘。示例性交叉存储器阵列包括被第二层近似平行导体704所覆盖(或在其下方)的第一层近似平行导体702。在诸个实施例中,第二层704的导体在取向上基本上垂直于第一层702的导体。在诸个实施例中,各层之间的取向角可以不是垂直。两层导体形成格子或交叉,其中第二层704的各个导体覆盖在第一层702的所有导体上,且在导体交叉点处与第一层702的各个导体紧密接触,导体交叉点代表两个导体之间的最紧密接触。虽然图7A中的单个导体被示为具有矩形截面,但导体还可具有正方形、圆形、椭圆形、或任何其它规则或不规则的截面。导体还可具有许多不同的宽度或直径以及长宽比或离心率。
以上公开的存储器元件可置于交叉存储器阵列的导体交叉点的至少一些处。在诸个实施例中,所公开的存储器元件可置于基本上所有的导体交叉点处。由所公开的存储器元件连接的导体交叉点可被称为“交叉结”。图7B和7C提供将交叉存储器阵列内的两个连续层的导体702a和704a互联的交叉结的两个不同图示。交叉结点可涉及或可不涉及两个导体702a和704a之间的物理接触。如图7B所示,两个导体在其重叠点处不物理接触,但导体702a和704a之间的间隙被存储器元件706a跨越,该存储器元件706a在两导体最接近的重叠点处位于两导体之间。图7C示出图7B所示的存储器元件706a和重叠的导体702a和704a的示意图。
所公开的存储器元件可有利地用于交叉存储器阵列,因为存储器元件中包括的开关器件可用作集成选择元件,该集成选择元件可避免或最小化在读、写和擦除操作期间由于寄生电流(sneak current)引起的非预期单元上的干扰。本文中所公开的开关器件与STRAM结合尤其有利,因为STRAM要求利用相反极性执行写和擦除操作。
因此,公开了肖特基二极管开关及包含它的存储部件的诸个实施例。上述实现及其他实现在以下权利要求书的范围内。本领域技术人员应当理解,本公开可用除所披露的实施例以外的实施例来实施。所公开的实施例出于说明而非限制的目的而呈现,并且本公开仅由所附权利要求书来限定。
Claims (20)
1.一种开关元件,包括:
第一半导体层,所述第一半导体层具有第一部分和第二部分;
第二半导体层,所述第二半导体层具有第一部分和第二部分;
置于所述第一半导体层和第二半导体层之间的绝缘层;
第一金属接触件,所述第一金属接触件与第一半导体层的第一部分接触形成第一结并且与第二半导体层的第一部分接触形成第二结;
第二金属接触件,所述第二金属接触件与第一半导体层的第二部分接触形成第三结并且与第二半导体层的第二部分接触形成第四结,
其中所述第一结和第四结是肖特基接触,所述第二结和第三结是欧姆接触。
2.如权利要求1所述的开关元件,其特征在于,所述第一半导体层和所述第二半导体层独立地选自:硅、含硅化合物、锗、含锗化合物、含铝化合物、含硼化合物、含镓化合物、含铟化合物、含镉化合物、含锌化合物、含铅化合物、含锡化合物。
3.如权利要求1所述的开关元件,其特征在于,所述第一半导体层是结晶硅且第二部分以磷(P)、硼(B)或砷(As)掺杂。
4.如权利要求1所述的开关元件,其特征在于,所述第二半导体层是结晶硅且第一部分以磷(P)、硼(B)或砷(As)掺杂。
5.如权利要求1所述的开关元件,其特征在于,所述第一半导体层的第二部分和第二半导体层的第一部分以磷(P)、硼(B)或砷(As)重掺杂。
6.如权利要求5所述的开关元件,其特征在于,所述第一半导体层的第一部分和第二半导体层的第二部分未被重掺杂。
7.如权利要求1所述的开关元件,其特征在于,还包括第二绝缘层和衬底层,其中第二绝缘层位于衬底层和第一半导体层之间,且第二绝缘层与第一和第二金属接触件接触。
8.一种非易失性存储器元件,包括:
开关器件,包括:
第一半导体层,所述第一半导体层具有第一部分和第二部分;
第二半导体层,所述第二半导体层具有第一部分和第二部分;
置于所述第一半导体层和第二半导体层之间的绝缘层;
第一金属接触件,所述第一金属接触件与第一半导体层的第一部分接触形成第一结并且与第二半导体层的第一部分接触形成第二结;
第二金属接触件,所述第二金属接触件与第一半导体层的第二部分接触形成第三结并且与第二半导体层的第二部分接触形成第四结,
其中第二结和第三结是欧姆接触;以及
非易失性存储器单元,
其中所述开关器件与非易失性存储器单元串联电连接。
9.如权利要求8所述的非易失性存储器元件,其特征在于,第一结和第四结是肖特基接触。
10.如权利要求8所述的非易失性存储器元件,其特征在于,所述第一半导体层的第二部分和第二半导体层的第一部分以磷(P)、硼(B)或砷(As)掺杂。
11.如权利要求8所述的非易失性存储器元件,其特征在于,所述第一半导体层的第一部分和第二半导体层的第二部分未被掺杂。
12.如权利要求8所述的非易失性存储器元件,其特征在于,所述第一和第二半导体层具有基本相等的厚度。
13.如权利要求8所述的非易失性存储器元件,其特征在于,所述非易失性存储器单元是自旋扭矩转移随机存取存储器(STRAM)层叠。
14.一种形成开关元件的方法,包括以下步骤:
提供分层制品,所述分层制品包括第一半导体层、绝缘层和第二半导体层;
形成第一掩摸区,其中第一掩摸区仅保护所述分层制品的第一部分;
利用第一能级仅掺杂第二半导体层的第一部分;
形成第二掩摸区,其中所述第二掩摸区仅保护分层制品的第二部分,其中所述分层制品的第一部分和第二部分仅部分重叠;
利用第二能级仅掺杂第一半导体层的第二部分,其中第一能级和第二能级是不同的,由此形成经掺杂的分层制品;
仅在经掺杂的分层制品的一部分上形成接触件掩摸;
蚀刻至少所述第二半导体层、所述绝缘层和所述第一半导体层的一部分;
在所述第二半导体层、所述绝缘层和所述第一半导体层的蚀刻区域中形成第一和第二金属接触件。
15.如权利要求14所述的方法,其特征在于,第一能量小于第二能量。
16.如权利要求14所述的方法,其特征在于,提供分层制品包括:
提供第一分层结构,所述第一分层结构包括第一衬底、第二绝缘层和第一半导体层,其中所述第二绝缘层位于第一衬底和第一半导体层之间;
提供第二分层结构,所述第二分层结构包括绝缘层和第二半导体层;
使第二分层结构与第一分层结构接触,使得第二分层结构的绝缘层与第一分层结构的第一半导体层相邻,并且将第一分层结构与第二分层结构接合以形成分层制品。
17.如权利要求16所述的方法,其特征在于,所述第二分层结构至少部分地通过对硅晶片进行氧化来形成。
18.如权利要求16所述的方法,其特征在于,所述第二分层结构至少部分地通过将绝缘材料沉积在硅上来形成。
19.如权利要求14所述的方法,其特征在于,所述第一和第二掩摸区配置成使分层制品的一部分未掺杂。
20.如权利要求18所述的方法,其特征在于,所述分层制品的未掺杂部分基本上与经掺杂的分层制品中被所述接触件掩摸掩盖的部分重合。
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KR101412190B1 (ko) | 2014-06-27 |
WO2011008650A1 (en) | 2011-01-20 |
KR20130099224A (ko) | 2013-09-05 |
US20110006276A1 (en) | 2011-01-13 |
US20120149183A1 (en) | 2012-06-14 |
JP2012533192A (ja) | 2012-12-20 |
US8198181B1 (en) | 2012-06-12 |
JP5702381B2 (ja) | 2015-04-15 |
US20120199936A1 (en) | 2012-08-09 |
KR101368313B1 (ko) | 2014-02-26 |
KR20130099225A (ko) | 2013-09-05 |
KR101444912B1 (ko) | 2014-09-26 |
CN102473706B (zh) | 2016-08-24 |
US8288749B2 (en) | 2012-10-16 |
US8158964B2 (en) | 2012-04-17 |
KR20120026634A (ko) | 2012-03-19 |
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