JP4855863B2 - 磁気メモリ - Google Patents
磁気メモリ Download PDFInfo
- Publication number
- JP4855863B2 JP4855863B2 JP2006217331A JP2006217331A JP4855863B2 JP 4855863 B2 JP4855863 B2 JP 4855863B2 JP 2006217331 A JP2006217331 A JP 2006217331A JP 2006217331 A JP2006217331 A JP 2006217331A JP 4855863 B2 JP4855863 B2 JP 4855863B2
- Authority
- JP
- Japan
- Prior art keywords
- current
- word line
- memory cell
- magnetization
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/10—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having two electrodes, e.g. diodes or MIM elements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/933—Spintronics or quantum computing
- Y10S977/935—Spin dependent tunnel, SDT, junction, e.g. tunneling magnetoresistance, TMR
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
Description
図1は、本発明の第1の実施形態に係るMRAMの構成を示す回路ブロック図である。MRAMは、メモリセルアレイ11及び電流制御回路14〜16を備えている。メモリセルアレイ11は、複数のメモリセルMCがマトリクス状に配置されて構成されている。
第2の実施形態は、上記第1の実施形態においてダイオード13の向きを反対にしてMRAMを構成したものである。
第3の実施形態は、上記第1の実施形態のMRAMを基本構成とし、磁気抵抗素子とダイオードとからなるメモリセルを2層に配置したものである。
第4の実施形態は、上記第2の実施形態のMRAMを基本構成とし、磁気抵抗素子とダイオードとからなるメモリセルを2層に配置したものである。
第5の実施形態は、メモリセルMCに含まれるダイオードに換えてトランジスタを用いてMRAMを構成している。
Claims (5)
- 磁化の方向が固定された磁化固定層と、磁化の向きが変化する磁化自由層と、前記磁化固定層と前記磁化自由層との間に設けられた非磁性層とを含み、かつ前記磁化自由層の磁化の方向に基づいて変化する抵抗値により情報を記録する複数の磁気抵抗素子と、
前記複数の磁気抵抗素子の一端に電気的に接続されたワード線と
を具備し、
情報の消去は、前記ワード線からの電流誘導磁場により前記磁化自由層の磁化の方向を第1の方向に設定することで行われ、かつ複数の磁気抵抗素子に対して一括して行われ、
情報の書き込みは、前記磁気抵抗素子に単方向に電流を供給し、スピン注入磁化反転により前記磁化自由層の磁化の方向を第2の方向に設定することで行われることを特徴とする磁気メモリ。 - 前記複数の磁気抵抗素子の他端に電気的に接続され、かつ前記磁気抵抗素子に流れる電流の向きを設定する複数のダイオードをさらに具備することを特徴とする請求項1に記載の磁気メモリ。
- 前記複数の磁気抵抗素子の他端にソース端子或いはドレイン端子が接続された複数の選択トランジスタをさらに具備することを特徴とする請求項1に記載の磁気メモリ。
- 前記磁気抵抗素子は、ワード線を介して積層されることを特徴とする請求項1又は2に記載の磁気メモリ。
- 前記ワード線は、金属層と、この金属層を覆う磁性層とを含むことを特徴とする請求項1乃至4のいずれかに記載の磁気メモリ。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006217331A JP4855863B2 (ja) | 2006-08-09 | 2006-08-09 | 磁気メモリ |
US11/743,241 US7668005B2 (en) | 2006-08-09 | 2007-05-02 | Magnetic memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006217331A JP4855863B2 (ja) | 2006-08-09 | 2006-08-09 | 磁気メモリ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008041217A JP2008041217A (ja) | 2008-02-21 |
JP4855863B2 true JP4855863B2 (ja) | 2012-01-18 |
Family
ID=39050580
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006217331A Expired - Fee Related JP4855863B2 (ja) | 2006-08-09 | 2006-08-09 | 磁気メモリ |
Country Status (2)
Country | Link |
---|---|
US (1) | US7668005B2 (ja) |
JP (1) | JP4855863B2 (ja) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008227009A (ja) * | 2007-03-09 | 2008-09-25 | Toshiba Corp | 磁気ランダムアクセスメモリ、その書き込み方法及びその製造方法 |
US7782660B2 (en) * | 2008-03-20 | 2010-08-24 | International Business Machines Corporation | Magnetically de-coupling magnetic memory cells and bit/word lines for reducing bit selection errors |
JP5356377B2 (ja) * | 2008-05-28 | 2013-12-04 | 株式会社日立製作所 | 磁気メモリセル及び磁気ランダムアクセスメモリ |
US7974119B2 (en) | 2008-07-10 | 2011-07-05 | Seagate Technology Llc | Transmission gate-based spin-transfer torque memory unit |
JP4738462B2 (ja) * | 2008-09-25 | 2011-08-03 | 株式会社東芝 | 磁気ランダムアクセスメモリ |
KR20100041470A (ko) * | 2008-10-14 | 2010-04-22 | 삼성전자주식회사 | 저항체를 이용한 비휘발성 메모리 장치 |
US7936580B2 (en) | 2008-10-20 | 2011-05-03 | Seagate Technology Llc | MRAM diode array and access method |
US9030867B2 (en) * | 2008-10-20 | 2015-05-12 | Seagate Technology Llc | Bipolar CMOS select device for resistive sense memory |
US7936583B2 (en) | 2008-10-30 | 2011-05-03 | Seagate Technology Llc | Variable resistive memory punchthrough access method |
US7825478B2 (en) | 2008-11-07 | 2010-11-02 | Seagate Technology Llc | Polarity dependent switch for resistive sense memory |
US8178864B2 (en) | 2008-11-18 | 2012-05-15 | Seagate Technology Llc | Asymmetric barrier diode |
US8203869B2 (en) | 2008-12-02 | 2012-06-19 | Seagate Technology Llc | Bit line charge accumulation sensing for resistive changing memory |
US8159856B2 (en) | 2009-07-07 | 2012-04-17 | Seagate Technology Llc | Bipolar select device for resistive sense memory |
US8406041B2 (en) * | 2009-07-08 | 2013-03-26 | Alexander Mikhailovich Shukh | Scalable magnetic memory cell with reduced write current |
US9171601B2 (en) | 2009-07-08 | 2015-10-27 | Alexander Mikhailovich Shukh | Scalable magnetic memory cell with reduced write current |
US8158964B2 (en) | 2009-07-13 | 2012-04-17 | Seagate Technology Llc | Schottky diode switch and memory units containing the same |
US8411494B2 (en) * | 2009-07-21 | 2013-04-02 | Alexander Mikhailovich Shukh | Three-dimensional magnetic random access memory with high speed writing |
US8228715B2 (en) * | 2010-05-28 | 2012-07-24 | Everspin Technologies, Inc. | Structures and methods for a field-reset spin-torque MRAM |
FR2964248B1 (fr) * | 2010-09-01 | 2013-07-19 | Commissariat Energie Atomique | Dispositif magnetique et procede de lecture et d’ecriture dans un tel dispositif magnetique |
US8648426B2 (en) | 2010-12-17 | 2014-02-11 | Seagate Technology Llc | Tunneling transistors |
US8976577B2 (en) * | 2011-04-07 | 2015-03-10 | Tom A. Agan | High density magnetic random access memory |
JP5740267B2 (ja) * | 2011-09-26 | 2015-06-24 | 株式会社東芝 | 磁気抵抗効果素子、ダイオードおよびトランジスタを用いた磁気ランダムアクセスメモリ |
US8952470B2 (en) | 2012-09-10 | 2015-02-10 | James John Lupino | Low cost high density nonvolatile memory array device employing thin film transistors and back to back Schottky diodes |
US9853053B2 (en) | 2012-09-10 | 2017-12-26 | 3B Technologies, Inc. | Three dimension integrated circuits employing thin film transistors |
KR101417956B1 (ko) | 2012-12-05 | 2014-08-14 | 한국과학기술연구원 | 스핀토크를 이용한 측면형 스핀 소자 |
US9236416B2 (en) | 2013-05-30 | 2016-01-12 | Alexander Mikhailovich Shukh | High density nonvolatile memory |
JP6386231B2 (ja) * | 2014-02-03 | 2018-09-05 | 国立大学法人東北大学 | 磁気トンネル接合素子を備えた記憶装置 |
CN107112049A (zh) | 2014-12-23 | 2017-08-29 | 3B技术公司 | 采用薄膜晶体管的三维集成电路 |
US11545201B2 (en) | 2020-06-23 | 2023-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device with unipolar selector |
CN114694704A (zh) * | 2020-12-29 | 2022-07-01 | 长鑫存储技术有限公司 | 磁性存储器及其读写方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5695864A (en) | 1995-09-28 | 1997-12-09 | International Business Machines Corporation | Electronic device using magnetic components |
US5640343A (en) * | 1996-03-18 | 1997-06-17 | International Business Machines Corporation | Magnetic memory array using magnetic tunnel junction devices in the memory cells |
JP2001148189A (ja) * | 1999-11-19 | 2001-05-29 | Hitachi Ltd | データ書き込み方法 |
US6911710B2 (en) * | 2000-03-09 | 2005-06-28 | Hewlett-Packard Development Company, L.P. | Multi-bit magnetic memory cells |
JP4667594B2 (ja) | 2000-12-25 | 2011-04-13 | ルネサスエレクトロニクス株式会社 | 薄膜磁性体記憶装置 |
US7190611B2 (en) * | 2003-01-07 | 2007-03-13 | Grandis, Inc. | Spin-transfer multilayer stack containing magnetic layers with resettable magnetization |
JP4192060B2 (ja) * | 2003-09-12 | 2008-12-03 | シャープ株式会社 | 不揮発性半導体記憶装置 |
JP2007109313A (ja) * | 2005-10-13 | 2007-04-26 | Renesas Technology Corp | 不揮発性半導体記憶装置 |
-
2006
- 2006-08-09 JP JP2006217331A patent/JP4855863B2/ja not_active Expired - Fee Related
-
2007
- 2007-05-02 US US11/743,241 patent/US7668005B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US7668005B2 (en) | 2010-02-23 |
US20080037314A1 (en) | 2008-02-14 |
JP2008041217A (ja) | 2008-02-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4855863B2 (ja) | 磁気メモリ | |
TWI666635B (zh) | Semiconductor memory device | |
JP3906212B2 (ja) | 磁気ランダムアクセスメモリ | |
CN1758372B (zh) | 磁存储器 | |
US7173846B2 (en) | Magnetic RAM and array architecture using a two transistor, one MTJ cell | |
EP1480226A2 (en) | MRAM having memory cell array in which cross-point memory cells are arranged by hierarchical bit line scheme and data read method thereof | |
US8385114B2 (en) | Nonvolatile memory circuit using spin MOS transistors | |
JP2005064050A (ja) | 半導体記憶装置及びそのデータ書き込み方法 | |
US20060114715A1 (en) | Memory | |
JP4855821B2 (ja) | 磁気記憶装置 | |
US9437270B2 (en) | Nonvolatile memory apparatus for controlling a voltage level of enabling a local switch | |
JP2008004199A (ja) | 半導体記憶装置 | |
CN106663465A (zh) | 非易失性半导体存储器 | |
US7471549B2 (en) | Semiconductor memory device | |
US6909628B2 (en) | High density magnetic RAM and array architecture using a one transistor, one diode, and one MTJ cell | |
JP2013026337A (ja) | 半導体装置及び磁気ランダムアクセスメモリ | |
US20220351767A1 (en) | Magnetic random access memory and electronic device | |
TW200414188A (en) | System for and method of accessing a four-conductor magnetic random access memory | |
TWI823232B (zh) | 非揮發性記憶體元件 | |
US6912174B2 (en) | Thin film magnetic memory device suppressing influence of magnetic field noise from power supply wiring | |
JP5036854B2 (ja) | 半導体装置 | |
KR102677729B1 (ko) | 반도체 회로 및 전자 기기 | |
JP4726169B2 (ja) | 磁気メモリ及びその駆動方法 | |
US7027324B2 (en) | Method and system for providing common read and write word lines for a segmented word line MRAM array | |
KR101605607B1 (ko) | 접힌 메모리 어레이 구조를 가지는 자기 저항 메모리 장치 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090209 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110916 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111004 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20111027 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141104 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141104 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |