CN102386114A - 芯片接合的方法 - Google Patents

芯片接合的方法 Download PDF

Info

Publication number
CN102386114A
CN102386114A CN2011100724813A CN201110072481A CN102386114A CN 102386114 A CN102386114 A CN 102386114A CN 2011100724813 A CN2011100724813 A CN 2011100724813A CN 201110072481 A CN201110072481 A CN 201110072481A CN 102386114 A CN102386114 A CN 102386114A
Authority
CN
China
Prior art keywords
workpiece
heating
chip
type substrate
substrate carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011100724813A
Other languages
English (en)
Other versions
CN102386114B (zh
Inventor
黄见翎
黄英叡
林正忠
刘重希
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102386114A publication Critical patent/CN102386114A/zh
Application granted granted Critical
Publication of CN102386114B publication Critical patent/CN102386114B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0012—Brazing heat exchangers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/20—Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
    • B23K1/203—Fluxing, i.e. applying flux onto surfaces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
    • B23K3/08—Auxiliary devices therefor
    • B23K3/087—Soldering or brazing jigs, fixtures or clamping means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/42—Printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7565—Means for transporting the components to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75743—Suction holding means
    • H01L2224/75744—Suction holding means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75743—Suction holding means
    • H01L2224/75745—Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75754—Guiding structures
    • H01L2224/75755—Guiding structures in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/81204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81905—Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
    • H01L2224/81907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

一种芯片接合的方法，包含提供第一工件，以及将第二工件附着在第一工件上，焊料凸块设置在第一工件与第二工件之间，使用加热工具的加热头加热第二工件，熔融焊料凸块，在加热第二工件的步骤之后，允许第一工件与第二工件中的一个在水平方向自由地移动，以自行对准第一与第二工件，在允许第一工件与第二工件中的一个移动的步骤之后，降低加热头的温度，直至第一焊料凸块固化形成第二焊料凸块。本发明通过将芯片粘着工艺与回焊工艺分开在两个独立的工具模块中进行，可改善TCB接合的生产率。此外，使用多头加热工具可进一步地改善生产率。夹具型基底载体使得基底可以在水平方向移动，并且使得基底自行对准芯片，改善芯片与基底之间对准的准确度。

Description

芯片接合的方法
技术领域
本发明涉及芯片接合的方法，尤其涉及芯片热压接合的方法。
背景技术
在半导体晶片上形成集成电路，然后切割成半导体芯片，接着将半导体芯片接合至封装基底上。在接合工艺期间，介于半导体芯片与封装基底之间的焊料凸块会进行回焊，传统的回焊方法包含传统型回焊以及热压回焊。传统型回焊具有相对较高的生产率，因为多个封装基底与其上方的芯片可经由回焊工艺同时接合在一起。然而，传统型回焊需要一段长的时间加热焊料凸块，其产生的高热预算会在芯片内造成明显的翘曲，并且可能会在低介电常数介电层之间造成脱层。
热压接合需要的热预算较传统型回焊低，然而，热压接合的生产率非常低，在热压接合期间，焊头(bond head)拾起芯片，将芯片翻转，并且将芯片附着至封装基底，然后焊头经过温度上升工艺，加热芯片以及用于接合芯片与封装基底的焊料凸块。在焊料凸块熔融之后，焊头经过冷却工艺，使得焊料凸块固化，针对每个芯片需重复此工艺，因此热压接合的生产率非常低，其生产率有时可能只有传统型回焊生产率的1/15。
发明内容
依据一实施例，芯片接合的方法包含提供第一工件，以及在第一工件上附着第二工件，第一焊料凸块设置在第一工件与第二工件之间。使用加热工具的加热头加热第二工件，使第一焊料凸块熔融，在加热第二工件的步骤之后，允许第一工件与第二工件中的一个在水平方向自由地移动，让第一工件与第二工件自行对准，在允许第一工件与第二工件中的一个移动的步骤之后，降低加热头的温度，直到第一焊料凸块固化，形成第二焊料凸块。
依据其他实施例，芯片接合的方法包含提供夹具型基底载体，其包含多个工件支撑架；将多个第一工件放置于这些工件支撑架内，其中这些第一工件的边缘部分直接位于夹具型基底载体的阻挡臂下方，且与阻挡臂垂直地重叠；以及在这些第一工件上方放置多个第二工件，焊料凸块接合这些第二工件至第一工件。此方法更包含对焊料凸块进行回焊，并且在焊料凸块熔融之后，将这些第二工件与在熔融状态的焊料凸块一起提起，其中这些第一工件被提起，悬挂在这些第二工件下方，且夹具型基底载体没有被提起。然后，降低焊料凸块的温度至焊料凸块的熔融温度之下。
依据另一实施例，芯片接合的方法包含提供夹具型基底载体的主体，其包括多个工件支撑架；将多个第一工件放置于这些工件支撑架内；在这些第一工件上附着多个第二工件，焊料凸块接合这些第二工件至第一工件；将夹具型基底载体的盖板放置在夹具型基底载体的主体上，其中盖板包括阻挡臂直接延伸至这些第一工件的边缘上方，并且与这些第一工件的边缘接触；在焊料凸块上方放置多个加热头，并回焊焊料凸块，其中每个加热头接触一个第二工件；通过使用这些加热头加热焊料凸块而使焊料凸块回焊；在焊料凸块熔融之后，从这些加热头释放这些第二工件；以及在释放这些第二工件的步骤之后，于焊料凸块在熔融状态下，使用这些加热头提起这些第二工件。
依据又另一实施例，芯片接合的方法包含提供夹具型基底载体的主体，其包括多个工件支撑架；将多个第一工件放置于这些工件支撑架内；使用第一工具模块，将多个第二工件附着在这些第一工件上，焊料凸块接合这些第二工件至第一工件；将夹具型基底载体的盖板放置在夹具型基底载体的主体上，将夹具型基底载体以及这些第一与第二工件转移至第二工具模块；以及使用多头加热工具的多个加热头回焊焊料凸块，这些加热头接触这些第二工件，多头加热工具包含在第二工具模块内。
本发明通过将芯片粘着工艺与回焊工艺分开在两个独立的工具模块中进行，可改善TCB接合的生产率。此外，使用多头加热工具可进一步地改善生产率。夹具型基底载体使得基底可以在水平方向移动，并且使得基底自行对准芯片，改善芯片与基底之间对准的准确度。
为了让本发明的上述目的、特征、及优点能更明显易懂，以下配合附图，作详细说明如下。
附图说明
图1及图2分别显示夹具型基底载体的本体与盖板的透视图。
图3显示芯片粘着头拾起芯片的示意图。
图4显示将芯片附着至封装基底上的工艺，其中封装基底位于夹具型基底载体的工件支撑架内。
图5A与图5B分别显示在芯片与封装基底之间的焊料凸块进行回焊的透视图与剖面示意图，其中使用多头加热工具加热焊料凸块。
图6显示通过加热工具提起芯片。
图7至图9显示依据其他实施例，在芯片与封装基底之间的焊料凸块进行回焊的中间阶段的剖面示意图。
图10及图11分别显示使用双头加热工具及四头加热工具进行焊料凸块的回焊。
图12显示在多头加热工具内的加热头的温度曲线图。
其中，附图标记说明如下：
20～夹具型基底载体；20A～本体；20B～盖板；20B’～阻挡臂；22～工件支撑架；24～开口；28～芯片粘着头；30～芯片；32～晶片；34～焊料凸块；40～封装基底；42～金属凸块；44～多头加热工具；45、48～平台；46～加热头；47～芯片提起的方向；49～封装基底移动的方向；50～多头加热工具移动的路径。
具体实施方式
以下详细讨论揭示的实施例的制造与使用，然而，可以理解的是，这些实施例提供许多可应用的发明概念，其可以在各种特定背景中实施，在此所讨论的特定实施例仅用于说明，并非限定公开的范围。
本发明的实施例提供一种新的热压接合(thermal compress bonding；TCB)工艺，各种实施例的中间制造阶段说明如下，同时也说明实施例的各种变化。在各种附图与实施例中，使用相似的附图标记标示相似的元件。
图1及图2分别显示夹具型基底载体(jig-type substrate carrier)20的本体与盖板，参阅图1，夹具型基底载体20的本体20A包含多个工件支撑架(workpiece holder)22，其可以排列成具有多行与多列的阵列。虽然图1只显示工件支撑架22为2x3的阵列，基底载体20的工件支撑架可具有任何数目的行与列。工件支撑架22可包含部分的主体20A，其形成孔洞的侧壁与底部，在孔洞中可放置工件。
参阅图2，提供夹具型基底载体20的盖板20B，盖板20B也包含多个开口24，盖板20B可牢固在本体20A上，使得盖板20B与本体20A可以被搬运，并且被视为整合的单元使用。当盖板20B牢固在本体20A上时，每个开口24直接位于一个工件支撑架22上方。此外，本体20A(图1)的长度L1与宽度W1大于盖板20B的个别长度L2与宽度W2，使得盖板20放置在本体20A上之后，每个工件支撑架22的边缘部分会被部分的盖板20B覆盖，而每个工件支撑架22的中央部分则不会被覆盖。
再参阅图1，在工件支撑架22内放置多个工件40，每个工件支撑架22支撑一个工件40。在一实施例中，工件40为封装基底或中介层(interposer)，其不具有有源元件例如晶体管在其中。在另一实施例中，工件40为元件芯片(device die)，其具有有源元件例如晶体管(未示出)在其中。在整篇说明书的描述中，工件40另外也称为(封装)基底40，虽然它们也可以是其他类型的工件。金属凸块42在基底40的顶端表面上形成，基底40的长度L3与宽度W3小于工件支撑架22的个别长度L1与宽度W1。另外，基底40的长度L3与宽度W3中的至少一个以及可能两个都大于盖板20B的开口24的个别长度L2与宽度W2。
参阅图3，使用芯片粘着头(die-attach head)28将工件30拾起，工件30也可以是元件芯片、中介层、封装基底或类似的物件。在整篇说明书的描述中，工件30也称为芯片30，虽然它们也可以是其他类型的工件。芯片30可从晶片切割得到，如图3所示的晶片32，然而芯片30也可能放置在芯片托盘(die tray)(未示出)中，并且芯片粘着头28可从芯片托盘中拾起芯片30。芯片粘着头28被配置成使用真空拾起芯片30，并且将芯片30表面上的焊料凸块34(在图3中未示出，请参阅图4)浸泡在助熔剂(flux)中。芯片粘着头28是工具模块(之后称为芯片粘着模块)的一部分，其用于执行芯片粘着工艺。
图4显示使用压缩放置(compressive placement)方式将芯片30粘着在基底40上，其中也使用芯片粘着头28。在进行芯片粘着期间，夹具型基底载体20的本体20A可放置在平台45上，并且可将夹具型基底载体20的本体20A牢固在平台45上，例如使用真空的方式。平台45也是芯片粘着模块的一部分，在芯片粘着之后，焊料凸块34接触基底40的金属凸块42，虽然凸块34被称为焊料凸块，凸块34也可以是非回焊(non-reflowable)金属凸块，例如铜柱凸块。然而，凸块34与42中的至少一个，以及可能两个都是焊料凸块，因此，位于芯片30与基底40之间的焊料凸块之后称为焊料凸块34/42。为了完成芯片粘着，芯片粘着头28施加一向下的力，例如少于约5NT，使得焊料凸块34可粘着在金属凸块42上，芯片粘着头28可重复执行芯片30的拾起、助熔剂浸泡以及压缩放置的工艺，直至全部的基底40都具有芯片30放置在其上。
在进行芯片粘着期间，芯片粘着头28的温度可以在例如低于约50℃的低温，并且可以在室温。在芯片30进行芯片粘着之后，将盖板20B放置在本体20A上，并牢固于本体20A上(参阅图5B)，因此夹具型基底载体20、基底40以及芯片30形成整合的部件，并且可从芯片粘着模块转移开，使得焊料凸块34/42可以被回焊。芯片30的水平长度L4与宽度W4(在图4中未示出W4，请参阅图10)小于图2中开口24的个别尺寸L2与W2。因此，即使芯片30已经粘着至基底40上，盖板20B仍可放置在本体20A上。
图5A及图5B分别显示焊料凸块34/42进行回焊的透视图与剖面示意图，夹具型基底载体20可放置在平台48(图5B)上，平台48可使用真空固定住夹具型基底载体20。此外，平台48可在后续的回焊工艺之前预热基底40，例如以低于100℃的温度进行预热。接着，如图5A所示，多个加热头46，其为多头(multi-head)加热工具44的一部分，接触芯片30的顶端表面，每个加热头46接触一个芯片30。如图5B所示，加热头46加热芯片30直到焊料凸块34/42熔融。
接着，如图6所示，加热头46，其也具有使用真空拾起芯片30的能力，将芯片30提起，如箭头47所示。通过熔融的焊料凸块34/42的表面张力，基底40也被提起，在提起的工艺期间，基底40自由地垂挂在个别的芯片30下方，并且自由地沿着水平方向移动，如箭头49所示。因此，基底40会自行对准其上方个别的芯片30。因为基底40的长度L3以及/或宽度W3(图1)大于开口24的个别长度L2以及/或宽度W2(图2)，基底40被一部分的盖板20B阻挡，这个部分之后称为阻挡臂(blocking arms)20B’。阻挡臂20B’直接位于个别基底40的边缘部分上方，并且与边缘部分重叠。调整芯片30被提起的距离，使得基底40被盖板20B阻挡之后，芯片30可以持续地稍微被提起，并且熔融的焊料凸块34/42可以在垂直方向被拉伸。因此，熔融的焊料凸块34/42的高度被调整，并且降低相邻的焊料凸块34/42之间产生架桥的可能性。然后可降低加热头46的温度至低于焊料凸块34/42的熔融温度，使熔融的焊料凸块34/42固化，然后加热头46释放个别的芯片30。
图7至图9显示依据其他实施例，在芯片与封装基底之间的焊料凸块进行回焊的中间阶段的剖面示意图，除非特别指出，在这些实施例中的附图标记表示与图1至图6的实施例中所示的元件相似，这些实施例的初始步骤基本上与图1至图5A所示相同。图7显示夹具型基底载体20的盖板20B放置在本体20A上之后，其结构的部分剖面示意图。选择夹具型基底载体20的本体20A的厚度，使得阻挡臂20B’的底部接触基底40的顶部表面的边缘部分，并因而将基底40的位置固定，使其无法垂直地与水平地移动。在后续的回焊工艺之前，使用平台48预热基底40，例如预热至温度低于100℃。
多头加热工具44的多个加热头46接触芯片30的顶端表面，每个加热头46接触一个芯片30，加热头46加热芯片，使得焊料凸块34/42熔融。
接着，参阅图8，加热头46释放其底下个别的芯片30，例如通过释放真空的方式达成。此外，加热头46可在一段短时间内提起芯片30，并且不接触芯片30。在一示范性实施例中，这段时间介于约1秒至2秒之间。在其他实施例中，这段时间介于约0.5秒至约4秒之间。在这段时间内，基底40仍然被阻挡臂20B’固定在原处，然而，因为焊料凸块34/42为液态，芯片30在水平方向与垂直方向可以自由地稍微移动。因此，因为芯片30在水平方向可以移动，芯片30会自行对准其下方个别的基底40。
接着，如图9所示，将加热头46再次放置成与芯片30接触，然后稍微地将芯片30提起，如箭头47所示。在这些实施例中，因为阻挡臂20B’将基底40扣留在原处，基底40不会沿着水平以及/或垂直方向自由地移动。调整提起芯片30的距离，使得熔融的焊料凸块34/42的高度调整至所需的数值，并且降低在相邻的焊料凸块34/42之间产生架桥的可能性。然后可将加热头46的温度降低至低于焊料凸块34/4的熔融温度，并因此使熔融的焊料凸块34/42固化，然后加热头46释放个别的芯片30。
在一实施例中，通过回焊模块进行回焊，其包含多头加热工具44以及平台48。在一实施例中，用于进行芯片粘着(图4)的芯片粘着模块以及用于进行回焊(图5A至图9)的回焊模块是属于相同TCB工具的不同工具模块。另外，芯片粘着模块与回焊模块可属于不同的工具。
图10及图11显示使用多头加热工具44进行的两个回焊工艺，参阅图10，多头加热工具44包含两个加热头46，并且因此可同时进行两个芯片30的接合，在两个芯片30的接合完成之后，可移动多头加热工具44至下两个芯片30进行回焊，箭头50显示多头加热工具44可能的移动路径。在图11中，多头加热工具44具有四个加热头46，并且因此可同时进行四个芯片30的接合，在四个芯片30的接合完成之后，可移动多头加热工具44至下四个芯片30，同样地，箭头50显示多头加热工具44可能的移动路径。在图10及图11所示的示范性实施例中，夹具型基底载体20中工件支撑架的总数量为32，因此，多头加热工具44中加热头46的数量可以像32一样多，并且也可以像2一样少，或者可等于任何其他可应用的数量，例如2、4、8、12以及16。
由于加热头46(图第5A及图5B)不执行拾起与放置芯片30的工作，因此加热头46的温度可保持在高温。例如图12所示的加热头46的温度曲线图，在第一回焊工艺的开始，加热头46的温度为T1，其高于室温，并且可高于约150℃，或甚至高于约180℃，温度T1也低于焊料凸块34/42的熔融温度T0，其例如可为约220℃至约260℃。在第一回焊工艺期间，加热头46的温度升高至温度T2，其高于温度T0，并且足够高至让焊料凸块34/42熔融。在第一回焊工艺之后，加热头46的温度降低，例如降回温度T1，或甚至更低，在第一回焊工艺中的温度曲线图可重复用在第二回焊工艺以及额外的回焊工艺。保持加热头46的温度在高温可减少温度上升的时间与冷却的时间，并因此也可改善TCB工艺的生产率。在其他实施例中，于第一回焊工艺之后，加热头46的温度也可降回低温，例如接近室温。
通过将芯片粘着工艺与回焊工艺分开在两个独立的工具模块中进行，可改善TCB接合的生产率。此外，使用多头加热工具可进一步地改善生产率。夹具型基底载体使得基底可以在水平方向移动，并且使得基底自行对准芯片，改善芯片与基底之间对准的准确度。
虽然本发明已公开较佳实施例如上，然其并非用以限定本发明，在此技术领域中的普通技术人员应当可以了解，在不脱离本发明的精神和范围内，当可做些许更动与润饰。因此，本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (11)

1.一种芯片接合的方法，包括：
提供一第一工件；
在该第一工件上附着一第二工件，具有一第一焊料凸块介于该第一工件与该第二工件之间；
使用一加热工具的一加热头加热该第二工件，使该第一焊料凸块熔融；
在加热该第二工件的该步骤之后，允许该第一工件与该第二工件中的一个在一水平方向自由地移动，使该第一工件与该第二工件自行对准；以及
在允许该第一工件与该第二工件中的一个移动的该步骤之后，降低该加热头的温度，直到该第一焊料凸块固化，形成一第二焊料凸块。
2.如权利要求1所述的接合的方法，其中允许该第一工件与该第二工件中的一个移动的该步骤包括：
从该加热头释放该第二工件；以及
在释放该第二工件的该步骤之后，使用该加热头将该第二工件提起，在提起的该步骤期间，该第一焊料凸块被熔融，其中该第一工件被固定在原处，且不会与该第二工件一起移动。
3.如权利要求2所述的接合的方法，其中在释放所述多个第二工件的该步骤与提起所述多个第二工件的该步骤之间的一时间间隔为介于1秒至2秒之间，且在该时间间隔期间，所述多个第一工件自由地移动而不会被阻挡。
4.如权利要求1所述的接合的方法，其中允许该第一工件与该第二工件中的一个移动的该步骤包括：
使用该加热头将该第二工件提起，该第一工件在该第二工件下方自由地悬挂；
在提起该第二工件的该步骤之后，以及在降低该加热头温度的该步骤之前，阻止该第一工件的一垂直的移动；以及
在阻止该第一工件的该垂直的移动的该步骤之后，持续地提起该第二工件。
5.如权利要求1所述的接合的方法，还包括在附着该第二工件的该步骤之前，将该第一工件放置在一夹具型基底载体内，该夹具型基底载体包括一主体，该主体还包括一工件支撑架，其中该第一工件放置在该工件支撑架内，且其中该夹具型基底载体包括多个阻挡臂，直接延伸在该第一工件的一边缘部分之上。
6.如权利要求5所述的接合的方法，其中该夹具型基底载体包括：
多个工件支撑架；以及
一盖板，该盖板包括一开口；
其中该第一工件的一水平尺寸小于该工件支撑架的一个别的水平尺寸，且大于该开口的一个别的水平尺寸，且其中该第二工件的一水平尺寸小于该开口的该个别的水平尺寸。
7.一种芯片接合的方法，包括：
提供一夹具型基底载体，包括多个工件支撑架；
将多个第一工件放置于所述多个工件支撑架内，其中所述多个第一工件的多个边缘部分直接位于该夹具型基底载体的多个阻挡臂下方，且与所述多个阻挡臂垂直地重叠；
在所述多个第一工件上放置多个第二工件，具有多个焊料凸块接合所述多个第二工件至所述多个第一工件；
回焊所述多个焊料凸块；
在所述多个焊料凸块熔融之后，将所述多个第二工件与在一熔融状态的所述多个焊料凸块一起提起，其中所述多个第一工件被提起，悬挂在所述多个第二工件下方，且其中该夹具型基底载体没有被提起；以及
降低所述多个焊料凸块的一温度至所述多个焊料凸块的一熔融温度之下。
8.如权利要求7所述的接合的方法，其中在降低所述多个焊料凸块的该温度的该步骤的整个期间，所述多个第一工件悬挂在所述多个第二工件下方。
9.如权利要求7所述的接合的方法，还包括在放置所述多个第一工件至所述多个工件支撑架内的该步骤之后，将该夹具型基底载体的一盖板牢固在该夹具型基底载体的一主体之上，其中所述多个工件支撑架为该主体的一部分，且该盖板的一部分作为所述多个阻挡臂。
10.如权利要求7所述的接合的方法，还包括：
在提起所述多个第二工件的该步骤之后，以及在降低所述多个焊料凸块的该温度的该步骤之前，使用所述多个阻挡臂阻止所述多个第一工件的一垂直的移动；以及
在阻止所述多个第一工件的该垂直的移动的该步骤之后，持续地提起所述多个第二工件。
11.如权利要求7所述的接合的方法，其中回焊所述多个焊料凸块的该步骤，以及降低所述多个焊料凸块的该温度的该步骤是使用一多头加热工具进行，该多头加热工具包括多个加热头，每个该加热头接触一个该第二工件。
CN2011100724813A 2010-09-01 2011-03-22 芯片接合的方法 Expired - Fee Related CN102386114B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/874,009 2010-09-01
US12/874,009 US8104666B1 (en) 2010-09-01 2010-09-01 Thermal compressive bonding with separate die-attach and reflow processes

Publications (2)

Publication Number Publication Date
CN102386114A true CN102386114A (zh) 2012-03-21
CN102386114B CN102386114B (zh) 2013-09-11

Family

ID=45508070

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011100724813A Expired - Fee Related CN102386114B (zh) 2010-09-01 2011-03-22 芯片接合的方法

Country Status (3)

Country Link
US (2) US8104666B1 (zh)
CN (1) CN102386114B (zh)
TW (1) TWI445108B (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI556373B (zh) * 2012-07-26 2016-11-01 台灣積體電路製造股份有限公司 用以加工半導體裝置的系統及用以加工半 導體裝置的方法
CN107968065A (zh) * 2016-10-20 2018-04-27 矽品精密工业股份有限公司 电子构件的置放制程及其应用的承载治具
CN110164783A (zh) * 2018-02-13 2019-08-23 三星电子株式会社 用于回流的堆叠工具以及包括该堆叠工具的回流装置
CN110729217A (zh) * 2019-10-22 2020-01-24 江苏佳晟精密设备科技有限公司 一种安装半导体芯片的装置
CN112201585A (zh) * 2020-06-29 2021-01-08 深圳卓橙科技有限公司 一种融合smt的mcm集成电路封装方法

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8381965B2 (en) 2010-07-22 2013-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal compress bonding
US9312240B2 (en) * 2011-01-30 2016-04-12 UTAC Headquarters Pte. Ltd. Semiconductor packages and methods of packaging semiconductor devices
JP5865639B2 (ja) * 2011-09-15 2016-02-17 ファスフォードテクノロジ株式会社 ダイボンダ及びボンディング方法
US8349116B1 (en) 2011-11-18 2013-01-08 LuxVue Technology Corporation Micro device transfer head heater assembly and method of transferring a micro device
US8794501B2 (en) 2011-11-18 2014-08-05 LuxVue Technology Corporation Method of transferring a light emitting diode
US9773750B2 (en) * 2012-02-09 2017-09-26 Apple Inc. Method of transferring and bonding an array of micro devices
US9842817B2 (en) 2012-02-27 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Solder bump stretching method and device for performing the same
US9475145B2 (en) 2012-02-27 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Solder bump joint in a device including lamellar structures
US8870051B2 (en) * 2012-05-03 2014-10-28 International Business Machines Corporation Flip chip assembly apparatus employing a warpage-suppressor assembly
US10199350B2 (en) * 2012-05-25 2019-02-05 Asm Technology Singapore Pte Ltd Apparatus for heating a substrate during die bonding
US9123860B2 (en) 2012-08-01 2015-09-01 Flextronics Ap, Llc Vacuum reflow voiding rework system
US9252309B2 (en) * 2012-08-01 2016-02-02 Flextronics Ap, Llc Hot bar soldering
US9059241B2 (en) * 2013-01-29 2015-06-16 International Business Machines Corporation 3D assembly for interposer bow
US9331032B2 (en) * 2013-03-06 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding and apparatus for performing the same
US9521795B2 (en) * 2013-03-12 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Two-step direct bonding processes and tools for performing the same
US9776270B2 (en) 2013-10-01 2017-10-03 Globalfoundries Inc. Chip joining by induction heating
KR102270748B1 (ko) 2013-11-07 2021-06-30 삼성전자주식회사 솔더볼 부착 장치, 솔더볼 부착 방법 및 이를 포함하는 반도체 패키지의 제조 방법
US9427818B2 (en) * 2014-01-20 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor processing boat design with pressure sensor
US9296056B2 (en) * 2014-07-08 2016-03-29 International Business Machines Corporation Device for thermal management of surface mount devices during reflow soldering
CN105448750A (zh) * 2014-08-28 2016-03-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置
US10319619B2 (en) * 2014-12-05 2019-06-11 Samsung Electronics Co., Ltd. Equipment for manufacturing semiconductor devices and method for use of same for manufacturing semiconductor package components
US10014272B2 (en) * 2015-05-11 2018-07-03 Asm Technology Singapore Pte Ltd Die bonding with liquid phase solder
WO2017031100A1 (en) * 2015-08-20 2017-02-23 MRSI Systems, LLC Die placement head with turret
TWI607587B (zh) * 2016-09-13 2017-12-01 台灣琭旦股份有限公司 固晶穩固製程
US10217729B2 (en) * 2016-09-30 2019-02-26 Intel Corporation Apparatus for micro pick and bond
EP4052829B1 (en) * 2017-08-10 2024-05-01 Hakko Corporation Soldering iron control device, cartridge, and soldering iron management system
JP6517412B1 (ja) * 2018-07-12 2019-05-22 白光株式会社 はんだこて制御装置
CN109108422B (zh) * 2018-10-09 2023-10-13 中山市微焊科技有限公司 循环水冷热压锡焊装置
US11978720B2 (en) * 2021-01-28 2024-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device package and methods of manufacture

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10223693A (ja) * 1997-02-12 1998-08-21 Toshiba Corp 電子部品実装方法および電子部品実装装置
US5975409A (en) * 1997-08-12 1999-11-02 International Business Machines Corporation Ceramic ball grid array using in-situ solder stretch
CN1451178A (zh) * 1999-10-26 2003-10-22 英特尔公司 改进的倒装芯片连接封装
CN1513206A (zh) * 2001-03-28 2004-07-14 ض� 无焊剂倒装芯片互连
CN1949469A (zh) * 2005-10-12 2007-04-18 恩益禧电子股份有限公司 在布线板上贴装半导体器件以确保其间不变间隙的焊接方法及其焊接装置
CN1965401A (zh) * 2004-06-08 2007-05-16 松下电器产业株式会社 元器件安装方法及元器件安装装置

Family Cites Families (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE559732A (zh) 1956-10-31 1900-01-01
US3458102A (en) * 1967-08-09 1969-07-29 Kulicke & Soffa Ind Inc Semiconductor wafer pickup and bonding tool
US4607779A (en) 1983-08-11 1986-08-26 National Semiconductor Corporation Non-impact thermocompression gang bonding method
US4763827A (en) 1984-08-13 1988-08-16 Hitachi, Ltd. Manufacturing method
US4878611A (en) * 1986-05-30 1989-11-07 American Telephone And Telegraph Company, At&T Bell Laboratories Process for controlling solder joint geometry when surface mounting a leadless integrated circuit package on a substrate
US4865245A (en) 1987-09-24 1989-09-12 Santa Barbara Research Center Oxide removal from metallic contact bumps formed on semiconductor devices to improve hybridization cold-welds
US5059559A (en) 1987-11-02 1991-10-22 Hitachi, Ltd. Method of aligning and bonding tab inner leads
JPH02206138A (ja) * 1989-02-06 1990-08-15 Shimadzu Corp フリップチップ実装方法
US5113581A (en) 1989-12-19 1992-05-19 Matsushita Electric Industrial Co., Ltd. Outer lead bonding head and method of bonding outer lead
JPH0493041A (ja) 1990-08-08 1992-03-25 Fujitsu Ltd 熱圧着方法
DE69117891T2 (de) 1990-11-20 1996-07-25 Sumitomo Electric Industries Verfahren zum Montieren von Halbleiterelementen
JPH0770565B2 (ja) 1990-12-17 1995-07-31 松下電器産業株式会社 部品のフィルムキャリアへの接合装置
US5148968A (en) * 1991-02-11 1992-09-22 Motorola, Inc. Solder bump stretch device
JP2890335B2 (ja) * 1991-07-15 1999-05-10 株式会社新川 テープクランプ機構
JPH05144870A (ja) 1991-11-19 1993-06-11 Fujitsu Ltd バンプ転写方法
JP3423727B2 (ja) 1992-01-16 2003-07-07 富士通株式会社 フリップチップ接合方法
US5346857A (en) 1992-09-28 1994-09-13 Motorola, Inc. Method for forming a flip-chip bond from a gold-tin eutectic
US5397423A (en) * 1993-05-28 1995-03-14 Kulicke & Soffa Industries Multi-head die bonding system
JP3331570B2 (ja) 1993-09-08 2002-10-07 ソニー株式会社 熱圧着装置と熱圧着方法および液晶表示装置の生産方法
US5385291A (en) * 1994-01-10 1995-01-31 Micron Custom Manufacturing Services, Inc. Method employing an elevating of atmospheric pressure during the heating and/or cooling phases of ball grid array (BGA) soldering of an IC device to a PCB
US5441195A (en) * 1994-01-13 1995-08-15 Unisys Corporation Method of stretching solder joints
US5435482A (en) 1994-02-04 1995-07-25 Lsi Logic Corporation Integrated circuit having a coplanar solder ball contact array
JP3393562B2 (ja) 1994-05-13 2003-04-07 ソニー株式会社 熱圧着装置
JPH0832296A (ja) 1994-07-11 1996-02-02 Ibiden Co Ltd 電子部品を実装する際の位置合わせ方法
JP3348528B2 (ja) 1994-07-20 2002-11-20 富士通株式会社 半導体装置の製造方法と半導体装置及び電子回路装置の製造方法と電子回路装置
JP2774068B2 (ja) 1994-08-19 1998-07-09 光洋産業株式会社 集合体の熱圧成形方法
US5632434A (en) 1995-06-29 1997-05-27 Regents Of The University Of California Pressure activated diaphragm bonder
KR0152607B1 (ko) * 1995-08-17 1998-12-01 김주용 윈도우 클램프 및 그를 이용한 리드 프레임 스트립의 정렬방법
US5639696A (en) * 1996-01-31 1997-06-17 Lsi Logic Corporation Microelectronic integrated circuit mounted on circuit board with solder column grid array interconnection, and method of fabricating the solder column grid array
JP3330037B2 (ja) 1996-11-29 2002-09-30 富士通株式会社 チップ部品の接合方法および装置
US6068174A (en) * 1996-12-13 2000-05-30 Micro)N Technology, Inc. Device and method for clamping and wire-bonding the leads of a lead frame one set at a time
JP3094948B2 (ja) * 1997-05-26 2000-10-03 日本電気株式会社 半導体素子搭載用回路基板とその半導体素子との接続方法
US7654432B2 (en) 1997-05-27 2010-02-02 Wstp, Llc Forming solder balls on substrates
US5984166A (en) * 1997-07-09 1999-11-16 Mask Technology, Inc. Process for creating fine and coarse pitch solder deposits on printed ciruit boards
US5968670A (en) * 1997-08-12 1999-10-19 International Business Machines Corporation Enhanced ceramic ball grid array using in-situ solder stretch with spring
US5964396A (en) * 1997-08-12 1999-10-12 International Business Machines Corporation Enhanced ceramic ball grid array using in-situ solder stretch with clip
SE511873C2 (sv) 1997-08-27 1999-12-13 Akzo Nobel Nv Katjoniska sockertensider från etoxilerade ammoniumföreningar och reducerande sackarider samt användning därav som hydrotoper för tensider
JP2997231B2 (ja) * 1997-09-12 2000-01-11 富士通株式会社 マルチ半導体ベアチップ実装モジュールの製造方法
US6131795A (en) * 1997-11-10 2000-10-17 Matsushita Electric Industrial Co., Ltd. Thermal compression bonding method of electronic part with solder bump
JP2000036501A (ja) * 1998-05-12 2000-02-02 Sharp Corp ダイボンド装置
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
JP2000100837A (ja) * 1998-09-17 2000-04-07 Miyagi Oki Denki Kk 半導体素子の実装装置
EP1030349B2 (de) * 1999-01-07 2013-12-11 Kulicke & Soffa Die Bonding GmbH Verfahren und Vorrichtung zum Behandeln von auf einem Substrat angeordneten elektronischen Bauteilen, insbesondere von Halbleiterchips
AU7073100A (en) 1999-08-23 2001-03-19 Radiant Technology Corporation Continuous-conduction wafer bump reflow system
US6237832B1 (en) * 1999-10-18 2001-05-29 Henry Chung Wave soldering fixture
US6796481B2 (en) 2000-01-14 2004-09-28 Toray Engineering Co., Ltd. Chip mounting method
US6186392B1 (en) 2000-01-21 2001-02-13 Micron Technology, Inc. Method and system for forming contacts on a semiconductor component by aligning and attaching ferromagnetic balls
JP2002002649A (ja) 2000-06-27 2002-01-09 Hokkai Can Co Ltd ポリエチレンテレフタレート樹脂製容器
JP4194227B2 (ja) 2000-06-30 2008-12-10 芝浦メカトロニクス株式会社 電子部品の熱圧着装置
US6666368B2 (en) * 2000-11-10 2003-12-23 Unitive Electronics, Inc. Methods and systems for positioning substrates using spring force of phase-changeable bumps therebetween
JP2002158257A (ja) 2000-11-16 2002-05-31 Mitsubishi Electric Corp フリップチップボンディング方法
US6550665B1 (en) 2001-06-06 2003-04-22 Indigo Systems Corporation Method for electrically interconnecting large contact arrays using eutectic alloy bumping
TW508644B (en) * 2001-11-19 2002-11-01 Advanced Semiconductor Eng Die bonding device
US7235886B1 (en) 2001-12-21 2007-06-26 Intel Corporation Chip-join process to reduce elongation mismatch between the adherents and semiconductor package made thereby
US6871394B2 (en) 2002-01-31 2005-03-29 Texas Instruments Incorporated Method for aligning substrates in a tray
JP3809125B2 (ja) 2002-04-11 2006-08-16 新光電気工業株式会社 半導体チップボンディング用ヘッドおよび半導体チップボンディング方法
JP4334892B2 (ja) 2003-03-20 2009-09-30 パナソニック株式会社 部品実装方法
JPWO2004107432A1 (ja) 2003-05-29 2006-07-20 富士通株式会社 電子部品の実装方法、取外し方法及びその装置
US7077908B2 (en) 2003-05-30 2006-07-18 Matsushita Electric Industrial Co., Ltd. Substrate holder
JP3921459B2 (ja) * 2003-07-11 2007-05-30 ソニーケミカル＆インフォメーションデバイス株式会社 電気部品の実装方法及び実装装置
JP2005064205A (ja) 2003-08-11 2005-03-10 Niigata Seimitsu Kk 回路基板の移載装置および移載方法、半田ボール搭載方法
JP4206320B2 (ja) 2003-09-19 2009-01-07 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
TWI244419B (en) * 2003-09-25 2005-12-01 Unaxis Internat Tranding Ltd Wire bonder with a downholder for pressing the fingers of a system carrier onto a heating plate
JP3891297B2 (ja) * 2003-10-02 2007-03-14 セイコーエプソン株式会社 半導体装置製造用治具
US6942137B2 (en) * 2003-10-16 2005-09-13 International Business Machines Corporation Die removal method and apparatus
JP2005190601A (ja) 2003-12-26 2005-07-14 Hitachi Ltd 回転磁気ヘッド型記録再生装置
US6890795B1 (en) * 2003-12-30 2005-05-10 Agency For Science, Technology And Research Wafer level super stretch solder
US7357293B2 (en) 2004-03-24 2008-04-15 Intel Corporation Soldering an electronics package to a motherboard
US7257887B2 (en) 2004-06-14 2007-08-21 David Lee Die holding apparatus for bonding systems
DE102004034421A1 (de) 2004-07-15 2006-02-09 Pac Tech - Packaging Technologies Gmbh Verfahren und Vorrichtung zur wechselseitigen Kontaktierung von zwei Wafern
US7287685B2 (en) 2004-09-20 2007-10-30 International Business Machines Corporation Structure and method to gain substantial reliability improvements in lead-free BGAs assembled with lead-bearing solders
KR101253794B1 (ko) 2005-02-02 2013-04-12 데쿠세리아루즈 가부시키가이샤 전기 부품의 실장 장치
CN100536102C (zh) * 2005-03-28 2009-09-02 松下电器产业株式会社 倒装片安装体和倒装片安装方法及倒装片安装装置
JP4534062B2 (ja) 2005-04-19 2010-09-01 ルネサスエレクトロニクス株式会社 半導体装置
US7370258B2 (en) * 2005-04-28 2008-05-06 Sandbridge Technologies Inc. Iterative concatenated convolutional Reed-Solomon decoding method
KR100634869B1 (ko) 2005-05-30 2006-10-17 삼성전자주식회사 멀티 다이 접착 장치
JP4539454B2 (ja) 2005-06-20 2010-09-08 パナソニック株式会社 電子部品の熱圧着ツールおよび電子部品の実装装置ならびに実装方法
US7135771B1 (en) * 2005-06-23 2006-11-14 Intel Corporation Self alignment features for an electronic assembly
US20070000592A1 (en) 2005-06-29 2007-01-04 Intel Corporation Apparatus and method to operate on one or more attach sites in die package assembly
JP2007142097A (ja) * 2005-11-17 2007-06-07 Nec Electronics Corp 半導体装置
CN101317502B (zh) 2005-11-29 2011-02-16 松下电器产业株式会社 针对电路基板的操作装置和操作方法
US7470904B1 (en) 2006-03-20 2008-12-30 Flir Systems, Inc. Infrared camera packaging
JP4720608B2 (ja) 2006-05-10 2011-07-13 パナソニック株式会社 部品実装装置および部品実装方法
US7614538B2 (en) * 2006-05-15 2009-11-10 Kulicke And Soffa Industries, Inc. Device clamp for reducing oxidation in wire bonding
TWI322476B (en) * 2006-10-05 2010-03-21 Advanced Semiconductor Eng Die bonder and die bonding method thereof
JP4930049B2 (ja) * 2006-12-27 2012-05-09 富士通株式会社 高さ調節装置及び実装方法
US20090091025A1 (en) * 2007-10-04 2009-04-09 Agency For Science, Technology And Research Method for forming and releasing interconnects
JP5167779B2 (ja) 2007-11-16 2013-03-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2009141269A (ja) 2007-12-10 2009-06-25 Sony Chemical & Information Device Corp 電気部品の実装方法及び実装装置
JP5040746B2 (ja) * 2008-03-14 2012-10-03 日本電気株式会社 電子部品及びその製造方法
US8381965B2 (en) 2010-07-22 2013-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal compress bonding

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10223693A (ja) * 1997-02-12 1998-08-21 Toshiba Corp 電子部品実装方法および電子部品実装装置
US5975409A (en) * 1997-08-12 1999-11-02 International Business Machines Corporation Ceramic ball grid array using in-situ solder stretch
CN1451178A (zh) * 1999-10-26 2003-10-22 英特尔公司 改进的倒装芯片连接封装
CN1513206A (zh) * 2001-03-28 2004-07-14 ض� 无焊剂倒装芯片互连
CN1965401A (zh) * 2004-06-08 2007-05-16 松下电器产业株式会社 元器件安装方法及元器件安装装置
CN1949469A (zh) * 2005-10-12 2007-04-18 恩益禧电子股份有限公司 在布线板上贴装半导体器件以确保其间不变间隙的焊接方法及其焊接装置

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI556373B (zh) * 2012-07-26 2016-11-01 台灣積體電路製造股份有限公司 用以加工半導體裝置的系統及用以加工半 導體裝置的方法
US9538582B2 (en) 2012-07-26 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control in the packaging of integrated circuits
US9888527B2 (en) 2012-07-26 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Systems for processing semiconductor devices, and methods of processing semiconductor devices
US10512124B2 (en) 2012-07-26 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control in the packaging of integrated circuits
US11432372B2 (en) 2012-07-26 2022-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control in the packaging of integrated circuits
CN107968065A (zh) * 2016-10-20 2018-04-27 矽品精密工业股份有限公司 电子构件的置放制程及其应用的承载治具
CN110164783A (zh) * 2018-02-13 2019-08-23 三星电子株式会社 用于回流的堆叠工具以及包括该堆叠工具的回流装置
CN110164783B (zh) * 2018-02-13 2024-04-09 三星电子株式会社 用于回流的堆叠工具以及包括该堆叠工具的回流装置
CN110729217A (zh) * 2019-10-22 2020-01-24 江苏佳晟精密设备科技有限公司 一种安装半导体芯片的装置
CN112201585A (zh) * 2020-06-29 2021-01-08 深圳卓橙科技有限公司 一种融合smt的mcm集成电路封装方法
CN112201585B (zh) * 2020-06-29 2022-04-22 深圳市伟安特电子有限公司 一种融合smt的mcm集成电路封装方法

Also Published As

Publication number Publication date
TWI445108B (zh) 2014-07-11
US20120111922A1 (en) 2012-05-10
TW201212135A (en) 2012-03-16
CN102386114B (zh) 2013-09-11
US8317077B2 (en) 2012-11-27
US8104666B1 (en) 2012-01-31

Similar Documents

Publication Publication Date Title
CN102386114B (zh) 芯片接合的方法
US5145099A (en) Method for combining die attach and lead bond in the assembly of a semiconductor package
KR101214336B1 (ko) 열압착 본딩
US10847504B2 (en) Micro-LED module and method for fabricating the same
KR101183824B1 (ko) 가열 결합 헤드를 사용하는 직접적인 다이 부착 방법
US5062565A (en) Method for combining die attach and wirebond in the assembly of a semiconductor package
CN102709203B (zh) 接合装置及接合方法
TWI467681B (zh) 半導體裝置之製造方法
US8012866B2 (en) Method of bonding semiconductor devices utilizing solder balls
KR101674397B1 (ko) 열압축 본딩 중에 다수의 반도체 디바이스들을 유지하기 위한 디바이스 및 본딩 방법
KR101638807B1 (ko) 다이 접합 중에 기판을 가열하기 위한 장치
JPH06151701A (ja) 半導体装置の製造方法
US20060011711A1 (en) Method of fabricating a semiconductor device and mounting equipment
US7259088B2 (en) Apparatus for singulating and bonding semiconductor chips, and method for the same
CN112289695A (zh) 一种用于多焊件自动共晶的通用共晶装置及共晶方法
CN103887219A (zh) 自对准拾取头和用于利用自对准拾取头制造装置的方法
CN105810594A (zh) 半导体器件的制造方法
US7981729B2 (en) Fabrication method of multi-chip stack structure
US11823920B2 (en) Apparatus for attaching semiconductor parts
JP2000349099A (ja) はんだ接合方法および、半導体装置の製造方法
CN102054658B (zh) 封装打线工艺的加热治具及其方法
CN110265312A (zh) 引线键合设备及操作方法
CN215919413U (zh) 一种激光锡箔焊接装置
KR20120054758A (ko) 반도체 패키지 제조용 칩 이송 장치
KR100706530B1 (ko) 반도체 패키지 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20130911

CF01 Termination of patent right due to non-payment of annual fee