CN102054658B - 封装打线工艺的加热治具及其方法 - Google Patents

封装打线工艺的加热治具及其方法 Download PDF

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CN102054658B
CN102054658B CN2009101979687A CN200910197968A CN102054658B CN 102054658 B CN102054658 B CN 102054658B CN 2009101979687 A CN2009101979687 A CN 2009101979687A CN 200910197968 A CN200910197968 A CN 200910197968A CN 102054658 B CN102054658 B CN 102054658B
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王德峻
吕岱烈
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Ase Assembly & Test (shanghai) Ltd
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Abstract

本发明公开一种封装打线工艺的加热治具及其方法，所述加热治具包含一承载块及一夹持块，其中所述夹持块用以夹持一封装载体，使所述封装载体被夹持于所述承载块与所述夹持块之间。所述夹持块设有至少一加热组件以加热所述封装载体的一第一区域至一第一温度；而所述封装载体的一第二区域则具有一第二温度，所述第二温度相对低于所述第一温度。因此，所述加热治具能使所述封装载体的第二区域上的芯片的焊垫硬度保持在适当的预定硬度值，以提高导线与焊垫之间的结合可靠度及结合良品率；并使得所述第一区域上的打线位置被加温，从而使导线容易接合。

Description

封装打线工艺的加热治具及其方法
【技术领域】
本发明是涉及一种封装打线工艺的加热治具及其方法，特别是涉及一种在打线接合程序期间用来临时性承载夹持及加热一封装载体的封装打线工艺的加热治具及其方法。
【背景技术】
半导体封装程序是用来提供一封装构造保护一半导体芯片，使半导体芯片在通电运作时能避免发生外力撞击、灰尘污染、受潮或氧化等问题，以便利用封装构造提升半导体芯片的使用可靠度及延长其使用寿命。在现有的半导体封装制造过程中，通常先取得半导体晶圆并对其进行晶圆测试，通过测试后的半导体晶圆接着会被切割成数个半导体芯片，而各半导体芯片随后将被黏固在导线架(leadframe)或基板(substrate)上，以进行打线接合(wirebonding)程序。最后，再利用封胶材料包覆半导体芯片、导线以及导线架或基板的部份表面，如此即可大致完成半导体封装构造的半成品。
请参照图1所示，其揭示一种现有导线架及其加热治具，其中一导线架11通常包括数个引脚111、一芯片承座112及数个支撑肋条(未绘示)，其中所述支撑肋条类似于所述引脚111的形状并用于连接支撑芯片承座112。所述导线架11整体主要由铜或铜合金等导电材料制成。每一所述引脚111具有一内引脚部111a及一外引脚部111b，所述内引脚部111a在其预定打线位置可能预先镀有镍、金、银、钯或其合金的薄层。所述芯片承座112用以承载一半导体芯片13，其中所述半导体芯片13的有源表面朝上并具有数个焊垫131。再者，所述导线架的加热治具是一加热块12，其上表面用以承载所述引脚111的内引脚部111a，且所述加热块12的上表面具有一凹陷部121，所述凹陷部121用以承载所述芯片承座112。利用所述加热块12本身内部的加热线圈或是外部附加的加热器，所述加热块12可以提供高温，以加热所述内引脚部111a。
请参照图1所示，在打线接合程序期间，首先提供热能至所述加热块12。接着，将所述导线架11放置到所述加热块12上，其中所述导线架11的芯片承座112上具有所述半导体芯片13。此时，利用所述加热块12加热所述导线架11的内引脚部111a。接着，利用数条导线14(如金线或铜线)电性连接所述半导体芯片13的焊垫131及对应的所述内引脚部111a，其中所述加热块12提供的高温即可增加所述内引脚部111a的温度，从而提高焊接所述导线14时的共晶效果，使所述导线14容易接合到所述内引脚部111a上。在完成打线后，将所述导线架11移离所述加热块12，并对所述导线架11进行封胶程序，以完成半导体封装构造的半成品。
然而，所述导线架的加热治具设计具有下述缺点：由于所述加热块12是一体成型制造的，因此在加热所述内引脚部111a的同时，也增加了所述芯片承座112的温度，并连带加热了所述半导体芯片13的焊垫131。以目前的晶圆制造技术而言，所述焊垫131通常为铝垫，其材质硬度原本就明显低于所述导线14的材质(如金或铜)硬度，而所述加热块12的高温却又连带造成所述焊垫131的材质硬度因受热而调降至一硬度更软的状态。结果，在所述导线14接合至所述焊垫131时，所述导线14的较高硬度可能产生过大的冲击作用力予所述焊垫131过软的表面，造成所述焊垫131的损坏，并可能影响所述导线14与焊垫131之间的结合可靠度及结合良品率(yield)。再者，所述内引脚部111a本身的材质(铜或铜合金)硬度或其上的薄层材质(镍、金、银、钯或其合金)硬度通常大于所述焊垫131的材质(铝)硬度，而两者的材质在加热后的硬度差异又被扩大。结果，由于所述导线14必需要依序焊接在不同硬度的表面上，因此打线机台的焊针(未绘示)必需适当以电脑控制成通过不同力道强度来将所述导线14焊接于所述内引脚部111a或所述焊垫131的表面上，如此也提高了焊针打线作业的参数控制难度，并可能影响所述导线14的打线质量。另外，若所述芯片承座112底面的温度超高，则可能会发生表面氧化现象，并形成一氧化层。此氧化层将导致封胶后的封胶材料与所述芯片承座112底面之间出现脱层缺陷，因而影响后续封胶的良品率。
另一方面，请参照图2所示，其揭示一种现有基板及其加热治具，其中一基板11’通常包括数个手指区111’及一芯片承载区112’。所述基板11’整体主要是一电路板构造。每一所述手指区111’具有数个焊垫111a’做为其预定打线位置，所述焊垫111a’的表面材质为铜或铜合金，且可能预先镀有镍、金、银、钯或其合金的薄层。所述芯片承载区112’用以承载一半导体芯片13，其中所述半导体芯片13的有源表面朝上并具有数个焊垫131。再者，所述基板的加热治具是一加热块12，其上表面用以承载所述手指区111’及芯片承载区112’。利用所述加热块12本身内部的加热线圈或是外部附加的加热器，所述加热块12可以提供高温，以加热所述手指区111’的焊垫111a’及所述芯片承载区112’上的半导体芯片13的焊垫131。然而，所述基板的加热治具的加热块12的一体成型设计同样容易过度加热所述半导体芯片13的焊垫131使其过度软化，因而在打线时造成所述焊垫131的损坏等缺点。
故，有必要提供一种封装打线工艺的加热治具及其加热方法，以解决现有技术所存在的问题。
【发明内容】
本发明的主要目的在于提供一种封装打线工艺的加热治具及其方法，其中夹持块设有加热组件以加热封装载体的第一区域至第一温度；同时，保持封装载体的第二区域具有相对较低的第二温度，因此夹持块的加热组件能使封装载体的第二区域上的芯片的焊垫硬度保持在适当的预定硬度值，以提高导线与焊垫之间的结合可靠度及结合良品率；并使得所述第一区域上的打线位置被加温，从而使导线容易接合，并相对降低焊针打线作业的参数控制难度及简化打线作业。
本发明的次要目的在于提供一种封装打线工艺的加热治具及其方法，其中利用导线电性连接第二区域上的半导体芯片的焊垫至第一区域的打线位置之前，另利用夹持块的加热组件的辐射热能来加热导线，以适当降低导线硬度，从而提高打线的结合可靠度及结合良品率。
为达成本发明的前述目的，本发明提供一种封装打线工艺的加热治具，其特征在于：所述加热治具包含一承载块及一夹持块，所述承载块用以承载一封装载体，所述封装载体具有一第一区域及一第二区域；所述夹持块用以夹持所述封装载体，使所述封装载体被夹持于所述承载块与所述夹持块之间，所述夹持块曝露所述第二区域及部分的第一区域以便于打线；其中所述夹持块设有至少一加热组件，以加热所述封装载体的第一区域至一第一温度，而所述封装载体的第二区域则具有一第二温度，所述第二温度相对低于所述第一温度。
在本发明的一实施例中，所述封装载体是一导线架，所述第一区域为所述导线架的数个内引脚部，及所述第二区域为所述导线架的一芯片承座，所述芯片承座承载至少一半导体芯片。
在本发明的一实施例中，所述封装载体是一基板，所述第一区域为所述基板的一手指区，及所述第二区域为所述基板的一芯片承载区，所述芯片承载区承载至少一半导体芯片。
在本发明的一实施例中，所述承载块具有一凹陷部，所述导线架的芯片承座设置于所述凹陷部内，且所述芯片承座底面放置于所述凹陷部的内底面。
在本发明的一实施例中，所述半导体芯片的焊垫的表面材质硬度低于所述打线所用的导线的材质硬度。
在本发明的一实施例中，所述半导体芯片的焊垫为铝垫；及所述导线为金线或铜线。
在本发明的一实施例中，所述夹持块于与所述封装载体的接触面上另设有一高比热层，所述高比热层局部或全部的隔开所述夹持块与所述封装载体的接触面。
在本发明的一实施例中，所述封装载体的第一区域的第一温度为180-220℃；第二区域的第二温度为130-170℃。
再者，本发明提供另一种封装打线工艺的加热方法，其特征在于：提供一加热治具，所述加热治具包含一承载块及一夹持块，其中所述夹持块设有至少一加热组件；利用所述承载块承载一封装载体，及利用所述夹持块夹持所述封装载体，使所述封装载体被夹持于所述承载块与所述夹持块之间，其中所述封装载体具有一第一区域及一第二区域；利用所述夹持块的加热组件将所述封装载体的第一区域加热至一第一温度，而所述封装载体的第二区域则具有一第二温度，所述第二温度相对低于所述第一温度；及利用一导线电性连接所述第二区域上的一半导体芯片的一焊垫至所述第一区域的一打线位置。
在本发明的一实施例中，利用一导线电性连接所述第二区域上的一半导体芯片的一焊垫至所述第一区域的一打线位置之前，还包含：利用所述夹持块的加热组件加热一焊针上的导线。
【附图说明】
图1是一现有导线架及其加热治具的示意图。
图2是一现有基板及其加热治具的示意图。
图3A是本发明第一实施例封装打线工艺的加热治具的剖视图。
图3B是本发明第一实施例封装打线工艺的加热治具的上视图。
图4A是本发明第一实施例封装打线工艺的加热治具的使用示意图。
图4B是本发明第一实施例封装打线工艺的加热治具的另一使用示意图。
图5是本发明第一实施例半导体封装载体完成封装程序后的示意图。
图6是本发明第二实施例封装打线工艺的加热治具的剖视图。
图7是本发明第二实施例封装打线工艺的加热治具的使用示意图。
图8是本发明第二实施例半导体封装载体完成封装程序后的示意图。
【具体实施方式】
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下：
本发明提供的封装打线工艺的加热治具及其方法主要在打线接合程序期间用来临时性承载夹持及加热一导线架(leadframe)或基板(substrate)等封装载体，以提高打线接合的质量。
请参照图3A及3B所示，本发明第一实施例的封装打线工艺的加热治具2主要包含：一承载块21及一夹持块22。所述承载块21是由金属或塑胶等耐用材质所制成，例如可选自低比热的金属、耐高热的工程塑料或其它复合材料。所述承载块21的形状可以为板片状或块状；所述夹持块22是由金属或合金材质所制成，其材质可为铜、铁、铝、镍或其合金(如不锈钢)。所述夹持块22的形状可以为板片状或块状，并且优选的，所述夹持块22中央具有一中空的区域(未标示)。
所述承载块21用以承载一封装载体3，所述封装载体3具有一第一区域及一第二区域，并且所述夹持块22用以由上方夹持所述封装载体3，使所述封装载体3被夹持于所述承载块21与所述夹持块22之间。并且，所述夹持块22曝露所述第二区域及部分的第一区域，以便于后续进行打线程序。
在本实施例中，所述夹持块22在本身内部埋设至少一加热组件221，以提供热能至所述夹持块22。或者，所述夹持块22亦可在其外部的上表面或下表面附加有至少一加热器(未绘示)，以提供热能至所述夹持块22。在本实施例中，所述加热组件221是一长条状的加热线圈，所述加热组件221优选环绕所述夹持块22的中空区域的边缘设置于所述夹持块22内部(如图3B所示)。
所述封装载体3为导线架或导线架条(leadframe strip)，其中所述导线架条指的是具有数个导线架单元的金属条。在本实施例中，所述封装载体3以导线架为例通常包含有数个引脚31、一芯片承座32及数个支撑肋条(未绘示)，其中所述支撑肋条类似于所述引脚31的形状并用于连接支撑芯片承座32。所述封装载体3整体主要由铜或铜合金等导电金属材料制成。每一所述引脚31并具有一内引脚部311及一外引脚部312，其中所述第一区域即为所述内引脚部311，所述内引脚部311在其预定打线位置的表面可能预先镀有镍、金、银、钯或其合金的薄层。再者，所述芯片承座32为所述封装载体3的一第二区域，所述芯片承座32用以承载至少一半导体芯片4。
依所述导线架3的规格，所述承载块21可能具有一凹陷部211，以便使所述导线架3的芯片承座32设置于所述凹陷部211内，且所述芯片承座32底面放置于所述凹陷部211的内底面。
请再参照图3A所示，在本发明第一实施例中，依封装产品设计需求，所述封装载体3(导线架)的芯片承座32的高度可能低于或等于所述内引脚部311的高度。依所述封装载体3的高度设计，所述承载块21的凹陷部211区域的表面高度则可对应设计成低于或等于所述承载块21的上表面的高度。另外，所述半导体芯片4的一背面利用黏着剂黏固于所述封装载体3(导线架)的芯片承座32上，同时所述半导体芯片4的一有源表面朝上并具有数个焊垫41，其中所述焊垫41通常为铝垫。
请再参照图4A及4B所示，在本发明第一实施例的封装打线工艺的加热治具2用以进行打线接合程序。所述封装打线工艺的加热方法包含：
首先，提供一加热治具2，所述加热治具2包含一承载块2及一夹持块22，其中所述夹持块22设有至少一加热组件221；
接着，利用所述承载块21承载一封装载体3，及利用所述夹持块22夹持所述封装载体3，使所述封装载体3被夹持于所述承载块21与所述夹持块22之间，其中所述封装载体3具有一第一区域31及一第二区域32；将所述封装载体3(导线架)放置到所述承载块21上，其中所述封装载体3的芯片承座32上具有所述半导体芯片4。
利用所述夹持块22的加热组件221将所述封装载体3的第一区域(内引脚部311)加热至一第一温度，而所述封装载体3的第二区域32(导线架的芯片承座32)则具有一第二温度，所述第二温度相对低于所述第一温度，其中所述加热组件221可以依需求选择在所述封装载体3放置在所述承载块21上之前或之后开始加热动作；及
利用一导线5电性连接所述第二区域32上的一半导体芯片4的一焊垫41至所述第一区域的一打线位置(内引脚部311)。
在上述加热步骤中，本实施例利用内部埋设的加热组件221或外部附加的加热器(未绘示)提供热能至所述夹持块22，接着利用所述夹持块22的下表面加热所述封装载体3的内引脚部311(即第一区域)。在本实施例中，所述第一温度优选控制介于180至220℃之间，例如200℃；以及所述第二温度优选控制介于130至170℃之间，例如150℃，但实际应用时的温度及温度差可依打线位置(所述内引脚部311及焊垫41)的材质来调整，故并不限于此。
请再参照图4A及4B所示，图4A是将一导线5打线于所述半导体芯片4的焊垫41的示意图；图4B是将一导线5打线于所述封装载体3的内引脚部311的示意图。本发明可利用数条导线5电性连接所述半导体芯片4的焊垫41及对应的所述封装载体3的内引脚部311(即第一区域的打线位置)，其中所述导线5优选为金线或铜线。此时，所述半导体芯片4的焊垫41为第二温度。由于第二温度低于第一温度，因此所述半导体芯片4的焊垫41的表面材质(铝)硬度相对仅具有较小的软化程度，而所述封装载体3的内引脚部311的表面或薄层材质(铜、镍、金、银、钯或其合金)硬度相对具有较大的软化程度。如此，即可确保所述半导体芯片4的焊垫41的表面材质(铝)硬度不会过度软化。也就是，在所述导线5接合至所述焊垫41时，本发明即可减少所述导线5的较高材质硬度产生的冲击作用力损坏所述焊垫41表面的机率，因而相对提高所述导线5与焊垫41之间的结合可靠度及结合良品率。同时，亦可增加所述内引脚部311的温度，以提高焊接时的共晶效果，使所述导线5容易接合到所述内引脚部311上。再者，本发明更可通过控制所述第一及第二温度的温度差来造成不同的材质有适当的不同软化程度，因而可以抵销不同材质本身硬度上的差异，以维持所述半导体芯片4的焊垫41的表面材质(铝)硬度在可接受的硬度范围内。如此，打线机台的焊针(未绘示)可通过相同或近似的力道强度来将所述导线5焊接于所述内引脚部311或所述焊垫41的表面上，如此有利于降低焊针打线作业的参数控制难度及简化打线作业。
另外，本发明第一实施例利用一导线5电性连接所述第二区域上的一半导体芯片4的一焊垫41至所述第一区域的一打线位置之前，还包含：利用所述夹持块22的至少一加热组件221加热一焊针6上的导线5。所述夹持块22的至少一加热组件221的辐射热能可加热所述焊针6的导线5，因此可加热所述导线5来降低导线5的硬度。
最后，请参照图5所示，在完成打线后，将所述封装载体3(导线架)移离所述加热治具2，并利用一封胶材料6对所述封装载体3进行封胶程序，如此即可完成一半导体封装构造的半成品。值得注意的是，由于在上述打线期间所述第二区域没有被直接加热，可确保所述芯片承座32底面的温度不致超高，因此可避免所述芯片承座32底面发生表面氧化现象，故不会导致封胶时的封胶材料6与所述芯片承座32底面之间出现脱层缺陷，进而有利于确保封胶程序的良品率。
请参照图6、7及8所示，本发明第二实施例的封装打线工艺的加热治具相似于本发明第一实施例，并大致沿用相同图号，但第二实施例的差异特征在于：所述第二实施例的加热治具2是用来加热一封装载体3’，所述封装载体3’是一封装基板(substrate)。所述加热治具2的承载块21用以承载所述封装载体3’的一第一区域，以加热所述第一区域至一第一温度，其中所述第一区域为所述基板的一手指区31’，所述封装载体3’的一芯片承载区32’即为一第二区域。再者，因为所述封装载体3’(基板)是平板状，因此所述承载块21的表面高度一致且不需设置所述凹陷部211。
请再参照图7所示，在本发明第二实施例的封装打线工艺的加热治具2用以进行打线接合程序时，所述夹持块22同样利用内部埋设的加热组件221或外部附加的加热器(未绘示)提供热能至所述夹持块22，接着利用所述夹持块22的下表面加热所述封装载体3’(基板)的手指区31’(即第一区域)的数个焊垫311’至第一温度，以及同时所述封装载体3’的芯片承载区32’(即第二区域)为第二温度，所述第二温度相对低于所述第一温度。接着，在利用数条导线5电性连接所述半导体芯片4的焊垫41及对应的所述封装载体3’的焊垫311’时，可以确保所述半导体芯片4的焊垫41的表面材质(铝)硬度不会过度软化，故本发明即可减少所述导线5损坏所述焊垫41表面的机率，因而相对提高所述导线5与焊垫41之间的结合可靠度及结合良品率。
另外，在本发明第二实施例进行打线接合程序中，在利用一导线5电性连接所述第二区域上的一半导体芯片4的一焊垫41至所述第一区域的一打线位置(内引脚311或焊垫311’)之前，还包含：利用所述夹持块22的至少一加热组件221加热一焊针6上的导线5，所述加热组件221的辐射热能可加热所述焊针6的导线5，以使导线5温度不至于下降，因此有利于加热所述导线5来降低导线5的硬度，以便所述导线5进行打线作业。
再者，在本实施例中，所述夹持块22在与所述封装载体3的接触面上另设有一高比热层222，所述高比热层222是由酚醛塑料(bakelite)等高比热材料所制成。所述高比热层222局部或全部的隔开所述夹持块22与所述封装载体3的接触面。本发明可通过控制高比热层222的覆盖面积来控制对所述导线5与对所述封装载体3’的焊垫311’的加热比例，即可以用较多的辐射热能加热所述导线5，使所述导线5在相对较高温度下维持适当软化加热程度，同时用较少的传导热能来加热所述封装载体3’的焊垫311，使所述焊垫311也在相对较低温度下维持适当软化加热程度。或者，通过改变所述承载块21的材质来控制第二温度，即改变所述承载块21将热能传导至所述半导体芯片4的焊垫41的效率。
所述夹持块22利用内部埋设的加热组件221或外部附加的加热器(未绘示)提供热能所产生的第一及第二温度的温度差用以造成不同的材质有适当的不同软化程度，使得所述半导体芯片4的焊垫41的表面材质(铝)硬度能在打线接合期间维持在近似于所述第一区域的(即手指区31’的焊垫311’打线位置)的表面材质硬度。如此，打线机台的焊针(未绘示)可通过相同或近似的力道强度来将所述导线5焊接于所述焊垫311’或所述焊垫41的表面上，如此有利于降低焊针打线作业的参数控制难度及简化打线作业。最后，请参照图8所示，在完成打线后，将所述封装载体3’(基板)移离所述加热治具2，并利用一封胶材料6对所述封装载体3’进行封胶程序，而所述封装载体3’的底表面也可结合数个焊球33’，如此即可完成一半导体封装构造的半成品。
如上所述，相较于图1及2的现有加热治具的加热块12的一体成型设计容易过度加热所述半导体芯片13的焊垫131使其过度软化，因而在打线时造成所述焊垫131的损坏等缺点，图3至8的本发明的封装打线工艺的加热治具2包含一承载块21及一夹持块22，其中一封装载体3被夹持于所述承载块21与所述夹持块22之间。所述夹持块22设有至少一加热组件221以加热所述封装载体3的一第一区域至一第一温度；而所述封装载体的一第二区域则具有一第二温度，所述第二温度相对低于所述第一温度。因此，所述加热治具2能使所述封装载体3的第二区域上的芯片4的焊垫41硬度保持在适当的预定硬度值，以提高导线5与焊垫41之间的结合可靠度及结合良品率；并使得所述第一区域上的打线位置被加温，从而使导线5容易接合。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反的，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (9)

1.一种封装打线工艺的加热治具，其特征在于：所述加热治具包含：
一承载块，所述承载块用以承载一封装载体，所述封装载体具有一第一区域及一第二区域；及
一夹持块，所述夹持块用以夹持所述封装载体，使所述封装载体被夹持于所述承载块与所述夹持块之间，所述夹持块曝露所述第二区域及部分的第一区域以便于打线；其中所述夹持块设有至少一加热组件，以加热所述封装载体的第一区域至180-220℃，而所述封装载体的第二区域温度为130-170℃。
2.如权利要求1所述的封装打线工艺的加热治具，其特征在于：所述封装载体是一导线架，所述第一区域为所述导线架的数个内引脚部，及所述第二区域为所述导线架的一芯片承座，所述芯片承座承载至少一半导体芯片。
3.如权利要求1所述的封装打线工艺的加热治具，其特征在于：所述封装载体是一基板，所述第一区域为所述基板的一手指区，及所述第二区域为所述基板的一芯片承载区，所述芯片承载区承载至少一半导体芯片。
4.如权利要求2所述的封装打线工艺的加热治具，其特征在于：所述承载块具有一凹陷部，所述导线架的芯片承座设置于所述凹陷部内，且所述芯片承座底面放置于所述凹陷部的内底面。
5.如权利要求2或3所述的封装打线工艺的加热治具，其特征在于：所述半导体芯片的焊垫的表面材质硬度低于所述打线所用的导线的材质硬度。
6.如权利要求5所述的封装打线工艺的加热治具，其特征在于：所述半导体芯片的焊垫为铝垫；及所述导线为金线或铜线。
7.如权利要求1所述的封装打线工艺的加热治具，其特征在于：所述夹持块于与所述封装载体的接触面上另设有一酚醛塑料层，所述酚醛塑料层局部或全部的隔开所述夹持块与所述封装载体的接触面。
8.一种封装打线工艺的加热方法，其特征在于：所述加热方法包含：
提供一加热治具，所述加热治具包含一承载块及一夹持块，其中所述夹持块设有至少一加热组件；
利用所述承载块承载一封装载体，及利用所述夹持块夹持所述封装载体，使所述封装载体被夹持于所述承载块与所述夹持块之间，其中所述封装载体具有一第一区域及一第二区域；
利用所述夹持块的加热组件将所述封装载体的第一区域加热至180-220℃，而所述封装载体的第二区域温度为130-170℃；及
利用一导线电性连接所述第二区域上的一半导体芯片的一焊垫至所述第一区域的一打线位置。
9.如权利要求8所述的封装打线工艺的加热方法，其特征在于：利用一导线电性连接所述第二区域上的一半导体芯片的一焊垫至所述第一区域的一打线位置之前，还包含：利用所述夹持块的加热组件加热一焊针上的导线。
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