CN102136442B - 半导体封装打线工艺的加热装置及其夹具 - Google Patents

半导体封装打线工艺的加热装置及其夹具 Download PDF

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CN102136442B
CN102136442B CN2010100231648A CN201010023164A CN102136442B CN 102136442 B CN102136442 B CN 102136442B CN 2010100231648 A CN2010100231648 A CN 2010100231648A CN 201010023164 A CN201010023164 A CN 201010023164A CN 102136442 B CN102136442 B CN 102136442B
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anchor clamps
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heat block
heater
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CN102136442A (zh
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刘怡
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Ase Assembly & Test (shanghai) Ltd
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Abstract

本发明公开一种半导体封装打线工艺的加热装置及其夹具，所述加热装置包含一加热块及一夹具。所述加热块包含一凸出部，其凸设于所述加热块的上表面，用以承载一封装载体的一打线作业区；所述夹具位于所述加热块的上方，所述夹具用以夹持所述封装载体，将所述封装载体夹持定位于所述加热块与所述夹具之间。所述夹具包含一打线窗口及至少一个排气口。所述打线窗口暴露所述封装载体上的打线作业区；所述排气口设于所述打线窗口的至少一侧边。因此，所述加热装置能利用所述凸出部集中加热所述打线作业区，以减少其加热时间及防止过度加热造成打线位置表面金属氧化，以及可利用所述排气口来排除打线时产生的有机挥发气体以避免污染打线位置表面。

Description

半导体封装打线工艺的加热装置及其夹具
【技术领域】
本发明是涉及一种半导体封装打线工艺的加热装置及其夹具，特别是涉及一种能防止过度加热造成打线位置表面氧化及避免被有机挥发气体污染的半导体封装打线工艺的加热装置及其夹具。
【背景技术】
半导体封装程序是用来提供一封装构造保护一半导体芯片，使半导体芯片在通电运作时能避免发生外力撞击、灰尘污染、受潮或氧化等问题，以便利用封装构造提升半导体芯片的使用可靠度及延长其使用寿命。在现有的半导体封装制造过程中，通常先取得半导体晶圆并对其进行晶圆测试，通过测试后的半导体晶圆接着会被切割成数个半导体芯片，而各半导体芯片随后将被黏固在导线架(leadframe)或封装基板(substrate)上，以进行打线接合(wirebonding)程序。最后，再利用封胶材料包覆半导体芯片、导线以及导线架或封装基板的部份表面，如此即可大致完成半导体封装构造的半成品。
请参照图1所示，其揭示一种现有导线架及其加热装置，其中所述加热装置1主要包含：一加热块11及一夹具12。所述加热块11及所述夹具12是由金属或合金材质所制成，其材质可为铜、铁、铝、镍或其合金(如不锈钢)，所述加热块11的形状可以为板片状或块状；所述夹具12的形状可以为板片状或块状，并且优选的，所述夹具12中央具有一中空的打线窗口12a。
所述加热块11用以承载一导线架条2(leadframe strip)，所述导线架条2阵列排列有数个导线架单元，各导线架单元包含至少一芯片承座21及数个内引脚部22，所述芯片承座21承载至少一半导体芯片23，并且所述夹具12用以由上方夹持所述导线架条2，使所述导线架条2被夹持于所述加热块11与所述所述夹具12之间。并且，所述夹具12的打线窗口12a曝露所述半导体芯片23及所述数个内引脚部22，以便于后续进行打线程序。
请参照图1所示，在打线接合程序期间，首先利用所述加热块11本身内部的加热线圈(未绘示)或是外部附加的加热器(未绘示)提供热能至所述加热块11。接着，将所述导线架条2放置到所述加热块11上，其中所述导线架条2的各芯片承座21上具有所述半导体芯片23。此时，所述加热块11加热所述导线架条2的内引脚部22。接着，利用数条导线24(如金线或铜线)电性连接所述半导体芯片23的焊垫(未标示)及对应的所述内引脚部22，其中所述加热块11提供的高温即可增加所述内引脚部22的温度，从而提高焊接所述导线24时的共晶效果，使所述导线24容易接合到所述内引脚部22上。在完成打线后，使所述导线架条2向右移动一格，再次对下一导线架单元的内引脚部22进行打线。在完成所述导线架条2上所有导线架单元的内引脚部22的打线作业后，先将所述夹具12移开，再将所述导线架条2移离所述加热块11，切割所述导线架条2分离出数个导线架单元，并对各导线架单元进行封胶程序，以完成半导体封装构造的半成品。
然而，所述导线架条2的加热装置1的设计具有下述缺点：所述加热块11进行所述导线架条2的加热时，由于所述加热块11的上表面为一平坦的表面，因此所述加热块11与所述导线架条2的接触面积包含整个所述加热块11的上表面，所述加热块11的一部份热能会被所述导线架条2不需打线的周边区域(如左方尚未打线的下一导线架单元的内引脚部22及芯片承座21，或右方已完成打线的前一导线架单元的内引脚部22及芯片承座21)所吸收，因此造成所述夹具12的打线窗口12a内的内引脚部22需要较长的加热时间才会达到所需打线温度。然而，过长的加热时间却又可能造成周边区域(如左方尚未打线的下一导线架单元，或右方已完成打线的前一导线架单元)的所述内引脚部22及芯片承座21长期处于高温环境，因此可能会发生周边区域的所述内引脚部22的打线位置表面(及所述芯片承座21的焊垫表面)发生氧化现象，而形成一氧化层。此氧化层将导致打线位置表面与所述导线24的接合性质降低，或是可能造成封胶后的封胶材料与所述芯片承座21(或所述内引脚部22)表面之间出现脱层缺陷，因而影响后续封胶的良品率。再者，由于所述导线架2与所述半导体芯片23之间多以液态胶或胶带(未标示)来粘着结合，因此在上述加温期间将会排出有机挥发气体，而现有的加热装置1只有在中央处具有所述打线窗口12a，无法快速有效的排除这些有机挥发气体，因而可能造成有机挥发气体再次固化成固态微粒而污染所述内引脚部22的打线位置表面(及所述芯片承座21的焊垫表面)，进而导致打线位置表面与所述导线24的接合性质降低。
另外，请再参照图2所示，其揭示一种现有封装基板及其加热装置。其中所述加热装置1主要包含与图1相同的一加热块11及一夹具12。所述加热块11用以承载一封装基板条3(substrate strip)，所述封装基板3阵列排列有数个封装基板单元，各封装基板单元包含至少一芯片承载区31及至少一手指区32，所述芯片承载区31承载至少一半导体芯片33，并且所述夹具12用以由上方夹持所述封装基板条3，使所述封装基板条3被夹持于所述加热块11与所述所述夹具12之间。并且，所述夹具12的打线窗口12a曝露所述半导体芯片33及所述手指区32，以便于后续进行打线程序。
其中，所述封装基板条3整体主要是一电路板构造。每一封装基板单元的所述手指区32具有数个焊垫(未标示)做为其预定打线位置，所述焊垫的表面材质为铜或铜合金，且可能预先镀有镍、金、银、钯或其合金的薄层。所述芯片承载区31用以承载所述半导体芯片33，其中所述半导体芯片33的有源表面朝上并具有数个焊垫(未标示)。利用所述加热块11本身内部的加热线圈(未绘示)或是外部附加的加热器(未绘示)，所述加热块11可以提供高温以加热所述手指区32的焊垫及所述芯片承载区31上的半导体芯片33的焊垫。然而，所述封装基板的加热装置1的加热块11的上表面平坦的设计同样容易过度加热使周边区域(如左方尚未打线的下一封装基板单元，或右方已完成打线的前一封装基板单元)的所述手指区32的焊垫表面(及所述半导体芯片33的焊垫表面)金属氧化，进而影响打线位置表面与所述导线34的接合性质降低、后续封胶的良品率，以及同样会发生有机挥发气体造成焊垫表面污染的问题。
故，有必要提供一种半导体封装打线工艺的加热装置及其夹具，以解决现有技术所存在的问题。
【发明内容】
本发明的主要目的在于提供一种半导体封装打线工艺的加热装置的夹具，其中一夹具包含一打线窗口及至少一个排气口，所述打线窗口曝露一封装载体的一打线作业区；所述至少一个排气口设于所述打线窗口的至少一侧边。因此，有助于即时排除打线时产生的有机挥发气体以减少有机挥发气体污染打线位置表面，进而提升打线接合的质量及接合强度。
本发明的次要目的在于提供一种半导体封装打线工艺的加热装置，其中所述一加热块包含一凸出部凸设于其上表面，用以承载一封装载体的一打线作业区，所述凸出部能集中加热所述打线作业区并相对减少加热时间，以利控制所述打线作业区的加热温度及防止过度加热造成周边区域打线位置表面的金属氧化，因此有利于提升打线接合的质量及接合强度。
为达成本发明的前述目的，本发明提供一种半导体封装打线工艺的加热装置的夹具，其设于一加热装置的一加热块的上方，所述加热块用以承载一封装载体，所述夹具用以夹持所述封装载体，将所述封装载体夹持定位于所述加热块与所述夹具之间，其特征在于：所述夹具包含：一打线窗口，曝露所述封装载体上的一打线作业区；及至少一个排气口，设于所述打线窗口的至少一侧边。
在本发明的一实施例中，所述加热块另包含一凸出部，其凸设于所述加热块的上表面，所述凸出部用以承载所述封装载体的打线作业区。
在本发明的一实施例中，所述加热块另包含至少一真空吸孔，所述至少一真空吸孔贯穿形成于所述凸出部的上表面及所述加热块的下表面之间。
在本发明的一实施例中，所述封装载体是一导线架条，其阵列排列有数个所述打线作业区，所述打线作业区各包含至少一芯片承座及数个内引脚部，所述芯片承座承载至少一半导体芯片，以及所述夹具的打线窗口及排气口分别曝露一个所述打线作业区以及与前述打线作业区相邻的至少一个所述打线作业区。
在本发明的一实施例中，所述封装载体是一封装基板条，其阵列排列有数个所述打线作业区，所述打线作业区各包含至少一芯片承载区及至少一手指区，所述芯片承载区承载至少一半导体芯片，以及所述夹具的打线窗口及排气口分别曝露一个所述打线作业区以及与前述打线作业区相邻的至少一个所述打线作业区。
再者，本发明另提供一半导体封装打线工艺的加热装置，其特征在于：所述加热装置包含：一加热块，包含一凸出部，所述凸出部凸设于所述加热块的上表面，所述凸出部用以承载一封装载体的一打线作业区；以及，一夹具，位于所述加热块的上方，所述夹具用以夹持所述封装载体，将所述封装载体夹持定位于所述加热块与所述夹具之间，所述夹具包含：一打线窗口，曝露所述封装载体的打线作业区；及至少一个排气口，设于所述打线窗口的至少一侧边。
在本发明的一实施例中，所述夹具的排气口的上方另包含一吸气装置。
在本发明的一实施例中，所述排气口设于所述打线窗口的二侧边或四侧边。
【附图说明】
图1是一种现有导线架及其加热装置的示意图。
图2是一种现有封装基板及其加热装置的示意图。
图3是本发明第一实施例半导体封装打线工艺的加热装置的立体图。
图4是本发明第一实施例半导体封装打线工艺的加热装置的剖视图。
图5A是本发明第一实施例半导体封装打线工艺的加热装置的使用示意图。
图5B是本发明第一实施例半导体封装打线工艺的加热装置的另一使用示意图。
图6是本发明第一实施例半导体封装载体完成封装程序后的示意图。
图7是本发明第二实施例半导体封装打线工艺的加热装置的剖视图。
图8是本发明第二实施例半导体封装打线工艺的加热装置的使用示意图。
图9是本发明第二实施例半导体封装载体完成封装程序后的示意图。
【具体实施方式】
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下：
本发明提供的封装打线工艺的加热装置及其方法主要在打线接合程序期间用来临时性承载夹持及加热一导线架(leadframe)或封装基板(substrate)等封装载体，以提高打线接合的质量(quality)。
请参照图3所示，本发明第一实施例的半导体封装打线工艺的加热装置4主要包含：一加热块41及一夹具42。所述夹具42位于所述加热块41的上方，所述夹具42用以将一封装载体5夹持定位于所述加热块41与所述夹具42之间。特别说明的是，该封装载体5上优选是阵列排列有多个芯片承座(未标示)的导线架条(leadframe strip)或封装基板条(substrate strip)，该些芯片承座可以是单列的或多列的阵列排列，但本发明并不限制该封装载体5上芯片承座的排列方式及数量。
请参照图3所示，本发明第一实施例的加热块41是由金属或合金材质所制成，其材质可为铜、铁、铝、镍或其合金(如不锈钢)，所述加热块41的形状可以为板片状或块状。在本发明中，所述加热块41另包含一凸出部41a，所述凸出部41a凸设于所述加热块41的上表面，并可用以承载所述封装载体5的一打线作业区。所述加热块41另具有至少一真空吸孔41b，所述真空吸孔41b贯穿形成于所述凸出部41a的上表面及所述加热块41的下表面之间。本发明并不限制所述真空吸孔41b的数目，可依实际需要(如所述封装载体5的尺寸)来设计。
另外，请参照图3所示，本发明第一实施例的夹具42是由金属或合金材质所制成，其材质可为铜、铁、铝、镍或其合金(如不锈钢)，所述夹具42的形状可以为板片状或块状。所述夹具42包含一打线窗口42a及至少一个排气口42b，所述打线窗口42a大致设于所述夹具42中央，所述至少一个排气口42b设于所述打线窗口42a的侧边，例如设于其一侧边、二侧边或四侧边。本发明并不限制所述至少一个排气口42b的数目及排列方式，可依实际需要(如所述封装载体5的打线位置排列)来设计。再者，所述打线窗口42a优选设置于所述夹具42中央的一凹陷表面(未标示)处，及所述至少一个排气口42b设于所述凹陷部侧边且较所述凹陷表面为高的至少一个抬升表面(未标示)处。
请再参照图3及4所示，其揭示本发明第一实施例半导体封装打线工艺的加热装置的剖视图。在本实施例中，所述封装载体5为导线架或导线架条(leadframe strip)，其中所述导线架条指的是具有数个导线架单元的金属条。所述封装载体5以导线架条为例通常阵列排列有数个打线作业区5a，每一所述打线作业区5a阵列排列有至少一个导线架单元5b，各导线架单元5b包含有至少一芯片承座51、数个引脚(未标示)及数个支撑肋条(未绘示)，其中所述支撑肋条类似于所述引脚的形状并用于连接支撑芯片承座51。所述封装载体5整体主要由铜或铜合金等导电金属材料制成。每一所述引脚并具有一内引脚部52及一外引脚部(未标示)，所述内引脚部52在其预定打线位置的表面可能预先镀有镍、金、银、钯或其合金的薄层。再者，所述夹具42的所述打线窗口42a曝露所述封装载体5上的一个所述打线作业区5a，以便于后续进行打线程序。所述打线作业区5a包含了至少一所述芯片承座51及所述数个内引脚部52，所述芯片承座51承载所述至少一半导体芯片53，所述半导体芯片53的一有源表面朝上并具有数个焊垫(未标示)，并利用数条导线54(如金线或铜线)电性连接所述半导体芯片53的焊垫(未标示)及对应的所述内引脚部52。
在本实施例中，所述加热块41的凸出部41a用以承载所述封装载体5对应于所述凸出部41a位置的一个打线作业区5a。所述加热块41本身内部的加热线圈(未绘示)或是外部附加的加热器(未绘示)提供热能至所述加热块41。另外，所述半导体芯片53的一背面在打线之前已预先利用液态胶或胶带(未标示)来粘着固设于所述封装载体5(导线架条)的芯片承座51上。
请参照图5A及5B所示，在本发明第一实施例的半导体封装打线工艺的加热装置4用以进行打线接合程序。所述封装打线工艺的加热程序包含：
首先，请参照图5A所示，提供一加热装置4，所述加热装置4包含一加热块41及一夹具42，其中所述加热块41设有至少一加热组件(未绘示)，其可为内部埋设的加热组件或外部附加的加热器；所述加热组件主要用以对所述凸出部41a进行加热，其中所述加热组件较佳在所述封装载体5放置于所述加热块41上之前即预先开始加热动作。在本实施例中，加热温度优选控制介于180至220℃之间，例如200℃，但实际应用时的温度及温度差可依实际状况来调整，故并不限于此。
接着，请参照图3及5A所示，利用所述加热块41的凸出部41a承载一封装载体5对应于所述凸出部41a位置的一个打线作业区5a，及利用所述夹具42夹持所述封装载体5，使所述封装载体5夹持定位于所述加热块41与所述夹具42之间，其中所述封装载体5上阵列排列有数个打线作业区(5a，每一所述打线作业区5a包含至少一个导线架单元5b，各导线架单元5b包含了至少一所述芯片承座51及所述数个内引脚部52。所述芯片承座51承载所述至少一半导体芯片53，所述半导体芯片53的一有源表面朝上并具有数个焊垫(未标示)；其中，所述加热块41包含的凸出部41a凸设于所述加热块41的上表面，因此所述加热块41只有一小部份(即所述凸出部41a的上表面)与所述封装载体5的一个打线作业区5a的下表面接触，其余所述封装载体5的相邻打线作业区5a则与所述凸出部41a保持距离而未接触。所述夹具42的打线窗口42a及排气口42b分别曝露一个所述打线作业区5a以及与前述打线作业区5a相邻的至少一个所述打线作业区5a。再者，所述加热块41另包含贯穿所述加热块的至少一真空吸孔41b，所述至少一真空吸孔41可连接一外部的吸力装置(未绘示)，以产生一真空吸力，用以提供一暂时性的固定力来吸住所述封装载体5的下表面，以便将所述封装载体5暂时固定于所述加热装置4的所述加热块41上；其中所述加热组件也可能依需求选择在所述封装载体5放置于所述加热块41上之后才开始加热动作。由于所述加热装置4能利用所述凸出部41a集中加热所述打线作业区5a并相对减少加热时间，故可以控制所述打线作业区的加热温度及防止过度加热造成打线位置表面的金属氧化。
接着，请参照图3及5B所示，利用一焊针6上的导线54来进行打线作业，以电性连接所述半导体芯片53的一焊垫(未标示)至所述内引脚部52的上表面(即打线位置表面)。如此，即可完成一次打线作业，并且所述封装载体5将向图式的右方移动至下一打线位置。值得注意的是，在打线作业期间，所述加热块41只有一小部份(所述凸出部41a的上表面)与所述封装载体5的下表面接触，故可集中加热所述打线作业区5a并相对减少加热时间，同时也防止过度加热造成周边区域(如左方尚未打线的下一打线作业区5a的导线架单元5b，或右方已完成打线的前一打线作业区5a的导线架单元5b)的打线位置表面的金属氧化所衍生的各种问题。例如：上述打线期间，通过相对减少加热时间，可以相对降低周边区域打线位置表面的金属氧化机率，进而提升每一打线作业区5a的所述导线54与打线位置表面之间的打线接合质量及接合强度。再者，因为加热的接触面积变小了，故还能相对减少所述加热块41的加热组件的耗能。另外，在本发明中，由于所述夹具42的打线窗口42a侧边设置有所述至少一个排气口42b，因此所述导线架2与所述半导体芯片23之间胶体因温度升高而挥发产生的有机挥发气体，可通过所述夹具42的打线窗口42a及至少一个排气口42b加以迅速且即时的排除，以减少有机挥发气体污染打线位置表面的机率，进而提升打线接合的质量及接合强度。
最后，请参照图6所示，在完成打线作业后，先将所述夹具42移开，再将所述导线架5移离所述加热块41，并利用封胶材料7对所述导线架5进行封胶程序，以完成半导体封装构造的半成品。由于所述凸出部41a可集中加热所述打线作业区5a并相对减少加热时间，故所述芯片承座51下表面的温度不致过度加热所述芯片承座51，因此可避免所述芯片承座51下表面发生表面氧化现象，因此不会导致后续封胶时的封胶材料7与所述芯片承座51下表面之间出现脱层缺陷，进而有利于确保封胶程序的良品率。
请参照图7、8及9所示，本发明第二实施例的半导体封装打线工艺的加热装置相似于本发明第一实施例，并大致沿用相同图号，但第二实施例的差异特征在于：所述第二实施例的加热装置4是用来加热一封装载体5’，所述封装载体5’是一封装基板(substrate)或封装基板条(substrate strip)。所述封装载体5’以封装基板条为例通常阵列排列有数个打线作业区(未标示，請參考圖3所示)。所述加热装置4的加热块41用以承载所述封装载体5’，每一所述打线作业区(未标示)阵列排列有至少一个封装基板单元(未标示)，各封装基板单元包含了至少一芯片承载区51’及至少一手指区52’，所述芯片承载区51’承载至少一半导体芯片53’。
请再参照图8及9所示，在本发明第二实施例的半导体封装打线工艺的加热装置2用以进行打线接合程序时，所述加热块41同样利用内部埋设的加热组件(未绘示)或外部附加的加热器(未绘示)提供热能至所述加热块41的凸出部41a处，接着利用加热块41的凸出部41a的上表面加热所述封装载体5’(封装基板)的手指区52’的数个焊垫(未标示，即打线位置)。接着，利用一焊针6上的导线54’电性连接所述半导体芯片53’的焊垫(未标示)及对应的所述封装载体5’的手指区52’的焊垫，因此，上述打线期间，由于所述加热装置4的凸出部41a能集中加热对应所述凸出部41a的所述打线作业区并相对减少加热时间，以利控制所述打线作业区的加热温度，故所述手指区52’的数个焊垫及所述芯片承载区51’上的半导体芯片53’的焊垫等打线位置表面不会被长时间加热及其温度也不致过高，同时也可防止过度加热造成周边区域(如左方尚未打线的下一打线作业区的封装基板单元，或右方已完成打线的前一打线作业区的封装基板单元)的打线位置表面的金属氧化，进而提升打线接合的质量及接合强度。再者，也能同时避免所述芯片承载区51’下表面发生表面氧化现象，故不会导致封胶时的封胶材料7与所述芯片承载区51’下表面之间出现脱层缺陷，因此亦有利于确保封胶程序的良品率。另外，由于所述夹具42的打线窗口42a侧边所设置的所述至少一个排气口42b，因此，所述封装载体5’与所述半导体芯片53之间胶体因温度升高而挥发产生的有机挥发气体，可通过所述夹具42的打线窗口42a及至少一个排气口42b加以迅速且即时的排除，以减少有机挥发气体污染打线位置表面的机率，进而提升打线接合的质量及接合强度。最后，请参照图9所示，在完成打线后，先将所述夹具42移开，再将所述封装载体5’移离所述加热块41，并对所述封装载体5’进行封胶程序，以完成半导体封装构造的半成品。
再者，在本发明的另一实施例中，所述加热装置4的所述夹具42在所述排气口42b的上方的上方也可选择性的包含一吸气装置(未绘示)，例如一真空吸气装置，其用以主动式的辅助吸除有机挥发气体，以加速有机挥发气体的排散。再者，为了尽量减少上述打线位置发生氧化的风险，所述加热装置4亦可置于惰性气体(例如氮气)环境下来进行打线作业。
如上所述，相较于图1及2的现有加热装置的加热块11，由于所述加热块11与封装载体(所述导线架2或所述封装基板3)的接触面积过大，因此所述封装载体的打线位置表面过度加热，而发生表面氧化现象影响后续打线接合的良品率；且现有的加热装置1无法快速有效的排除有机挥发气体，因而造成线位置表面受到污染。图3至9的本发明的半导体封装打线工艺的加热装置4包含一加热块41及一夹具42，其中所述加热块41只有一小部份(即所述凸出部41a)与所述封装载体5、5’的下表面接触，因此在打线期间，能集中加热及相对减少加热时间，并防止过度加热造成周边区域打线位置表面金属氧化，进而有利于确保打线作业(及后续封胶程序)的良品率。再者，由于所述夹具42的打线窗口42a侧边设置有所述至少一个排气口42b，因此所述封装载体5与所述半导体芯片53之间胶体因温度升高而挥发产生的有机挥发气体亦可通过所述夹具42的打线窗口42a及至少一个排气口42b加以迅速且即时的排除，以减少有机挥发气体污染打线位置表面的机率，进而提升打线接合的质量及接合强度。。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反的，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (10)

1.一种半导体封装打线工艺的加热装置的夹具，其设于一加热装置的一加热块的上方，所述加热块用以承载一封装载体，所述夹具用以夹持所述封装载体，将所述封装载体夹持定位于所述加热块与所述夹具之间，其特征在于：所述夹具包含：
一打线窗口，设置于所述夹具中央的一凹陷表面，曝露所述封装载体上的一打线作业区；及
至少一个排气口，设于所述凹陷表面对应的凹陷部侧边且较所述凹陷表面为高的至少一个抬升表面。
2.如权利要求1所述的半导体封装打线工艺的加热装置的夹具，其特征在于：所述加热块另包含一凸出部，其凸设于所述加热块的上表面，所述凸出部用以承载所述封装载体的打线作业区。
3.如权利要求2所述的半导体封装打线工艺的加热装置的夹具，其特征在于：所述加热块另包含至少一真空吸孔，所述至少一真空吸孔贯穿形成于所述凸出部的上表面及所述加热块的下表面之间。
4.如权利要求1所述的半导体封装打线工艺的加热装置的夹具，其特征在于：所述封装载体是一导线架条，其阵列排列有数个所述打线作业区，所述打线作业区各包含至少一芯片承座及数个内引脚部，所述芯片承座承载至少一半导体芯片，以及所述夹具的打线窗口及排气口分别曝露一个所述打线作业区以及与前述打线作业区相邻的至少一个所述打线作业区。
5.如权利要求1所述的半导体封装打线工艺的加热装置的夹具，其特征在于：所述封装载体是一封装基板条，其阵列排列有数个所述打线作业区，所述打线作业区各包含至少一芯片承载区及至少一手指区，所述芯片承载区承载至少一半导体芯片，以及所述夹具的打线窗口及排气口分别曝露一个所述打线作业区以及与前述打线作业区相邻的至少一个所述打线作业区。
6.一种半导体封装打线工艺的加热装置，其特征在于：所述加热装置包含：一加热块，包含一凸出部，所述凸出部凸设于所述加热块的上表面，所述凸出部用以承载一封装载体的一打线作业区；以及一夹具，位于所述加热块的上方，所述夹具用以夹持所述封装载体，将所述封装载体夹持定位于所述加热块与所述夹具之间，所述夹具包含：
一打线窗口，设置于所述夹具中央的一凹陷表面，曝露所述封装载体的打线作业区；及
至少一个排气口，设于所述凹陷表面对应的凹陷部侧边且较所述凹陷表面为高的至少一个抬升表面。
7.如权利要求6所述的半导体封装打线工艺的加热装置，其特征在于：所述加热块另包含至少一真空吸孔，所述至少一真空吸孔贯穿形成于所述凸出部的上表面及所述加热块的下表面之间。
8.如权利要求6所述的半导体封装打线工艺的加热装置，其特征在于：所述封装载体是一导线架条，其阵列排列有数个所述打线作业区，所述打线作业区各包含至少一芯片承座及数个内引脚部，所述芯片承座承载至少一半导体芯片，以及所述夹具的打线窗口及排气口分别曝露一个所述打线作业区以及与前述打线作业区相邻的至少一个所述打线作业区。
9.如权利要求6所述的半导体封装打线工艺的加热装置，其特征在于：所述封装载体是一封装基板条，其阵列排列有数个所述打线作业区，所述打线作业区各包含至少一芯片承载区及至少一手指区，所述芯片承载区承载至少一半导体芯片，以及所述夹具的打线窗口及排气口分别曝露一个所述打线作业区以及与前述打线作业区相邻的至少一个所述打线作业区。
10.如权利要求6所述的半导体封装打线工艺的加热装置，其特征在于：所述夹具的排气口的上方另包含一吸气装置。
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