CN101894770A - 半导体封装打线表面的预氧化处理方法及其预氧化层结构 - Google Patents
半导体封装打线表面的预氧化处理方法及其预氧化层结构 Download PDFInfo
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Abstract
本发明公开一种半导体封装打线表面的预氧化处理方法及其预氧化层结构,所述预氧化处理方法包含以下步骤:提供一导线及一打线接合表面,所述导线的一端焊接结合于所述打线接合表面,形成一打线结合部;提供一氧化气体于所述打线结合部,使所述打线结合部上的所述打线接合表面及/或所述导线的表面形成一预氧化层;及利用一封胶材料封装所述导线、所述打线接合表面、所述预氧化层及所述打线结合部。由于所述打线接合表面及/或所述导线的表面具有所述预氧化层,因此当进行封装程序时,所述预氧化层可防止所述导线及/或打线接合表面进一步产生腐蚀现象,因而可减少封装程序中产生氧化缺陷的风险,以提高所述打线结合部的焊接质量,并且可有效提高半导体封装的良品率。
Description
【技术领域】
本发明涉及一种半导体封装打线表面的预氧化处理方法及其预氧化层结构,特别是涉及一种在半导体封装打线工艺中对于导线及/或打线接合表面进行预氧化处理的半导体封装打线表面的预氧化处理方法及其预氧化层结构。
【背景技术】
现有的半导体封装制造过程中,通常先取得半导体晶圆并对其进行晶圆测试,通过测试后的半导体晶圆接着会被切割成数个半导体芯片,而各半导体芯片随后将被黏固在导线架(leadframe)或基板(substrate)上,以进行打线接合(wire bonding)程序。打线接合(wire bonding)技术广泛地应用于半导体芯片与封装基板或导线架之间的电性连接上,以半导体芯片与导线架的电性连接为例,当导线架被移送至打线位置后,应用电子影像处理技术来确定芯片上各个接点以及每一接点所相对应的内引脚上接点的位置,然后做打线接合的动作,利用极细的导线(小于50微米)将芯片上的接点电性连接到导线架上之内引脚上。
接着,在上述现有的半导体封装打线工艺之后,再进行一半导体封装程序,其利用封胶材料包覆半导体芯片、导线以及导线架或基板的部份表面,其目的是提供一封装构造保护半导体芯片,来避免半导体芯片发生外力撞击、灰尘污染、受潮或氧化等问题,以便利用封装构造提升半导体芯片的使用可靠度及延长其使用寿命。
请参照图1A、1B及1C所示,其揭示一种现有的半导体封装打线工艺中的打线接合方法的流程示意图。当进行一芯片10与一导线架20打线接合时,以芯片10上的接点(焊垫)为第一焊接点11,以导线架20的内引脚上之接点为第二焊接点21。首先,如图1A所示,提供一焊针(capillary)30用以输出一导线31,以及提供一电子火焰点火杆(electronic flame off wand)(未绘示)用以在导线31的端部形成焊球(未标示),而后将焊球压焊在第一焊接点11上(此称为第一接合,first bond)。接着,如图1B所示,依照设计好之路径移动焊针30,最后焊针30将导线31压焊在第二焊接点21上(此称为第二接合,second bond)。接着,如图1C所示,以焊针30拉断在第二焊接点21处的导线31,从而完成一条导线31的打线接合动作。
请参照图2所示,其揭示一种现有的半导体封装打线工艺中的封装方法示意图。通过上述图1A至1C的打线接合方法后,所述导线架20承载固定所述芯片10,并通过多个导线31电性连结多个所述芯片10的第一焊接点11(芯片焊垫)及所述导线架20的第二焊接点21(内引脚上之接点),再以封胶材料P进行半导体封装程序,其完成品如图2所示。上述半导体封装程序使用的封胶材料P多为环氧树脂材料。
然而,在进行所述导线31的打线接合程序之后与进行封装程序之前后,所述导线31和所述焊接点11、12(芯片焊垫、内引脚之接点)是被暴露在一般环境中或密封在封胶材料P中,所述导线31和所述焊接点11、12(芯片焊垫、内引脚之接点)的表面可能因为空气及封胶材料P中的湿气或卤素离子导致的腐蚀反应,产生严重的缺陷。在进行封装程序时,所述导线31和所述焊接点11、12的腐蚀缺陷可能严重影响所述打线结合部的焊接质量(quality),并且使得半导体封装的良品率降低。即使未导致不良品,但半导体封装产品出厂后的使用可靠度与使用寿命仍旧会受到影响。
因此,有必要提供一种半导体封装打线表面的预氧化处理方法及其预氧化层结构,以解决现有技术所存在的问题。
【发明内容】
本发明的主要目的是提供一种半导体封装打线表面的预氧化处理方法及其预氧化层结构,通过提供氧化气体于打线结合部,使打线结合部上的打线接合表面及/或导线的表面形成一预氧化层。因此当进行封装程序时,预氧化层可防止导线及打线接合表面产生腐蚀现象,因而可减少封装程序中产生缺陷的风险,以提高打线结合部的焊接质量,并且可有效提高半导体封装的良品率。
为达上述目的,本发明提供一种半导体封装打线表面的预氧化处理方法,其用于半导体封装打线工艺,其特征在于:所述预氧化处理方法包含以下步骤:提供一导线及一打线接合表面,所述导线的一端焊接结合于所述打线接合表面,形成一打线结合部;提供一氧化气体于所述打线结合部,使所述打线结合部上的所述打线接合表面及所述导线的其中至少一个的表面形成一预氧化层;及利用一封胶材料封装所述导线、所述打线接合表面、所述预氧化层及所述打线结合部。
在本发明的一实施例中,所述氧化气体选自臭氧。
在本发明的一实施例中,在提供所述氧化气体的步骤中,是在一高温烘烤室中提供所述氧化气体于所述打线结合部,使所述打线接合表面及所述导线两者的表面皆形成所述预氧化层。
在本发明的一实施例中,在提供所述氧化气体的步骤中,通过一氧化气体注入系统局部供应所述氧化气体至所述打线接合表面或所述导线,使所述打线接合表面及所述导线的其中至少一个的表面形成所述预氧化层。
在本发明的一实施例中,所述导线的材质选自铜、铝或银;及所述打线接合表面的材质选自铜、铝或银。
在本发明的一实施例中,所述预氧化层的厚度介于10纳米至1000纳米之间。
为达上述目的,本发明另提供一种半导体封装打线表面的预氧化层结构,其用于半导体封装打线工艺,其特征在于:一导线的一端焊接结合于一打线接合表面形成一打线结合部,所述打线结合部上的所述打线接合表面及所述导线的其中至少一个的表面具有一预氧化层。
在本发明的一实施例中,所述导线的材质选自铜、铝或银;及所述打线接合表面的材质选自铜、铝或银。
【附图说明】
图1A~1C:现有的半导体封装打线工艺中的打线接合方法的流程示意图。
图2:现有的半导体封装打线工艺中的封装方法示意图。
图3A~3C:本发明第一实施例的一种半导体封装打线表面的预氧化处理方法中的打线接合(第一接合,first bond)示意图。
图4A~4C:本发明第一实施例的一种半导体封装打线表面的预氧化处理方法中的打线接合(第二接合,second bond)示意图。
图5A~5B:本发明第一实施例的一种半导体封装打线表面的预氧化处理方法中的预氧化处理示意图。
图6A~6B:本发明第一实施例的一种半导体封装打线表面的预氧化层结构的剖视图。
图7:本发明第一实施例的一种半导体封装打线表面的预氧化处理方法中的封装程序示意图。
图8:本发明第二实施例的一种半导体封装打线表面的预氧化处理方法中的预氧化处理示意图。
【具体实施方式】
为让本发明上述目的、特征及优点更明显易懂,下文特举本发明较佳实施例,并配合附图,作详细说明如下:
本发明第一实施例提供一种半导体封装打线表面的预氧化处理方法,其先进行二道打线接合,再进行预氧化处理,最后进行封装程序。请参照图3A至7所示,所述半导体封装打线表面的预氧化处理方法包含以下步骤:提供一导线40及一打线接合表面50、50’,所述导线40的一端焊接结合于所述打线接合表面50、50’,形成一打线结合部60、60’;提供一氧化气体G于所述打线结合部60、60’,使所述打线结合部60、60’上的所述打线接合表面50、50’及所述导线40的其中至少一个的表面形成一预氧化层S;以及,利用一封胶材料P封装所述导线40、所述打线接合表面50、50’、所述预氧化层S及所述打线结合部60、60’。
首先,请参照图3A、3B及3C所示,其揭示本发明第一实施例的一种半导体封装打线表面的预氧化处理方法中的打线接合(第一接合,first bond)示意图。如图3A所示,在本实施例中,所述第一接合动作的打线接合方法首先是:提供一焊针30及一邻接于所述焊针30的电子点火杆(未绘示),所述焊针30具有一供线孔(未标示),以输出所述导线40。所述导线40的材质可选自铜(Cu)、铝(Al)、银(Ag)或其合金线材等,但不限于此,一般所述导线40的直径是大于或等于20微米(μm)。
接着,本发明通过上述焊针30及电子点火杆使所述导线40的一端焊接于所述第一接合表面50。通过所述焊针30的供线孔输出所述导线40,所述导线40凸出所述焊针30的供线孔一长度。另外,所述第一接合表面50例如是一芯片的焊垫,但亦可能为导线架(leadframe)的内引脚或是基板(substrate)电路的接点。在本实施例中,所述第一接合表面50是一芯片的焊垫,所述焊垫的表面材质例如为铝,但并不限于此,例如亦可为铜或银等。
接着,如图3B所示,本发明通过所述电子点火杆(未绘示)的点火加热,使所述焊针30输出的导线40的端部熔结形成一焊球B,其中所述焊球B的直径至少大于所述导线40的最大外径。
最后,如图3C所示,本发明通过将所述焊针30下压,使所述导线40的一端,即所述焊球B焊接于所述第一接合表面50,并形成所述打线结合部60。
请再参照图4A、4B及4C所示,其揭示本发明第一实施例的一种半导体封装打线表面的预氧化处理方法中的打线接合(第二接合,second bond)示意图,在完成第一实施例的打线接合制造过程的第一接合动作后,依照设计好之移动路径,所述焊针30牵引所述导线40至第二接合的位置,通过另一打线接合方法使所述导线40的另一端焊接于所述第二接合表面50’,所述第二接合表面50’例如可以是导线架(leadframe)的内引脚或基板(substrate)电路的接点,但亦可能是芯片的焊垫,在本实施例中,所述第二接合表面50’是一导线架(leadframe)的内引脚。
如图4A、4B及4C所示,所述打线接合制造过程的第二接合的详细说明如下:首先,如图4A所示,本发明通过所述焊针30的供线孔继续输出所述导线40,并从第一接合的第一接合表面50(未绘示)牵引所述导线40,直到所述导线结构40到达所述第二接合表面50’上方为止。其中,所述第二接合表面60的材质例如为铜、锡、镍、铝、银或其合金,但并不限于此。
接着,如图4B所示,本发明通过将所述焊针30下压,而使所述焊针30的供线孔的所述导线40一小段焊接于所述第二接合表面50’。
最后,如图4C所示,本发明通过所述焊针30将所述导线40拉断,同时保留所述导线40的接点于所述第二接合表面50’上,如此即可完成打线接合制造过程的第二接合动作,并形成所述导线40的所述打线结合部60’。
请再参照图5A及5B所示,其揭示本发明第一实施例的一种半导体封装打线表面的预氧化处理方法中的预氧化处理示意图。在完成打线接合制造过程之后(如图5A),提供所述氧化气体G于所述打线结合部60、60’(如图5B),使所述打线结合部60、60’上的所述打线接合表面50、50’及所述导线40的其中至少一个的表面形成所述预氧化层S。在本发明中,所述氧化气体优选是选自臭氧(ozone gas),但本发明并不限于此。并且,在提供所述氧化气体的步骤中,优选是在一高温烘烤室中70(如图5B)中进行,通过高温可促进所述氧化气体G于所述打线结合部60、60’的氧化作用,使所述打线结合部60、60’的所述打线接合表面50、50’及所述导线40两者的表面皆形成所述预氧化层S,另外,通过高温条件而将打线完成的产品置于空气中,也可以作为一种加速氧化形成预氧化层的方法。
本发明针对所述预氧化层S进一步说明如下:请再参照图6A及6B所示,其揭示本发明第一实施例的一种半导体封装打线表面的预氧化层结构的剖视图。如图6A所示,其是经过预氧化处理方法后,在第一打线接合部60上所述导线40与所述打线接合表面50(例如芯片的焊垫)的表面产生所述预氧化层S的情形。所述导线40的一端焊接结合于所述打线接合表面50形成所打线结合部60,所述打线结合部60上的所述打线接合表面50及所述导线40的其中至少一个的表面具有一预氧化层S。
如图6B所示,其是经过预氧化处理方法后,在第二打线接合部60’上所述导线40与所述打线接合表面50’(例如导线架的内引脚)的表面产生所述预氧化层S的情形。所述导线40的一端焊接结合于所述打线接合表面50’形成所打线结合部60’,所述打线结合部60’上的所述打线接合表面50’及所述导线40的其中至少一个的表面具有一预氧化层S。
其中,所述导线40及/或所述打线接合表面50、50’的材质的材质选自铜(Cu)、铝(Al)或银(Ag)。而所述预氧化层的厚度优选介于10纳米至1000纳米之间,能具有较佳的保护效果。然而,所述氧化气体G对于不同金属材质所造成的氧化的反应顺位与反应速率也不同,其是取决于金属材质的氧化电位。举例来说,如图6A中,在一实施例中,若所述导线40材质例如为铜,所述打线接合表面50(芯片的焊垫)例如为铝,则铝质的所述打线接合表面50氧化的速率及程度较铜质的所述导线40为快,此时可能只有铝质的所述打线接合表面50氧化形成所述预氧化层S,或者处理时间较久的话,可能所述打线接合表面50及所述导线40两者皆氧化形成所述预氧化层S;又如图6B中,在另一实施方式中,若所述导线40材质例如为铝,所述打线接合表面50’(导线架的内引脚)例如为铜,则铝质的所述导线40氧化的速率及程度较铜质的所述打线接合表面50’为快,此时可能只有铝质的所述导线40氧化形成所述预氧化层S,或者处理时间较久的话,可能所述导线40及所述打线接合表面50’两者皆氧化形成所述预氧化层S。因此,本发明可通过对供应所述氧化气体G的参数控制(如时间或气体浓度控制),来控制使所述打线结合部60、60’上的所述打线接合表面50、50’及/或所述导线40的表面形成所述预氧化层S,或者两者皆形成所述预氧化层S。
最后,请再参照图7所示,其揭示本发明第一实施例的一种半导体封装打线表面的预氧化处理方法中的封装程序示意图。如图7所示,本发明最后利用一封胶材料P封装所述导线40、所述打线接合表面50、50’、所述预氧化层S及所述打线结合部60、60’,如此即可完成半导体封装打线工艺。
请参照图8所示,其揭示本发明第二实施例的一种半导体封装打线表面的预氧化处理方法中的预氧化处理示意图,本发明第二实施例的一种半导体封装打线表面的预氧化处理方法相似于本发明第一实施例,沿用相同的元件名称与标号,但其不同之处在于:本发明第二实施例在提供所述氧化气体G的步骤中,是通过管径较小的供气系统将所述氧化气体G注入系统局部供应所述氧化气体G至所述打线接合部60、60’,仅使所述打线接合部60、60’的其中一个的表面形成所述预氧化层S。
或者,透过更精细的供气系统使所述氧化气体G能局限于更小的范围,例如可单独针对所述打线结合部60、60’上的所述打线接合表面50、50’或所述导线40的其中一个的表面送供应所述氧化气体G以使所述打线接合表面50、50’及所述导线40两者的其中一个的表面形成所述预氧化层S。
综上所述,在现有的半导体封装制造过程中,在进行导线的打线接合程序之后与进行封装程序之前,导线和焊接点(芯片焊垫、内引脚之接点)是被暴露在一般环境中其的表面可能因为空气或封装材料中的湿气及卤素离子导致的腐蚀反应,产生严重的劣化现象,进而影响所述打线结合部的焊接质量。反观,如图3A至图8所示,本发明的一种半导体封装打线表面的预氧化处理方法及其预氧化层结构,通过提供所述氧化气体G于所述打线结合部60、60’,使所述打线结合部60、60’上的所述打线接合表面50、50’及所述导线40的表面形成所述预氧化层S。因此当进行封装程序时,所述预氧化层S是一致密的氧化层,其厚度介于10微米至1000微米之间,可防止所述导线40及/或所述打线接合表面50、50’的金属基材接触外部湿气及卤素离子,以避免两者的金属基材产生严重的劣化现象,因而能减少封装程序中产生缺陷的风险,提高打线所述结合部60、60’的焊接质量,并且可有效提高半导体封装的良品率。
本发明已由上述相关实施例加以描述,然而上述实施例仅为实施本发明的范例。必需指出的是,已公开的实施例并未限制本发明的范围。相反地,包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。
Claims (10)
1.一种半导体封装打线表面的预氧化处理方法,其用于半导体封装打线工艺,其特征在于:所述预氧化处理方法包含以下步骤:
提供一导线及一打线接合表面,所述导线的一端焊接结合于所述打线接合表面,形成一打线结合部;
提供一氧化气体于所述打线结合部,使所述打线结合部上的所述打线接合表面及所述导线的其中至少一个的表面形成一预氧化层;及
利用一封胶材料封装所述导线、所述打线接合表面、所述预氧化层及所述打线结合部。
2.如权利要求1所述的半导体封装打线表面的预氧化处理方法,其特征在于:所述氧化气体选自臭氧。
3.如权利要求1所述的半导体封装打线表面的预氧化处理方法,其特征在于:在提供所述氧化气体的步骤中,是在一高温烘烤室中提供所述氧化气体于所述打线结合部,使所述打线接合表面及所述导线两者的表面皆形成所述预氧化层。
4.如权利要求1所述的半导体封装打线表面的预氧化处理方法,其特征在于:在提供所述氧化气体的步骤中,通过一氧化气体注入系统局部供应所述氧化气体至所述打线接合表面或所述导线,使所述打线接合表面及所述导线的其中至少一个的表面形成所述预氧化层。
5.如权利要求1所述的半导体封装打线表面的预氧化处理方法,其特征在于:所述导线的材质选自铜、铝或银;及所述打线接合表面的材质选自铜、铝或银。
6.如权利要求1所述的半导体封装打线表面的预氧化处理方法,其特征在于:所述预氧化层的厚度介于10纳米至1000纳米之间。
7.一种半导体封装打线表面的预氧化层结构,其特征在于:一导线的一端焊接结合于一打线接合表面形成一打线结合部,所述打线结合部上的所述打线接合表面及所述导线的其中至少一个的表面具有一预氧化层。
8.如权利要求7所述的半导体封装打线表面的预氧化层结构,其特征在于:所述导线的材质选自铜、铝或银;及所述打线接合表面的材质选自铜、铝或银。
9.如权利要求7所述的半导体封装打线表面的预氧化层结构,其特征在于:所述预氧化层的厚度介于10纳米至1000纳米之间。
10.如权利要求7所述的半导体封装打线表面的预氧化层结构,其特征在于:所述打线接合表面及所述导线两者的表面皆形成所述预氧化层。
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CN109136825A (zh) * | 2018-11-09 | 2019-01-04 | 东北大学 | 一种利用预氧化提高Co-Al-W系高温合金抗热腐蚀性能的方法 |
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