CN1513206A - 无焊剂倒装芯片互连 - Google Patents

无焊剂倒装芯片互连 Download PDF

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CN1513206A
CN1513206A CNA028109333A CN02810933A CN1513206A CN 1513206 A CN1513206 A CN 1513206A CN A028109333 A CNA028109333 A CN A028109333A CN 02810933 A CN02810933 A CN 02810933A CN 1513206 A CN1513206 A CN 1513206A
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temperature
metal
chip
substrate
solder
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CN100440496C (zh
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J
J·库波塔
K·塔卡哈施
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Intel Corp
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Intel Corp
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Abstract

本发明描述了接合芯片与基片的倒装芯片方法。热压缩接合器被用来对准芯片与基片,并施加一个接触力以将基片上的焊料凸块与芯片上的金属凸块保持在一起。芯片由接合器头中的脉冲加热器从它的非工作面进行快速加热直至达到焊料凸块的回流温度为止。在接近达到焊料凸块的回流温度时,接触力被释放。焊料被保持在高于它的回流温度几秒钟,以利于基片的金属凸起物打湿和接合。由诸如钯等贵金属组成的金属帽被施加到金属凸块的表面,以防止金属凸块(它通常包括高导电的和高活性的金属,诸如铜)正好在回流操作之前和期间在高温下氧化。

Description

无焊剂倒装芯片互连
                     版权声明
这里包含的是受到版权保护的材料。版权拥有者不反对任何个人按照在专利和商标局专利文件或记录中所呈现的那样精确复制本专利公开的内容,在别的方面所有者保留对版权的一切权利。
                     发明背景
发明领域
本发明总的涉及半导体芯片封装领域。更具体地,本发明涉及通过使用倒装处理把半导体芯片与基片相接合。
相关技术描述
传统上,是将半导体芯片通过互连导线电连接到基片上的导电条上,此互连导线的一端被焊接在芯片的顶部区域,另一端焊接在包围芯片的基片的导电条焊盘上。这些类型的互连导线在空间上不太有效,因为需要有用于芯片的基底面和导电条焊盘周界的面积。为了更有效地利用基片表面和促进更小的芯片封装,曾经开发了倒装互连处理技术。基本上就是把半导体芯片的工作表面翻转成面向基片,并把芯片直接焊接到位于工作表面附近的导电条焊盘上。其结果能使封装更紧凑且空间利用更有效。
把翻转的芯片电连接到基片的一个最成功和有效的方法是利用可控塌陷芯片连接技术(C4)。图1显示C4处理过程。首先,如方块105所示,焊料凸块一般通过使用任何次数的适当处理(包括镀覆和汽相沉积)而被施加到基片的焊盘上。通常,使用具有低于200℃的熔点的铅锡焊料。接着,在方块110,通过把焊料凸块加热到焊料熔点以上的温度,使得焊料凸块回流,把焊料凸块充分打湿覆盖在它们的各自的焊盘。通常是把具有高铅含量的金属凸块或凸起物沉积在相应的芯片焊盘上。
在方块115,焊剂被施加到要被接合的至少一个表面上。通常,焊剂包括媒液(vehicle)和活化剂。焊剂媒液起到在第二次回流期间把焊料表面与大气隔离开的作用,使焊料很热和/或熔化时氧化的风险减到最小。焊剂媒液通常是发粘的,它提供接合力,以在第二次回流之前,把芯片与基片固定一起。活化剂通常是有机酸或无机酸,用来去除在焊料表面上存在的氧化物或表面薄膜,以利于焊料打湿要被接合的金属面。在方块120,芯片和基片的焊剂承载表面被放置成在大致对准地互相接触。
接着,如方块125所示,通过把芯片和基片封装加热到焊料熔点以上的温度而进行第二次回流。熔化的焊料凸块打湿相应的金属凸块,熔化的焊料的表面张力使得金属凸块自对准每个相应的基片焊盘。新形成的互连点然后被冷却,使得焊料凝固。
在方块130所示的去焊剂操作中,从芯片和基片封装上去除任何焊剂或焊剂残余物。这个操作通常包括用溶剂清洗该封装,以去除焊剂残余物。也可以规定一个互连后烘烤周期,以挥发任何剩余的溶剂或低沸点的焊剂成分。
环氧树脂底层填料被加到芯片的工作表面和基片的上表面之间以包围和支撑焊料互连。底层填料大大地增加了封装互连的可靠性和抗疲劳性。底层填料有助于发热诱发的应变所引起的应力分布更均匀,这种应变是由于在芯片与基片的整个表面上芯片与基片之间的热膨胀系数(CTE)的差别所造成的。如果在互连的芯片与基片之间的缝隙没有被底层填充,则应力将由相对较薄的焊料互连承载,这常常造成封装过早出现故障。然而,为了正确地执行底层填充,必须很好地接合芯片和基片表面。即使焊剂残余物的薄膜也会造成接合面的过早的层剥离,最后导致一个或多个互连故障。因此,使用C4技术的重大的挑战之一是从封装上完全去除所有的焊剂残余物。当芯片与基片之间的缝隙的厚度减小时,这变得特别麻烦。
总的生产时间(TPT),或制作一个焊接好的芯片所花费的时间,主要受从保护焊剂去除残余物(这是特别费时的)所需要时间的影响。例如,化学去焊剂可能花费几分钟,而后烘烤去除任何剩余的焊剂或溶剂残余物可能花费几小时。已开发了在高温下完全挥发的焊剂。然而,因为在C4处理过程中需要焊剂在回流之前把芯片和基片粘在一起,只有其挥发温度处在或高于焊料熔点的那些焊剂才适用于C4处理过程。然而,芯片与基片之间的缝隙厚度较薄与焊剂高的挥发温度一起,使得在回流处理过程期间,或在随后的以略低于焊料熔化温度的后烘烤操作中,通过沸腾去除所有的焊剂残余物成为很困难,甚至不可能。由于挥发焊剂需要很长的后烘烤时间和去焊剂操作,所以不可能大幅度降低TPT。
                     附图简述
在附图中以例子说明本发明,而不是只限于这些例子,在图上,相同的标号是指相似的元件,其中:
图1表示对于使用C4接合处理创建倒装接合一般所需要的操作的
现有技术方框图。
图2显示按照本发明的一个实施例所用的接合处理过程的方框图。
图3显示被施加到基片的粘接焊盘上并回流的焊料凸块,以及涂有贵金属帽的基于铜的金属凸块,此帽是加在芯片上表面的接合焊盘上。
图4a-c显示在互连处理过程期间进行各种操作时的芯片与基片。
图5提供在本发明的实施例中可利用的接合周期图。
图6A是芯片/基片的封装图,其中基片包含一个针栅阵列。
图6B是从实验中得出的图,表示按照本发明的实施例执行芯片互连处理过程期间,在芯片和基片上的几个位置所观察到的温度。
                     发明详细描述
本发明描述了不使用焊剂而把芯片互连到基片的倒装方法。通过使用热压缩接合器(或类似装备的设备),使焊料凸块在回流之前通过接触压力保持芯片和相关基片大致对准,因而在焊料凸块回流之前不必使用焊剂来把芯片与基片接合在一起。因此,通过在高温接合处理过程中使用抗氧化贵金属的金属帽来保护金属凸块(或凸起物),可以完全不使用焊剂。其优点是,通过消除费时的去焊剂和烘烤周期,TPT可以大大地减小。使用热压缩接合器来执行接合操作,与使用炉子提供用于焊料回流所必须的热量的现有技术的C4接合相比较,可进一步减小TPT。另外,有可能进一步增加芯片与基片表面的底层填充接合的整体性,以获得具有更高的抗疲劳性和更长的预期寿命的芯片封装。
图2是显示按照本发明的一个实施例所用的接合处理过程的方框图。首先,如方块205所示的,焊料通常被施加到基片的上表面的接合焊盘上,虽然在替换的实施例中,焊料也可以被施加到芯片(管心)的接合焊盘上。焊料可以通过使用本领域技术人员已知的任何数目的适当的技术(包括但不限于汽相沉积和电镀)被施加到接合焊盘上。在施加焊料后,基片被施加热到超过焊料的熔点,使得焊料回流(如方块210所示),以利于完全打湿接合焊盘。在优选实施例中,规定了具有约221℃的熔点的96.5%锡/3.5%银的易熔焊料,虽然也可以利用任何数目的适当的焊料混合物。最理想是无铅焊料,以消除由铅造成的潜在的环境问题。
通常,如方块215所示,金属凸块被施加到芯片的接合焊盘上,但在替换的实施例中,金属凸块也可被施加到基片上。金属凸块可以通过使用本领域技术人员已知的各种方法(包括但不限于,汽相沉积,镀覆和导线成块(wire bumping))被施加到接合焊盘上。最理想是选择具有良好电性能的凸块金属。传统上,在惯用的C4倒装接合处理过程中利用了抗氧化的、基于铅的凸块金属,诸如97%铅/3%锡合金。基于铅的凸块金属和使用该物质的焊料,在惯用的C4处理过程中,在加热炉温度逐渐上升和保持时间期间,可提供必要的抗氧化性,特别是在使用焊剂时。但是,以铅为主的凸块金属的电性能比较差,尚有很大的改进余地。在本发明的实施例中,逐渐上升和保持时间是相当短的(每秒逐渐上升100度以及1-5秒保持时间);因此,产生严重氧化的可能性非常之小,所以在金属凸块中可以利用具有极佳电性能的更具活性的底金属。在该优选实施例中,指明用铜基金属凸块。
为了帮助确保金属凸块表面在焊料回流和接合之前保持不被氧化,给金属凸块的接合面配上一个金属帽,如方块220所示。金属帽通常由在100到300℃的高温下具有良好的抗氧化性的金属或金属合金组成。合适的金属包括贵金属,诸如铂,铱,金和钯。最好金属还具有不错的电性能。金属帽可以通过使用本领域技术人员已知的多种方法(包括镀覆和汽相沉积)被施加到金属凸块上。图3显示被施加到基片315的接合焊盘310并被回流的焊料凸块305。也显示了被施加到芯片325的上表面的接合焊盘335的铜基底金属凸块320。金属凸块320在它的一部分表面覆盖以钯金属帽330,防止在芯片互连处理过程期间铜的氧化。
参照图2的方块225,芯片320由热压缩接合器头托起并与基片315对准。图4A上显示了与金属凸起物的芯片对准的带焊料凸起物的基片315。热压缩接合器是在芯片封装操作中经常使用的设备,它具有通过台板405和移动头410提供热和压力的能力。因为在本发明的优选实施例中,由热压缩接合器施加的压力被用来在回流之前使得芯片与基片保持在一起,所以,与现有技术的C4处理过程不同,不必采用焊剂来在回流之前使得芯片与基片保持在一起。在该优选实施例中,热压缩接合器的下部的台板405装备有台板加热器,这样,台板405可被保持在室温与焊料凸块的熔化温度之间的一个中间温度。在该优选实施例中,下部的台板405被保持在约135℃的温度。同样地,头部410可保持在一个中间温度,通常在30到100℃之间。头部410可包括内部加热元件,或如图4A所示利用能够快速加热(例如,大于每秒25℃)的脉冲加热工具415。
接着,在方块230,开始互连周期。首先,如图4B所示,让覆盖着芯片325的基底金属凸块320的帽金属与基片315的相应的焊料凸块305相接触,并施加压力。在方块235,脉冲加热工具415被快速地加热到远高于焊料凸块305的熔点的温度。图5显示在本发明的优选实施例中采用的接合周期。线540代表在该周期期间某个时间脉冲加热工具340的温度。线545是一条压力曲线,表示在某个时间施加到金属凸块与焊料凸块之间的交界面的力总量。如以上讨论的,开始时脉冲加热工具被保持在一个中间温度,例如30℃。芯片在时刻525由热压缩接合器头托起。芯片与基片对准,而且使芯片与基片相接触,并在时刻530左右施施加压力。通常,根据芯片的尺寸和要被作出的倒装连接的数目,施加2到5公斤的力。此后不久,脉冲加热工具被通电,并被快速加热到它的保持温度。在优选实施例中,规定了约100℃的加热速率。峰值保持温度515通常是约250到400℃,它取决于几个因素,包括芯片厚度,芯片的热传导率,以及焊料凸块305的熔点和想要的回流温度。通常,一个温度梯度将在芯片上形成,使得与焊料凸块305的交界面处的温度小于与脉冲加热工具415的交界面处的温度。因此,脉冲加热工具415的保持温度515通常大于焊料凸块305的回流温度。在时刻550或其前后,在芯片与基片之间的交界面处达到焊料的熔化温度,而且不再需要压力来将芯片与基片保持在一起,因为焊料凸块开始熔化并打湿金属凸块。因此,加到芯片的力被释放,使得施加的压力减小到零,正如压力曲线545所表示的。在脉冲加热工具保持在温度515时,焊料凸块成为完全熔化和回流。芯片上的金属凸块被打湿,连同熔化的焊料的表面张力一起,将有助于促进芯片与基片的自对准,其间芯片作小量必要的横向移动,使得所有的互连的平均有效表面张力最小。脉冲加热工具被保持在温度515很短的时间间隔,通常1到5秒,在这之后,脉冲加热工具340断电,焊料凸块很快地重新固化。一旦脉冲加热工具达到温度510(在该优选实施例中约为200℃)已接合的芯片与基片就从热压缩接合器处取下,让接合器空出来执行另一个芯片接合。图4C显示互连的芯片与基片,其中焊料凸块已变形并打湿了金属凸块的带帽的表面。
不像回流是在炉子中进行的C4那样,这里金属凸块和焊料被暴露在高温中的总的时间是非常短的。因此,对于优选的锡和银焊料凸块几乎没有时间发生严重的氧化。另外,在高的互连温度下,在抗氧化金属帽上不会形成阻止焊料打湿凸块金属的氧化物。
正如上面提到的,在优选实施例中,利用96.5%锡/3.5%银焊料来形成焊料凸块。这个焊料具有约221℃的熔点,需要至少比熔点大几度的回流温度。正如以上讨论的,诸如C4那样的现有技术方法通常利用基于铅的焊料(诸如37%铅63%锡),它具有小于190℃的熔点。较低的熔点的焊料当通过使用C4处理来把芯片接合到装有管脚的基片时是特别需要的,因为超过210℃的温度会造成管脚焊料的软化(典型的焊料是,95%锡5%锑,它在232℃左右开始熔化),导致管脚的移动。本发明的优选实施例中使用96.5%锡/3.5%银焊料,使管脚焊料的温度不超过200℃。在高端的芯片与脉冲加热工具交界面和低端的台板与基片交界面之间的温度梯度在脉冲加热工具通电的短时间内决没有机会达到平衡。图6A是芯片/基片封装图,其中基片包括针栅阵列(PGA)。PGA的管脚620通过管脚焊料620被固定就位。图6B是从实验中得出的图,表示在按照本发明的实施例执行的芯片接合期间,在芯片和基片上的几个位置观察到的温度。沿水平轴列出的温度表示在芯片接合区域605的中心处的温度。应当指出,优选的焊料的熔化和回流通常发生在220和225℃之间的温度。上部线表示在基片的针栅阵列面的中心处的相应温度。底部线表示在基片的针栅阵列列面的边缘处相应的温度。如图6B所示,在基片的针栅阵列面上的温度从未超过165℃,而同时达到和超过了焊料凸块的熔化温度,这有利于回流和接合。
回过来参照图2,在芯片与基片之间的缝隙通常以环氧树脂作底层填充,以便显著增加互连的耐久性,环境抵抗性,和疲劳强度,如方块240所示。使用现有的C4处理过程,在芯片与基片之间存在的任何焊剂残余物需要在去焊剂操作中被去除,这通常要用溶剂清洗。而且,也许要进行烘烤周期,来“烧掉”任何剩余的残余物。可以理解,执行这些操作要耗费大量的时间并大大增加芯片/基片互连的TPT。通过使用不用焊剂的本发明的优选实施方案,可以消除去焊剂和烘烤操作,从而可以大大地减小TPT。
替换实施例
在以上的描述中,为了说明起见而阐述了许多具体细节,以便对本发明有透彻的了解。详细的说明和这里讨论的实施例并不是要限制如权利要求所确定的本发明的范围。相反,权利要求的各种实施例包含着权利要求书语言的全部内容。因此,可以不用这里提供的某些具体的细节而实施本发明。
例如,以上主要藉助于使用热压缩接合器的倒装接合处理过程来描述本发明的实施例。可以想象到,可以使用其他设备来完成权利要求书的界定的内容,这对于本领域技术人员是显而易见的。同样,虽然该处理过程是藉助于使用96.5%锡/3.5%银焊料的示例性实施例来描述的,但可考虑有其他适用的焊料。在优选实施例中,一旦焊料凸块开始熔化,相对于基片施加到芯片的压力就被撤除,然而,可考虑有替换的实施例,其中在互连处理中至少保持对于芯片的某些压力。此外,在其他备选实施例中,可考虑把挥发温度低于焊料熔化温度的免清洗焊剂的薄涂层加到焊料凸块上,以便在加热期间从焊料凸块去除任何氧化物。免清洗焊剂在完成芯片接合之前被完全蒸发掉,因而不需要任何后续的去焊剂或烘烤操作。在至今为止描述的实施例中,金属凸块被施加到芯片表面上,而焊料凸块被施加到基片上,但是,也可以把金属和焊料凸块的放置颠倒过来。

Claims (23)

1.一种方法,包括:
把基片与相应的芯片对准,
基片具有相对的第一和第二基片表面,第一基片表面具有多个被附着在其上的焊料凸块,
焊料凸块具有熔化温度,
芯片具有相对的第一和第二芯片表面,第一芯片表面具有被附着在其上的金属凸起物,
金属凸起物至少部分地覆盖有金属帽,金属凸起物主要包括第一金属,金属帽主要包括第二金属;
使得多个焊料凸块与多个隆起金属凸起物互相接触;以及
把多个焊料凸块加热到大于熔化温度的第一温度,以熔化多个焊料凸块。
2.权利要求1的方法,其中使得多个焊料凸块与多个隆起金属凸起物互相接触还包括施加接触力。
3.权利要求2的方法,其中在所述把多个焊料凸块加热到第一温度期间,一旦多个焊料凸块开始熔化,接触力就被释放。
4.权利要求1的方法,其中把多个焊料凸块加热到第一温度包括通过把第二芯片表面固定装置快速加热到第二温度而产生在芯片上的温度梯度,第二温度比起第一温度大得多。
5.权利要求4的方法,其中完成所述快速加热第二芯片表面的热量是通过与第二芯片表面相接触的加热器而提供的。
6.权利要求4的方法,其中当多个焊料凸块处在第一温度时,在第二基片表面处的第三温度大大低于第一温度。
7.权利要求1的方法,还包括将多个焊料凸块在等于或大于第一温度的温度下保持一段时间。
8.权利要求1的方法,其中第二金属是在高温下抗氧化的金属或金属合金。
9.权利要求1的方法,其中多个焊料凸块由无铅焊料组成。
10.权利要求4的方法,其中快速加热第二芯片表面到第二温度是通过使用每秒超过50℃的加热速率完成的。
11.一种方法,包括:
把基片或芯片放置在第一固定装置中,
在基片或芯片上沉积多个焊料凸块,焊料凸块具有在第一温度的熔点,
第一固定装置被保持在低于第一温度的第二温度,
把基片或芯片的另一个放置在第二固定装置中,
在基片或芯片的另一个上附着多个主要由第一金属组成的金属凸起物,多个金属凸起物的每一个至少部分地覆盖有金属帽,金属帽主要包括第二金属;
通过使第一和第二固定装置之一或二者朝向彼此移动,而使得多个焊料凸块与多个隆起金属凸起物互相接触;
快速加热与第一或第二固定装置相连的加热器,从第三温度加热到第四温度,
第三温度低于第一温度,以及
第四温度高于第一温度;
将加热器保持在大约第四温度或高于第四温度下,直至多个焊料凸块熔化和打湿每个金属凸起物的金属帽的至少一部分为止。
12.权利要求11的方法,其中加热器以及第一和第二固定装置包括热压缩接合器。
13.权利要求11的方法,其中在基片上沉积多个焊料凸块,以及在芯片上附着多个金属凸起物。
14.权利要求11的方法,其中脉冲加热工具在大约1与5秒之间的一段时间内保持在第四温度。
15.权利要求11的方法,其中使得多个焊料凸块与多个金属凸起物互相接触还包括施加接触力,以使多个焊料凸块与多个金属凸起物保持互相接触。
16.接合芯片与基片的倒装芯片方法,包括:
把金属凸起物施加到芯片的工作表面上的电互连焊盘上,芯片具有与工作表面相对的第二表面,金属凸起物包括第一金属以及具有一表面,其中包括抗氧化金属或金属合金的金属帽覆盖该表面的至少一部分;
把无铅焊料凸块施加到基片的上表面上的电互连焊盘上,基片也具有与上表面相对的底部表面,焊料凸块具有熔化温度,熔化温度处在200-400℃的范围内;
把基片的底部表面放置在热压缩接合器的台板上,台板被保持在小于熔化温度的第一温度,第一温度处在70-190℃的范围内;
把芯片的第二表面附着到热压缩接合器的头部,头部包含一个加热器,该头部被保持在第二温度,第二温度低于120℃;
把焊料凸块大致对准相应的金属凸起物;
降低该头部或升高该台板,使得焊料凸块与金属凸起物相接触;
施加接触力,以将焊料凸块与相应的金属凸起物保持在一起;
快速增加加热器的温度到第三温度,直至基片的上表面达到第四温度为止,第三温度处在250-400℃的范围内,第四温度大于熔化温度;以及
将上表面在第四温度下保持一段时间。
17.权利要求16的方法,还包括在焊料凸块开始熔化后,但在这段时间间隔消逝之前,释放接触力。
18.权利要求16的方法,还包括:
在所述一段时间结束和焊料凸块固化之后,从热压缩接合器上取下互连的芯片与基片封装件。
19.权利要求16的方法,其中焊料凸块由基于锡主的焊料组成。
20.一种方法,包括:
把多个金属凸起物施加到芯片的芯片表面上,多个金属凸起物主要包括第一金属;以及
至少部分地用金属帽覆盖多个金属凸起物,金属帽主要包括第二金属。
21.权利要求20的方法,其中金属凸起物被施加到位于芯片表面上的电接合焊盘上。
22.权利要求20的方法,其中第二金属在175与250℃之间的高温下抗氧化。
23.权利要求20的方法,其中第一金属是铜。
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101573789A (zh) * 2006-12-28 2009-11-04 英特尔公司 包括其凸块形成位点上的焊料帽的微电子管芯及其制造方法
CN101993034A (zh) * 2010-11-03 2011-03-30 深港产学研基地 一种高洁净度mems器件气密封装方法
CN102386114A (zh) * 2010-09-01 2012-03-21 台湾积体电路制造股份有限公司 芯片接合的方法
CN103094139A (zh) * 2011-11-07 2013-05-08 矽品精密工业股份有限公司 覆晶接合方法
CN101965241B (zh) * 2008-11-21 2015-04-22 三菱重工业株式会社 晶片接合装置
CN104733414A (zh) * 2013-12-18 2015-06-24 相丰科技股份有限公司 芯片构件与芯片封装体
CN107919856A (zh) * 2016-10-06 2018-04-17 三菱电机株式会社 半导体装置
CN108511354A (zh) * 2017-02-27 2018-09-07 日月光半导体制造股份有限公司 半导体装置和其制造方法
CN112151398A (zh) * 2019-06-26 2020-12-29 上海微电子装备(集团)股份有限公司 一种芯片封装方法

Families Citing this family (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6666368B2 (en) * 2000-11-10 2003-12-23 Unitive Electronics, Inc. Methods and systems for positioning substrates using spring force of phase-changeable bumps therebetween
US6815324B2 (en) 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US7099293B2 (en) 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
US7235886B1 (en) 2001-12-21 2007-06-26 Intel Corporation Chip-join process to reduce elongation mismatch between the adherents and semiconductor package made thereby
US20030116860A1 (en) * 2001-12-21 2003-06-26 Biju Chandran Semiconductor package with low resistance package-to-die interconnect scheme for reduced die stresses
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
DE10238582B4 (de) * 2002-08-22 2006-01-19 Infineon Technologies Ag Verfahren zur Herstellung eines Verbundes aus einer getesteten integrierten Schaltung und einer elektrischen Einrichtung
US6854636B2 (en) * 2002-12-06 2005-02-15 International Business Machines Corporation Structure and method for lead free solder electronic package interconnections
US6870270B2 (en) * 2002-12-28 2005-03-22 Intel Corporation Method and structure for interfacing electronic devices
US7271497B2 (en) * 2003-03-10 2007-09-18 Fairchild Semiconductor Corporation Dual metal stud bumping for flip chip applications
US6943058B2 (en) * 2003-03-18 2005-09-13 Delphi Technologies, Inc. No-flow underfill process and material therefor
US6833289B2 (en) * 2003-05-12 2004-12-21 Intel Corporation Fluxless die-to-heat spreader bonding using thermal interface material
US20050003650A1 (en) 2003-07-02 2005-01-06 Shriram Ramanathan Three-dimensional stacked substrate arrangements
US20050003652A1 (en) * 2003-07-02 2005-01-06 Shriram Ramanathan Method and apparatus for low temperature copper to copper bonding
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US20060216860A1 (en) 2005-03-25 2006-09-28 Stats Chippac, Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US8216930B2 (en) 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
WO2005048311A2 (en) 2003-11-10 2005-05-26 Chippac, Inc. Bump-on-lead flip chip interconnection
US7736950B2 (en) * 2003-11-10 2010-06-15 Stats Chippac, Ltd. Flip chip interconnection
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
US8674500B2 (en) * 2003-12-31 2014-03-18 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8067837B2 (en) 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
US7223695B2 (en) * 2004-09-30 2007-05-29 Intel Corporation Methods to deposit metal alloy barrier layers
US8294279B2 (en) 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
JP4650220B2 (ja) * 2005-11-10 2011-03-16 パナソニック株式会社 電子部品の半田付け方法および電子部品の半田付け構造
US20070134844A1 (en) * 2005-12-13 2007-06-14 Shin-Etsu Chemical Co., Ltd. Process for producing flip-chip type semiconductor device and semiconductor device produced by the process
DE102006050653A1 (de) * 2006-10-24 2008-04-30 Carl Zeiss Smt Ag Verfahren und Vorrichtung zum stoffschlüssigen Verbinden eines optischen Elementes mit einer Fassung
US20080157910A1 (en) * 2006-12-29 2008-07-03 Park Chang-Min Amorphous soft magnetic layer for on-die inductively coupled wires
KR100790454B1 (ko) * 2007-02-09 2008-01-03 주식회사 하이닉스반도체 플립 칩 패키지
US20090233436A1 (en) * 2008-03-12 2009-09-17 Stats Chippac, Ltd. Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating
US8080884B2 (en) * 2008-06-27 2011-12-20 Panasonic Corporation Mounting structure and mounting method
TWI455263B (zh) * 2009-02-16 2014-10-01 Ind Tech Res Inst 晶片封裝結構及晶片封裝方法
US8536458B1 (en) 2009-03-30 2013-09-17 Amkor Technology, Inc. Fine pitch copper pillar package and method
US20110186989A1 (en) * 2010-02-04 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Bump Formation Process
CN102456958A (zh) * 2010-10-23 2012-05-16 富士康(昆山)电脑接插件有限公司 电连接器及其制造方法
US8381965B2 (en) 2010-07-22 2013-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal compress bonding
US8177862B2 (en) 2010-10-08 2012-05-15 Taiwan Semiconductor Manufacturing Co., Ltd Thermal compressive bond head
EP2671251A2 (de) * 2011-02-02 2013-12-11 Pac Tech - Packaging Technologies GmbH Verfahren und vorrichtung zur elektrischen kontaktierung von anschlussflächen zweier substrate
US8492893B1 (en) 2011-03-16 2013-07-23 Amkor Technology, Inc. Semiconductor device capable of preventing dielectric layer from cracking
JP5704994B2 (ja) * 2011-03-31 2015-04-22 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation 半導体接合装置
US9257276B2 (en) 2011-12-31 2016-02-09 Intel Corporation Organic thin film passivation of metal interconnections
WO2013101243A1 (en) 2011-12-31 2013-07-04 Intel Corporation High density package interconnects
US8444043B1 (en) * 2012-01-31 2013-05-21 International Business Machines Corporation Uniform solder reflow fixture
US8967452B2 (en) * 2012-04-17 2015-03-03 Asm Technology Singapore Pte Ltd Thermal compression bonding of semiconductor chips
EP2675252A1 (en) * 2012-06-13 2013-12-18 Polska Wytwornia Papierow Wartosciowych S.A. A method for mounting an electronic element on a substrate with conductive paths sensitive to high temperature
US10011478B2 (en) * 2015-05-18 2018-07-03 Innovative Micro Technology Thermocompression bonding with raised feature
US9842819B2 (en) 2015-08-21 2017-12-12 Invensas Corporation Tall and fine pitch interconnects
CN106254971A (zh) * 2016-09-29 2016-12-21 广东欧珀移动通信有限公司 一种音箱网布的连接方法及音箱网罩及音箱
KR102534735B1 (ko) 2016-09-29 2023-05-19 삼성전자 주식회사 필름형 반도체 패키지 및 그 제조 방법
JP7323508B2 (ja) * 2017-08-02 2023-08-08 ソウル セミコンダクター カンパニー リミテッド ディスプレイ装置、ディスプレイ装置用基板およびディスプレイ装置の修理方法
US11824037B2 (en) * 2020-12-31 2023-11-21 International Business Machines Corporation Assembly of a chip to a substrate
CN113410148B (zh) * 2021-05-26 2022-06-14 深圳市时代速信科技有限公司 一种芯片封装的焊接方法及芯片封装方法
CN118197937B (zh) * 2024-05-17 2024-10-15 成都汉芯国科集成技术有限公司 一种pmu芯片采用的fc倒装焊接工艺

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2414297C3 (de) * 1974-03-25 1980-01-17 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur teilautomatischen Herstellung von Zwischenträgern für Halbleiterbauelemente
DE2431987C2 (de) * 1974-07-03 1983-09-01 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Verbinden eines mit höckerförmigen Anschlußelektroden versehenen Halbleiterbauelements mit einem Träger
US4652336A (en) * 1984-09-20 1987-03-24 Siemens Aktiengesellschaft Method of producing copper platforms for integrated circuits
JPS634652A (ja) 1986-06-25 1988-01-09 Hitachi Ltd 半導体装置
JPH07112041B2 (ja) * 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
JPS63208251A (ja) 1987-02-25 1988-08-29 Nec Corp 集積回路のパツケ−ジ構造
US5299730A (en) 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
JP2805245B2 (ja) 1989-08-28 1998-09-30 エルエスアイ ロジック コーポレーション フリップチップ構造
JP2724033B2 (ja) 1990-07-11 1998-03-09 株式会社日立製作所 半導体モジユール
US5019673A (en) 1990-08-22 1991-05-28 Motorola, Inc. Flip-chip package for integrated circuits
US5438477A (en) 1993-08-12 1995-08-01 Lsi Logic Corporation Die-attach technique for flip-chip style mounting of semiconductor dies
US5508561A (en) 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
US5816478A (en) 1995-06-05 1998-10-06 Motorola, Inc. Fluxless flip-chip bond and a method for making
US6344234B1 (en) * 1995-06-07 2002-02-05 International Business Machines Corportion Method for forming reflowed solder ball with low melting point metal cap
US5985692A (en) * 1995-06-07 1999-11-16 Microunit Systems Engineering, Inc. Process for flip-chip bonding a semiconductor die having gold bump electrodes
US5637920A (en) 1995-10-04 1997-06-10 Lsi Logic Corporation High contact density ball grid array package for flip-chips
US5710071A (en) 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
US5744869A (en) 1995-12-05 1998-04-28 Motorola, Inc. Apparatus for mounting a flip-chip semiconductor device
US6111317A (en) 1996-01-18 2000-08-29 Kabushiki Kaisha Toshiba Flip-chip connection type semiconductor integrated circuit device
US5808360A (en) * 1996-05-15 1998-09-15 Micron Technology, Inc. Microbump interconnect for bore semiconductor dice
JP3431406B2 (ja) 1996-07-30 2003-07-28 株式会社東芝 半導体パッケージ装置
US6121689A (en) 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US5778913A (en) 1997-02-20 1998-07-14 Lucent Technologies Inc. Cleaning solder-bonded flip-chip assemblies
JP3564944B2 (ja) * 1997-05-22 2004-09-15 松下電器産業株式会社 チップの実装方法
US6131795A (en) * 1997-11-10 2000-10-17 Matsushita Electric Industrial Co., Ltd. Thermal compression bonding method of electronic part with solder bump
US5942798A (en) 1997-11-24 1999-08-24 Stmicroelectronics, Inc. Apparatus and method for automating the underfill of flip-chip devices
JP3556450B2 (ja) 1997-12-02 2004-08-18 富士通株式会社 半導体装置
JPH11186338A (ja) * 1997-12-24 1999-07-09 Casio Comput Co Ltd ボンディング装置
JP2000100869A (ja) * 1998-09-22 2000-04-07 Hitachi Ltd 半導体装置およびその製造方法
US6087732A (en) 1998-09-28 2000-07-11 Lucent Technologies, Inc. Bond pad for a flip-chip package
US6127731A (en) * 1999-03-11 2000-10-03 International Business Machines Corporation Capped solder bumps which form an interconnection with a tailored reflow melting point

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101573789B (zh) * 2006-12-28 2016-11-09 英特尔公司 包括其凸块形成位点上的焊料帽的微电子管芯及其制造方法
CN101573789A (zh) * 2006-12-28 2009-11-04 英特尔公司 包括其凸块形成位点上的焊料帽的微电子管芯及其制造方法
CN101965241B (zh) * 2008-11-21 2015-04-22 三菱重工业株式会社 晶片接合装置
CN102386114A (zh) * 2010-09-01 2012-03-21 台湾积体电路制造股份有限公司 芯片接合的方法
CN102386114B (zh) * 2010-09-01 2013-09-11 台湾积体电路制造股份有限公司 芯片接合的方法
CN101993034A (zh) * 2010-11-03 2011-03-30 深港产学研基地 一种高洁净度mems器件气密封装方法
CN103094139A (zh) * 2011-11-07 2013-05-08 矽品精密工业股份有限公司 覆晶接合方法
CN104733414A (zh) * 2013-12-18 2015-06-24 相丰科技股份有限公司 芯片构件与芯片封装体
CN107919856A (zh) * 2016-10-06 2018-04-17 三菱电机株式会社 半导体装置
CN107919856B (zh) * 2016-10-06 2021-03-16 三菱电机株式会社 半导体装置
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CN112151398A (zh) * 2019-06-26 2020-12-29 上海微电子装备(集团)股份有限公司 一种芯片封装方法
CN112151398B (zh) * 2019-06-26 2023-12-15 上海微电子装备(集团)股份有限公司 一种芯片封装方法

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JP2005500672A (ja) 2005-01-06
CN100440496C (zh) 2008-12-03
DE60219779T2 (de) 2007-12-27
ATE360888T1 (de) 2007-05-15
US20020140094A1 (en) 2002-10-03
KR100555354B1 (ko) 2006-02-24
HK1061741A1 (en) 2004-09-30
WO2002080271A2 (en) 2002-10-10
EP1386356A2 (en) 2004-02-04
KR20040055734A (ko) 2004-06-26
US6495397B2 (en) 2002-12-17
DE60219779D1 (de) 2007-06-06
MY122941A (en) 2006-05-31
AU2002245476A1 (en) 2002-10-15
EP1386356B1 (en) 2007-04-25

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