CN107919856A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN107919856A
CN107919856A CN201710909111.8A CN201710909111A CN107919856A CN 107919856 A CN107919856 A CN 107919856A CN 201710909111 A CN201710909111 A CN 201710909111A CN 107919856 A CN107919856 A CN 107919856A
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China
Prior art keywords
substrate
electrode
face
semiconductor device
pad
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CN201710909111.8A
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CN107919856B (zh
Inventor
渡边伸介
西泽弘郎
西泽弘一郎
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

本发明涉及具有场效应晶体管的半导体装置，其目的在于得到能够抑制基板的面积的增加的半导体装置。本发明涉及的半导体装置具有：晶体管，其设置于第1基板；栅极焊盘，其与该晶体管的栅极电极连接；导电性凸块，其设置于该栅极焊盘之上；第2基板，其设置于该第1基板的上方，具有第1面和第2面；第1电极，其从该第1面贯穿至该第2面，在该第2面侧与该导电性凸块连接；电阻，其一端连接于该第1电极的该第1面侧，另一端连接于输入端子；以及第2电极，其与该第1电极相邻设置在该第1面，以不经由该电阻的状态连接于该输入端子，该晶体管的栅极泄漏电流从该第1电极通过该第2基板的该母材及该第2电极而流动至该输入端子。

Description

半导体装置
技术领域
本发明涉及一种半导体装置，该半导体装置具有将高频信号放大的场效应晶体管。
背景技术
就使用了化合物半导体的高频用FET(Field Effect Transistor)而言，有时栅极电极和输入端子经由电阻而连接。该电阻是为了实现振荡的抑制以及施加至FET的栅极电压的调整而设置的。如果FET的温度上升，则有时会产生栅极泄漏电流。如果该栅极泄漏电流流过与栅极电极连接的电阻，则施加至FET的栅极电压由于电压降而上升。其结果，流过FET的漏极电流增加，FET进一步发热。由此，栅极泄漏电流进一步增加。由于其连锁反应，FET有可能受到损伤。
对此，专利文献1公开了一种具有偏置电路的半导体装置，该偏置电路具有NIN元件。NIN元件与电阻并联连接，该电阻连接于栅极偏置供给电源与栅极之间。NIN元件具有在2个N型的导电性接触层之间夹着半绝缘性的半导体层的结构。NIN元件的电阻值伴随着温度上升而降低。因此，如果温度上升，则偏置电路的电阻值减小。此时，即使栅极泄漏电流增加，栅极电位的上升也得到抑制。因此，FET的温度上升得到抑制。
专利文献1：日本特开平11－297941号公报
就专利文献1所示的半导体装置而言，在基板形成FET及NIN元件。此时，将FET和NIN元件靠近配置这一作法有时会受到限制。因此，即使FET处于高温状态，NIN元件的温度有时也难以上升。因此，有可能无法充分地抑制栅极电位的上升。另外，如果基板使用与硅相比带隙宽的化合物半导体，则能够制作适于大功率动作的FET。另一方面，对于由化合物半导体形成的NIN元件，即使FET的温度上升，电阻有时也难以下降。因此，有可能无法充分利用NIN元件来抑制栅极电位的上升。
另外，为了形成NIN元件而增加基板的面积。因此，制造成本增加。另外，为了充分地得到FET的性能，期望将匹配电路形成于FET的附近。但是，如果在FET的附近形成NIN元件，则有时无法在FET的附近配置匹配电路。此时，有可能抑制FET的性能。
发明内容
本发明就是为了解决上述课题而提出的，目的在于得到一种能够抑制基板的面积的增加的半导体装置。
本发明涉及的半导体装置具有：第1基板；晶体管，其设置于该第1基板；栅极焊盘，其设置于该第1基板的上表面，与该晶体管的栅极电极连接；导电性凸块，其设置于该栅极焊盘之上；第2基板，其设置于该第1基板的上方，具有第1面和第2面，该第2面是与该第1面相反的面；第1电极，其从该第1面贯通至该第2面，在该第2面侧与该导电性凸块连接；电阻，其一端连接于该第1电极的该第1面侧，另一端连接于输入端子；以及第2电极，其与该第1电极相邻设置在该第1面，以不经由该电阻的状态连接于该输入端子，该第1电极和该第2电极由该第2基板的母材隔开，从该晶体管的漏极电极流动至该栅极电极的栅极泄漏电流从该第1电极通过该第2基板的该母材及该第2电极而流动至该输入端子。
发明的效果
就本发明涉及的半导体装置而言，向栅极焊盘经由导电性凸块连接第2基板。如果晶体管发热，则第2基板的母材的电阻值降低。此时，从晶体管的漏极电极流动至栅极电极的栅极泄漏电流从第1电极通过第2基板的母材而流动至第2电极。因此，抑制了因栅极泄漏电流流过第1电阻所产生的电压降。因此，抑制了FET的发热。另外，无需在第1基板形成用于抑制栅极泄漏电流的元件。因此，能够抑制第1基板的面积的增加。
附图说明
图1是实施方式1涉及的半导体装置的剖视图。
图2是实施方式1涉及的第1基板的俯视图。
图3是对比例涉及的半导体装置的剖视图。
图4是表示硅的电导率的温度特性的图。
图5是实施方式1的第1变形例涉及的第2基板的俯视图。
图6是实施方式1的第1变形例涉及的第2基板的仰视图。
图7是实施方式1的第2变形例涉及的半导体装置的剖视图。
图8是对比例涉及的半导体装置的剖视图。
图9是实施方式2涉及的半导体装置的剖视图。
图10是实施方式3涉及的半导体装置的剖视图。
图11是实施方式4涉及的半导体装置的剖视图。
图12是实施方式4的第1变形例涉及的半导体装置的剖视图。
图13是实施方式4的第2变形例涉及的半导体装置的剖视图。
标号的说明
80、280、380、480、580、680、780半导体装置，10第1基板，12晶体管，13栅极电极，14漏极电极，11栅极焊盘，30导电性凸块，20、120、320、520、720第2基板，61第1面，62第2面，44、444、744第1电极，50输入端子，51电阻，45、345、645第2电极，41、641第2键合焊盘，21、121、421、721第1焊盘，528第1凹部，729第2凹部，126匹配电路，260树脂。
具体实施方式
参照附图对本发明的实施方式涉及的半导体装置进行说明。对相同或者相对应的结构要素标注相同的标号，有时省略重复说明。
实施方式1.
图1是实施方式1涉及的半导体装置的剖视图。本实施方式涉及的半导体装置80具有第1基板10。在第1基板10设置晶体管12。在本实施方式中，晶体管12是高频用FET。第1基板10由化合物半导体形成。使用砷化镓、氮化镓、磷化铟等化合物半导体作为第1基板10的材料。
在第1基板10的上表面设置栅极焊盘11。栅极焊盘11通过配线15与晶体管12的栅极电极13连接。在第1基板10的上表面设置漏极焊盘18。漏极焊盘18通过配线17与晶体管12的漏极电极14连接。在第1基板10的背面设置有接地金属52。向接地金属52施加接地电位。
在栅极焊盘11之上设置导电性凸块30。另外，在漏极焊盘18之上设置导电性凸块31。能够使用金、铜或者焊料作为导电性凸块30、31。导电性凸块30、31的材料并不限定于此。
在第1基板10的上方设置第2基板20。第2基板20具有第1面61和第2面62，该第2面是与第1面61相反的面。第2基板20由电阻率大于或等于100Ωcm的硅形成。作为第2基板20的材料的硅是高频用基板所使用的本征硅。第2基板20以第2面62与第1基板10的上表面相对的方式设置于导电性凸块30、31之上。第2基板20通过导电性凸块30、31安装于第1基板10的上方。
在第2基板20形成第1电极44。第1电极44从第1面61贯通至第2面62。另外，第1电极44在第2面62侧与导电性凸块30连接。第1电极44在第2面62具有第1焊盘21。第1焊盘21与导电性凸块30连接。另外，第1电极44在第1面61具有第1键合焊盘40。第1键合焊盘40是用于进行导线键合的焊盘。第1焊盘21和第1键合焊盘40通过从第1面61贯通至第2面62的第1通路孔22而导通。
半导体装置80具有电阻51。电阻51的一端连接于第1电极44的第1面61侧。电阻51的一端通过配线53与第1键合焊盘40连接。电阻51的另一端与输入端子50连接。从输入端子50进行高频信号的输入及栅极电压的施加。通过电阻51能够实现振荡的抑制及施加至晶体管12的栅极电压的调整。
在第2基板20形成第2电极45。在本实施方式中，第2电极45是设置于第1面61的第2键合焊盘41。第2电极45与第1电极44相邻设置。第2电极45通过配线54与输入端子50连接。第2电极45以不经由电阻51的状态与输入端子50连接。
在本实施方式中，第2电极45是设置于第1面61的第2键合焊盘41。第2电极45的形状并不限定于此。第2电极45只要至少设置于第1面61、且其第1面61侧连接于输入端子50即可。第2电极45不与其他焊盘及晶体管12连接。第2电极45和第1电极44由第2基板20的母材隔开。第2电极45处于浮置状态。
第2基板20在第2面62具有第3焊盘23。第3焊盘23与导电性凸块31连接。另外，第2基板20在第1面61具有第3键合焊盘43。第3焊盘23和第3键合焊盘43通过从第1面61贯通至第2面62的第3通路孔24而连接。第3键合焊盘43通过配线55连接于输出端子56。
图2是实施方式1涉及的第1基板的俯视图。在第1基板10的上表面交替配置有漏极电极14和源极电极16。漏极电极14及源极电极16在俯视时为长方形。在漏极电极14和源极电极16之间配置有栅极电极13。在配置栅极电极13、漏极电极14及源极电极16的区域的一端配置栅极焊盘11和源极焊盘19。在配置栅极电极13、漏极电极14及源极电极16的区域的另一端配置漏极焊盘18。
图3是对比例涉及的半导体装置的剖视图。对比例涉及的半导体装置81具有第1基板10。第1基板10的构造与半导体装置80相同。半导体装置81不具有第2基板20。电阻51的一端经由配线53而连接于栅极焊盘11。输入端子50连接于电阻51的另一端。漏极焊盘18经由配线55连接于输出端子56。
如果晶体管12被施加栅极电压，漏极电流流动，则晶体管12发热。通常，对于由化合物半导体形成的FET，如果FET的温度上升为大于或等于一定值，则产生从漏极电极14向栅极电极13流动的栅极泄漏电流。该栅极泄漏电流通过栅极焊盘11，经由电阻51向输入端子50流动。如果栅极泄漏电流流过电阻51，则施加至晶体管12的栅极电压由于电压降而上升。其结果，流过晶体管12的漏极电流增加。因此，晶体管12进一步发热。由此，栅极泄漏电流进一步增加。由于其连锁反应，晶体管12有可能受到损伤。
与此相对，对本实施方式涉及的半导体装置80的动作进行说明。在晶体管12的温度为常温的情况下，晶体管12的增益高。对于增益高的FET，有可能产生振荡。在本实施方式中，通过与输入端子50连接的电阻51，能够抑制晶体管12的振荡。另外，在常温下第2基板20的母材即硅的电导率低。因此，在第1电极44和第2电极45之间不流过电流。
如果向输入端子50输入栅极电压及大功率的高频信号，则晶体管12的温度上升。如果晶体管12处于高温状态，则增益减少。此时，降低了引起振荡的可能性。另一方面，如果晶体管12处于高温状态，则产生栅极泄漏电流。栅极泄漏电流从漏极电极14向栅极电极13流动，通过栅极焊盘11、导电性凸块30而朝向第1电极44流动。
此时，第1基板10所产生的热经由第1基板10与第2基板20之间的空气及导电性凸块30、31而传递至第2基板20。其结果，第2基板20的温度上升。如果第2基板20的温度上升，则在硅的内部产生本征载流子。因此，第2基板20的电导率上升。此时，通过将第2电极45与第1电极44相邻配置，从而在第1电极44与第2电极45之间形成电流的路径。
此时，从漏极电极14流动至栅极电极13的栅极泄漏电流变为从第1电极44经由第2基板20的母材及第2电极45而流动至输入端子50。栅极泄漏电流经由第2电极45从输入端子50朝向外部流动。其结果，流过电阻51的栅极泄漏电流减少，抑制了因电阻51引起的电压降。因此，抑制了栅极电压的上升，抑制了晶体管12的进一步发热。因此，能够防止因发热对半导体装置80造成的损伤。
这里，第1电极44与第2电极45之间的电流的路径为低电阻即可。因此，第2电极45靠近第1电极44而配置。优选第1电极44与第2电极45之间的间隔小于或等于100μm。
另外，第1基板10所产生的热经由第1基板10与第2基板20之间的空气及导电性凸块30、31而传递至第2基板20。由于空气难以传递热，因此第2基板20的温度不会上升至晶体管12的温度。但是，导电性凸块30、31的高度通常为几μm至几十μm。因此，能够使第1基板10和第2基板20靠近。因此，能够使第2基板20的温度充分上升，以使第2基板20的电导率增加。
通过基于有限元法的热解析计算出晶体管12发热时的第2基板20的温度。在热解析中，将第1基板10和第2基板20的间隔设为了10μm。另外，将流过栅极泄漏电流时的晶体管12的温度设为了摄氏190度。此时，得到第2基板20的温度大于或等于摄氏140度的计算结果。
图4是表示硅的电导率的温度特性的图。硅在常温下不具有导电性。硅如果超过摄氏130度，则急速地产生本征载流子。其结果，电导率增加。根据热解析，晶体管12发热，由此第2基板20成为140度。因此，由于晶体管12的发热，本征载流子在第2基板20急速地增加。其结果，能够使第2基板20的电导率增加，在第1电极44与第2电极45之间形成电流路径。因此，能够使栅极泄漏电流经由硅流动至第2电极45。
在本实施方式中，经由导电性凸块30、31而在作为发热源的晶体管12的正上方配置有第2基板20。导电性凸块30、31的高度能够变更。因此，第1基板10和第2基板20的间隔能够变更。因此，能够控制第2基板20的温度。在希望增加第2基板20的电导率的情况下，使第2基板20接近第1基板10。由此，变得容易从第1基板10向第2基板20传递热。因此，第2基板20的温度上升，电导率增加。
另外，在第1基板10的温度低的状态下，即使在想要形成朝向第2电极45的电流路径的情况下，也缩窄第1基板10和第2基板20的间隔。由此，变得容易传递来自第1基板10的热，第2基板20的温度变得容易大于或等于130度。因此，越是缩窄第1基板10和第2基板20的间隔，越能够在第1基板10的温度低的状态下，形成朝向第2电极45的电流路径。由此，在使用具有在比通常的FET低的温度下栅极泄漏电流开始流动的特性的FET作为晶体管12的情况下，也能够抑制栅极电压的上升。
另外，通过对第1电极44和第2电极45的间隔进行变更，从而能够变更第1电极44与第2电极45之间的电阻值。通过使第1电极44和第2电极45的间隔变近，从而能够容易地使电流在第1电极44与第2电极45之间流动。另外，在本实施方式中，第2电极45配置于第1电极44与第3键合焊盘43之间。第1电极44和第2电极45的位置关系也可以是上述以外的情形。
在本实施方式中，能够对第1电极44和第2电极45的位置关系及第1基板10和第2基板20的间隔进行调整。由此，能够得到与栅极泄漏电流开始流动的温度等晶体管12的特性匹配的半导体装置80。
作为与晶体管12的特性匹配的半导体装置80的调整方法，也可以对第2基板20的材料进行变更。在本实施方式中，第2基板20是常温下的电阻率大于或等于100Ωcm的硅。由此，能够防止在常温下电流流过第2电极45。在即使常温下的电阻率低也没有问题的情况下，也可以使用电阻率不足100Ωcm的硅。相反，在需要直至第2基板20变为高温为止维持高电阻率的情况下，也可以使用宽带隙半导体作为第2基板20的材料。
为了抑制晶体管12的温度上升，想到的是在第1基板10将热敏电阻与电阻51并联连接的方法。但是，根据该方法，为了形成热敏电阻，第1基板10的面积变大。
与此相对，本实施方式涉及的半导体装置80通过在第1基板10的上方设置第2基板20，从而能够抑制晶体管12的温度上升。将第1基板10和第2基板20连接的导电性凸块30、31分别设置于栅极焊盘11及漏极焊盘18之上。栅极焊盘11及漏极焊盘18是用于导线键合的焊盘。栅极焊盘11及漏极焊盘18通常设置于基板之上。
因此，在本实施方式中，不需要为了抑制晶体管12的温度上升而在第1基板10设置新的要素。因此，无需扩大第1基板10的面积。因此，能够抑制第1基板10的面积的增加。特别是，大功率用FET所使用的化合物半导体基板与硅基板相比大多是高价的。因此，能够抑制由化合物半导体形成的第1基板10的面积的增加，从而能够降低制造成本。
图5是实施方式1的第1变形例涉及的第2基板的俯视图。图6是实施方式1的第1变形例涉及的第2基板的仰视图。作为本实施方式的第1变形例，第2基板120也可以具有抑制发热以外的功能。例如，也可以在第2基板120形成匹配电路等其他电路。
在第1变形例涉及的第2基板120处，在第1面61设置第1键合焊盘40。在第2面62设置第4焊盘125。第1键合焊盘40和第4焊盘125由第1通路孔122连接。此外，在图5及图6中，为了方便，将第1通路孔122的位置由虚线示出。另外，就第1变形例涉及的第2基板120而言，第1键合焊盘40、第2键合焊盘41及第3键合焊盘43的配置与第2基板20不同。
在第1变形例涉及的第2基板120处，在第2面62形成有匹配电路126。匹配电路126连接于第4焊盘125与第1焊盘121之间。匹配电路126是曲折式电感器(meander inductor)。匹配电路126也可以不是曲折式电感器。
通常，为了使FET具有高性能，优选将匹配电路配置于FET的附近。另一方面，对于第2基板120，为了对发热的晶体管12的温度进行感知，也需要靠近晶体管12而配置。在本实施方式中，在第2基板120设置匹配电路126。因此，能够将第2基板120和匹配电路126一起靠近晶体管12而配置。因此，能够同时得到FET的高性能化、抑制因发热引起的损伤的效果。另外，通过在第2基板120设置匹配电路126，从而变得不需要在第1基板10设置匹配电路。因此，能够削减第1基板10的面积。因此，能够实现FET的高集成化。在第2基板120形成的电路不限定于匹配电路126。
图7是实施方式1的第2变形例涉及的半导体装置的剖视图。就第2变形例涉及的半导体装置280而言，第1基板10和第2基板20由树脂260进行封装。其他构造与半导体装置80相同。第1基板10和第2基板20由树脂260进行封装，从而能够保护半导体装置280免受冲击及高湿度的空气的影响。树脂260是环氧树脂。
图8是对比例涉及的半导体装置的剖视图。对比例涉及的半导体装置281的第1基板10由树脂261进行封装。其他构造与对比例涉及的半导体装置81相同。就对比例涉及的半导体装置281而言，如果将第1基板10由树脂261进行封装，则晶体管12和树脂261接触。因此，晶体管12的性能有时会降低。
对此，就第2变形例涉及的半导体装置280而言，在第1基板10之上设置导电性凸块30、31。在导电性凸块30、31之上设置第2基板20。因此，在晶体管12的周围形成中空区域。即，能够将第2基板20用作第1基板10的罩部。由此，能够对半导体装置280进行封装而不会降低晶体管12的性能。
上述变形能够适当应用于以下的实施方式涉及的半导体装置。此外，对于以下的实施方式涉及的半导体装置，由于与实施方式1的共同点较多，因此以与实施方式1的区别点为中心进行说明。
实施方式2.
图9是实施方式2涉及的半导体装置的剖视图。本实施方式涉及的半导体装置380的第2电极345的构造与半导体装置80不同。其他构造与实施方式1相同。第2电极345从第2基板320的第1面61贯通至第2面62。第2电极345在第1面61具有第2键合焊盘41。另外，第2电极345在第2面62具有第2焊盘342。第2键合焊盘41和第2焊盘342由第2通路孔327连接。第2电极345和第1电极44由第2基板320的母材隔开。
第2基板320的母材与第2基板20相同。如果第2基板320成为高温状态，则第2基板320的电导率上升，栅极泄漏电流朝向第2电极345而流动。电流路径的截面面积越大，第1电极44与第2电极345之间的电阻值越小。在本实施方式中，栅极泄漏电流在第1通路孔22与第2通路孔327之间流动。因此，与实施方式1相比，电流路径的截面面积变大。因此，与实施方式1相比，能够降低第1电极44与第2电极345之间的电阻值。因此，容易使栅极泄漏电流朝向第2电极345流动。因此，能够提高抑制晶体管12发热的效果。
实施方式3.
图10是实施方式3涉及的半导体装置的剖视图。本实施方式涉及的半导体装置480的第1电极444的构造与半导体装置80不同。其他构造与实施方式1相同。第1电极444具有第1焊盘421，该第1焊盘421与导电性凸块30连接，设置于第2面62。第1焊盘421延伸至第2键合焊盘41的正下方。第1焊盘421在俯视时形成至与第2键合焊盘41重叠的位置。
在实施方式1及实施方式2中，在第1电极44与第2电极45、345之间流动的栅极泄漏电流主要沿与第1面61平行的方向流动。与此相对，在本实施方式中，能够使栅极泄漏电流沿从第2面62朝向第1面61的方向流动。通过扩大在俯视时第1焊盘421和第2键合焊盘41重叠的面积，从而能够增大电流路径的截面面积。因此，能够降低从第1电极444向第2电极45的栅极泄漏电流的电流路径的电阻值。
实施方式4.
图11是实施方式4涉及的半导体装置的剖视图。本实施方式涉及的半导体装置580的第2基板520的形状与实施方式3不同。在第2基板520的第1面61形成第1凹部528。第2电极45设置于第1凹部528的底面。其他的形状与实施方式3相同。第1凹部528是对第2基板520的第1面61进行蚀刻而形成的。
本实施方式涉及的第2基板520的设置有第2键合焊盘41的部分比周围薄。因此，第1焊盘421和第2键合焊盘41的间隔比实施方式3小。因此，能够将从第1电极444向第2电极45的栅极泄漏电流的电流路径进一步低电阻化。
图12是实施方式4的第1变形例涉及的半导体装置的剖视图。第1变形例涉及的半导体装置680的第2电极645的形状与半导体装置580不同。第2电极645具有第2键合焊盘641。第2键合焊盘641将第1凹部528填埋。
第2基板520的形成有第1凹部528的部分比周围薄。第2键合焊盘641将第1凹部528填充，从而能够对第2基板520进行加强。另外，对于半导体装置580，在第1凹部528的内部对第2键合焊盘41实施导线键合。与此相对，对于第1变形例涉及的半导体装置680，第1凹部528由第2键合焊盘641进行填充。因此，能够在第1凹部528的外部实施导线键合。因此，导线键合变得容易。
图13是实施方式4的第2变形例涉及的半导体装置的剖视图。第2变形例涉及的半导体装置780在第2基板720的第2面62形成有第2凹部729。第2凹部729形成于第2键合焊盘41的正下方。另外，第1电极744在第2面62具有第1焊盘721。第1焊盘721与导电性凸块30连接。另外，第1焊盘721将第2凹部729填埋。
如第2变形例所示，也可以在第2面62设置第2凹部729，将第2凹部729由第1焊盘721进行填充。在第2变形例中，也能够得到与第1变形例相同的效果。另外，也可以同时设置第1凹部528和第2凹部729。此外，也可以将在各实施方式中说明的技术特征适当进行组合而使用。

Claims (12)

1.一种半导体装置，其特征在于，具有：
第1基板；
晶体管，其设置于所述第1基板；
栅极焊盘，其设置于所述第1基板的上表面，与所述晶体管的栅极电极连接；
导电性凸块，其设置于所述栅极焊盘之上；
第2基板，其设置于所述第1基板的上方，具有第1面和第2面，该第2面是与所述第1面相反的面；
第1电极，其从所述第1面贯通至所述第2面，在所述第2面侧与所述导电性凸块连接；
电阻，其一端连接于所述第1电极的所述第1面侧，另一端连接于输入端子；以及
第2电极，其与所述第1电极相邻设置在所述第1面，以不经由所述电阻的状态连接于所述输入端子，
所述第1电极和所述第2电极由所述第2基板的母材隔开，
从所述晶体管的漏极电极流动至所述栅极电极的栅极泄漏电流从所述第1电极通过所述第2基板的所述母材及所述第2电极而流动至所述输入端子。
2.根据权利要求1所述的半导体装置，其特征在于，
所述第1电极与所述第2电极之间的间隔小于或等于100μm。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述第2电极是设置于所述第1面的第2键合焊盘。
4.根据权利要求1或2所述的半导体装置，其特征在于，
所述第2电极从所述第1面贯通至所述第2面。
5.根据权利要求3所述的半导体装置，其特征在于，
所述第1电极具有第1焊盘，该第1焊盘与所述导电性凸块连接，设置于所述第2面，
所述第1焊盘延伸至所述第2键合焊盘的正下方。
6.根据权利要求5所述的半导体装置，其特征在于，
所述第2基板的设置有所述第2键合焊盘的部分比周围薄。
7.根据权利要求6所述的半导体装置，其特征在于，
在所述第1面形成第1凹部，
所述第2键合焊盘将所述第1凹部填埋。
8.根据权利要求6或7所述的半导体装置，其特征在于，
在所述第2面，在所述第2键合焊盘的正下方形成第2凹部，
所述第1焊盘将所述第2凹部填埋。
9.根据权利要求1至8中任一项所述的半导体装置，其特征在于，
所述第2基板的所述母材是电阻率大于或等于100Ωcm的硅。
10.根据权利要求1至9中任一项所述的半导体装置，其特征在于，
在所述第2基板形成有匹配电路。
11.根据权利要求1至10中任一项所述的半导体装置，其特征在于，
所述第1基板和所述第2基板由树脂进行封装。
12.根据权利要求1至11中任一项所述的半导体装置，其特征在于，
所述第1基板由化合物半导体形成。
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